Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	67152137	1697970	0	0
clk_enables_rd_A	67152137	11432	0	0
clk_hints_rd_A	67152137	10049	0	0
extclk_ctrl_rd_A	67152137	15454	0	0
extclk_ctrl_regwen_rd_A	67152137	9638	0	0
jitter_enable_rd_A	67152137	15479	0	0
jitter_regwen_rd_A	67152137	9997	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	1697970	0	0
T2	188614	66067	0	0
T13	0	212164	0	0
T18	2364	0	0	0
T19	33852	0	0	0
T20	1616	0	0	0
T21	1900	0	0	0
T22	1571	0	0	0
T23	99388	0	0	0
T26	0	38304	0	0
T27	1661	0	0	0
T28	1120	0	0	0
T29	74290	0	0	0
T32	0	71699	0	0
T68	0	50219	0	0
T69	0	44013	0	0
T70	0	98732	0	0
T71	0	83762	0	0
T72	0	119798	0	0
T73	0	124312	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	11432	0	0
T9	61628	0	0	0
T10	134183	0	0	0
T11	96694	0	0	0
T26	0	1524	0	0
T52	0	1	0	0
T87	2250	1	0	0
T88	1528	0	0	0
T89	1933	0	0	0
T90	2453	0	0	0
T91	2017	0	0	0
T116	3211	0	0	0
T117	1146	0	0	0
T144	0	4	0	0
T145	0	1	0	0
T146	0	9	0	0
T147	0	7	0	0
T148	0	3	0	0
T149	0	12	0	0
T150	0	2	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	10049	0	0
T18	2364	7	0	0
T19	33852	0	0	0
T20	1616	0	0	0
T21	1900	0	0	0
T22	1571	0	0	0
T23	99388	0	0	0
T26	0	1186	0	0
T27	1661	0	0	0
T28	1120	0	0	0
T29	74290	0	0	0
T52	0	4	0	0
T83	1998	0	0	0
T87	0	10	0	0
T145	0	2	0	0
T146	0	5	0	0
T147	0	15	0	0
T148	0	9	0	0
T149	0	7	0	0
T151	0	3	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	15454	0	0
T3	76072	0	0	0
T23	99388	0	0	0
T26	0	1734	0	0
T27	1661	33	0	0
T28	1120	0	0	0
T29	74290	0	0	0
T58	0	35	0	0
T83	1998	0	0	0
T84	1234	0	0	0
T85	2864	0	0	0
T86	1012	0	0	0
T87	2250	0	0	0
T89	0	7	0	0
T91	0	72	0	0
T152	0	13	0	0
T153	0	11	0	0
T154	0	48	0	0
T155	0	16	0	0
T156	0	56	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	9638	0	0
T26	125378	1275	0	0
T36	1577	0	0	0
T37	1442	0	0	0
T69	0	1654	0	0
T103	37633	0	0	0
T156	2040	0	0	0
T157	0	8	0	0
T158	0	14	0	0
T159	0	59	0	0
T160	0	35	0	0
T161	0	39	0	0
T162	0	38	0	0
T163	0	12	0	0
T164	0	14	0	0
T165	1118	0	0	0
T166	1005	0	0	0
T167	2415	0	0	0
T168	1997	0	0	0
T169	953	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	15479	0	0
T18	2364	98	0	0
T19	33852	0	0	0
T20	1616	0	0	0
T21	1900	0	0	0
T22	1571	0	0	0
T23	99388	0	0	0
T26	0	1271	0	0
T27	1661	0	0	0
T28	1120	0	0	0
T29	74290	0	0	0
T52	0	102	0	0
T83	1998	0	0	0
T87	0	95	0	0
T144	0	119	0	0
T145	0	119	0	0
T146	0	231	0	0
T147	0	106	0	0
T148	0	119	0	0
T151	0	104	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	9997	0	0
T26	125378	1445	0	0
T36	1577	0	0	0
T37	1442	0	0	0
T65	0	3	0	0
T69	0	1674	0	0
T73	0	4745	0	0
T102	0	25	0	0
T103	37633	0	0	0
T156	2040	0	0	0
T165	1118	0	0	0
T166	1005	0	0	0
T167	2415	0	0	0
T168	1997	0	0	0
T169	953	0	0	0
T170	0	798	0	0
T171	0	50	0	0
T172	0	12	0	0
T173	0	14	0	0
T174	0	27	0	0