Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T4,T2,T23
1	0	Covered	T5,T1,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	671521370	762102	0	0
DstReqKnown_A	1304529086	1281507388	0	0
SrcAckBusyChk_A	671521370	150463	0	0
SrcBusyKnown_A	671521370	648199050	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671521370	762102	0	0
T1	866700	1557	0	0
T2	1886140	11881	0	0
T3	0	1568	0	0
T4	692400	2303	0	0
T5	1818400	2589	0	0
T6	13360	0	0	0
T7	21290	0	0	0
T9	0	1235	0	0
T10	0	2047	0	0
T16	11280	0	0	0
T17	16640	0	0	0
T18	23640	0	0	0
T19	338520	592	0	0
T23	0	4061	0	0
T29	0	1418	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1304529086	1281507388	0	0
T1	1190644	1190128	0	0
T2	5400654	5378534	0	0
T4	414006	21898	0	0
T5	981060	979610	0	0
T6	34062	33206	0	0
T7	13316	12208	0	0
T16	28396	27740	0	0
T17	10920	10522	0	0
T18	15404	14676	0	0
T19	436552	435724	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671521370	150463	0	0
T1	866700	320	0	0
T2	1886140	1480	0	0
T3	0	420	0	0
T4	692400	280	0	0
T5	1818400	300	0	0
T6	13360	0	0	0
T7	21290	0	0	0
T9	0	220	0	0
T10	0	240	0	0
T16	11280	0	0	0
T17	16640	0	0	0
T18	23640	0	0	0
T19	338520	120	0	0
T23	0	571	0	0
T29	0	400	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	671521370	648199050	0	0
T1	866700	866250	0	0
T2	1886140	1874480	0	0
T4	692400	33280	0	0
T5	1818400	1815860	0	0
T6	13360	12970	0	0
T7	21290	19320	0	0
T16	11280	10970	0	0
T17	16640	15980	0	0
T18	23640	22290	0	0
T19	338520	337830	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T5,T1,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	67152137	44105	0	0
DstReqKnown_A	195988429	192055403	0	0
SrcAckBusyChk_A	67152137	12348	0	0
SrcBusyKnown_A	67152137	64819905	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	44105	0	0
T1	86670	112	0	0
T2	188614	734	0	0
T3	0	119	0	0
T4	69240	114	0	0
T5	181840	159	0	0
T6	1336	0	0	0
T7	2129	0	0	0
T9	0	82	0	0
T10	0	145	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	41	0	0
T23	0	180	0	0
T29	0	108	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195988429	192055403	0	0
T1	180869	180776	0	0
T2	183877	183072	0	0
T4	69240	3328	0	0
T5	140003	139758	0	0
T6	5131	4983	0	0
T7	2044	1854	0	0
T16	4335	4214	0	0
T17	1664	1598	0	0
T18	2364	2229	0	0
T19	66319	66185	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	12348	0	0
T1	86670	32	0	0
T2	188614	145	0	0
T3	0	42	0	0
T4	69240	20	0	0
T5	181840	30	0	0
T6	1336	0	0	0
T7	2129	0	0	0
T9	0	22	0	0
T10	0	24	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	12	0	0
T23	0	40	0	0
T29	0	40	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	64819905	0	0
T1	86670	86625	0	0
T2	188614	187448	0	0
T4	69240	3328	0	0
T5	181840	181586	0	0
T6	1336	1297	0	0
T7	2129	1932	0	0
T16	1128	1097	0	0
T17	1664	1598	0	0
T18	2364	2229	0	0
T19	33852	33783	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T5,T1,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	67152137	63227	0	0
DstReqKnown_A	97171660	96179629	0	0
SrcAckBusyChk_A	67152137	12348	0	0
SrcBusyKnown_A	67152137	64819905	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	63227	0	0
T1	86670	159	0	0
T2	188614	1161	0	0
T3	0	157	0	0
T4	69240	161	0	0
T5	181840	257	0	0
T6	1336	0	0	0
T7	2129	0	0	0
T9	0	120	0	0
T10	0	208	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	60	0	0
T23	0	278	0	0
T29	0	146	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97171660	96179629	0	0
T1	90402	90388	0	0
T2	917715	915623	0	0
T4	20675	1667	0	0
T5	69948	69879	0	0
T6	2659	2625	0	0
T7	975	927	0	0
T16	2121	2107	0	0
T17	820	799	0	0
T18	1129	1115	0	0
T19	33141	33093	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	12348	0	0
T1	86670	32	0	0
T2	188614	145	0	0
T3	0	42	0	0
T4	69240	20	0	0
T5	181840	30	0	0
T6	1336	0	0	0
T7	2129	0	0	0
T9	0	22	0	0
T10	0	24	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	12	0	0
T23	0	40	0	0
T29	0	40	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	64819905	0	0
T1	86670	86625	0	0
T2	188614	187448	0	0
T4	69240	3328	0	0
T5	181840	181586	0	0
T6	1336	1297	0	0
T7	2129	1932	0	0
T16	1128	1097	0	0
T17	1664	1598	0	0
T18	2364	2229	0	0
T19	33852	33783	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T5,T1,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	67152137	101056	0	0
DstReqKnown_A	48585436	48089527	0	0
SrcAckBusyChk_A	67152137	12348	0	0
SrcBusyKnown_A	67152137	64819905	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	101056	0	0
T1	86670	246	0	0
T2	188614	2041	0	0
T3	0	236	0	0
T4	69240	272	0	0
T5	181840	441	0	0
T6	1336	0	0	0
T7	2129	0	0	0
T9	0	194	0	0
T10	0	356	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	96	0	0
T23	0	481	0	0
T29	0	208	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48585436	48089527	0	0
T1	45201	45194	0	0
T2	458856	457810	0	0
T4	10338	834	0	0
T5	34974	34939	0	0
T6	1329	1312	0	0
T7	488	464	0	0
T16	1060	1053	0	0
T17	410	400	0	0
T18	564	557	0	0
T19	16570	16546	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	12348	0	0
T1	86670	32	0	0
T2	188614	145	0	0
T3	0	42	0	0
T4	69240	20	0	0
T5	181840	30	0	0
T6	1336	0	0	0
T7	2129	0	0	0
T9	0	22	0	0
T10	0	24	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	12	0	0
T23	0	40	0	0
T29	0	40	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	64819905	0	0
T1	86670	86625	0	0
T2	188614	187448	0	0
T4	69240	3328	0	0
T5	181840	181586	0	0
T6	1336	1297	0	0
T7	2129	1932	0	0
T16	1128	1097	0	0
T17	1664	1598	0	0
T18	2364	2229	0	0
T19	33852	33783	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T5,T1,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	67152137	43113	0	0
DstReqKnown_A	209757057	205637955	0	0
SrcAckBusyChk_A	67152137	12348	0	0
SrcBusyKnown_A	67152137	64819905	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	43113	0	0
T1	86670	107	0	0
T2	188614	711	0	0
T3	0	115	0	0
T4	69240	93	0	0
T5	181840	184	0	0
T6	1336	0	0	0
T7	2129	0	0	0
T9	0	81	0	0
T10	0	120	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	41	0	0
T23	0	175	0	0
T29	0	102	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209757057	205637955	0	0
T1	188411	188314	0	0
T2	195535	194308	0	0
T4	72128	3459	0	0
T5	169840	169586	0	0
T6	5346	5191	0	0
T7	2129	1932	0	0
T16	4515	4389	0	0
T17	1734	1665	0	0
T18	2463	2322	0	0
T19	69085	68944	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	12348	0	0
T1	86670	32	0	0
T2	188614	145	0	0
T3	0	42	0	0
T4	69240	20	0	0
T5	181840	30	0	0
T6	1336	0	0	0
T7	2129	0	0	0
T9	0	22	0	0
T10	0	24	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	12	0	0
T23	0	40	0	0
T29	0	40	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	64819905	0	0
T1	86670	86625	0	0
T2	188614	187448	0	0
T4	69240	3328	0	0
T5	181840	181586	0	0
T6	1336	1297	0	0
T7	2129	1932	0	0
T16	1128	1097	0	0
T17	1664	1598	0	0
T18	2364	2229	0	0
T19	33852	33783	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T5,T1,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	67152137	60645	0	0
DstReqKnown_A	100761961	98791180	0	0
SrcAckBusyChk_A	67152137	11848	0	0
SrcBusyKnown_A	67152137	64819905	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	60645	0	0
T1	86670	156	0	0
T2	188614	1171	0	0
T3	0	155	0	0
T4	69240	84	0	0
T5	181840	246	0	0
T6	1336	0	0	0
T7	2129	0	0	0
T9	0	142	0	0
T10	0	196	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	59	0	0
T23	0	158	0	0
T29	0	145	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100761961	98791180	0	0
T1	90439	90392	0	0
T2	944344	938454	0	0
T4	34622	1661	0	0
T5	75765	75643	0	0
T6	2566	2492	0	0
T7	1022	927	0	0
T16	2167	2107	0	0
T17	832	799	0	0
T18	1182	1115	0	0
T19	33161	33094	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	11848	0	0
T1	86670	32	0	0
T2	188614	145	0	0
T3	0	42	0	0
T4	69240	10	0	0
T5	181840	30	0	0
T6	1336	0	0	0
T7	2129	0	0	0
T9	0	22	0	0
T10	0	24	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	12	0	0
T23	0	20	0	0
T29	0	40	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	64819905	0	0
T1	86670	86625	0	0
T2	188614	187448	0	0
T4	69240	3328	0	0
T5	181840	181586	0	0
T6	1336	1297	0	0
T7	2129	1932	0	0
T16	1128	1097	0	0
T17	1664	1598	0	0
T18	2364	2229	0	0
T19	33852	33783	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T4,T2,T23
1	0	Covered	T5,T1,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	67152137	62905	0	0
DstReqKnown_A	195988429	192055403	0	0
SrcAckBusyChk_A	67152137	17785	0	0
SrcBusyKnown_A	67152137	64819905	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	62905	0	0
T1	86670	109	0	0
T2	188614	762	0	0
T3	0	121	0	0
T4	69240	232	0	0
T5	181840	158	0	0
T6	1336	0	0	0
T7	2129	0	0	0
T9	0	82	0	0
T10	0	146	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	41	0	0
T23	0	353	0	0
T29	0	106	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195988429	192055403	0	0
T1	180869	180776	0	0
T2	183877	183072	0	0
T4	69240	3328	0	0
T5	140003	139758	0	0
T6	5131	4983	0	0
T7	2044	1854	0	0
T16	4335	4214	0	0
T17	1664	1598	0	0
T18	2364	2229	0	0
T19	66319	66185	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	17785	0	0
T1	86670	32	0	0
T2	188614	151	0	0
T3	0	42	0	0
T4	69240	40	0	0
T5	181840	30	0	0
T6	1336	0	0	0
T7	2129	0	0	0
T9	0	22	0	0
T10	0	24	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	12	0	0
T23	0	80	0	0
T29	0	40	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	64819905	0	0
T1	86670	86625	0	0
T2	188614	187448	0	0
T4	69240	3328	0	0
T5	181840	181586	0	0
T6	1336	1297	0	0
T7	2129	1932	0	0
T16	1128	1097	0	0
T17	1664	1598	0	0
T18	2364	2229	0	0
T19	33852	33783	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T4,T2,T23
1	0	Covered	T5,T1,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	67152137	90154	0	0
DstReqKnown_A	97171660	96179629	0	0
SrcAckBusyChk_A	67152137	17859	0	0
SrcBusyKnown_A	67152137	64819905	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	90154	0	0
T1	86670	157	0	0
T2	188614	1218	0	0
T3	0	160	0	0
T4	69240	329	0	0
T5	181840	258	0	0
T6	1336	0	0	0
T7	2129	0	0	0
T9	0	120	0	0
T10	0	208	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	58	0	0
T23	0	560	0	0
T29	0	145	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97171660	96179629	0	0
T1	90402	90388	0	0
T2	917715	915623	0	0
T4	20675	1667	0	0
T5	69948	69879	0	0
T6	2659	2625	0	0
T7	975	927	0	0
T16	2121	2107	0	0
T17	820	799	0	0
T18	1129	1115	0	0
T19	33141	33093	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	17859	0	0
T1	86670	32	0	0
T2	188614	151	0	0
T3	0	42	0	0
T4	69240	40	0	0
T5	181840	30	0	0
T6	1336	0	0	0
T7	2129	0	0	0
T9	0	22	0	0
T10	0	24	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	12	0	0
T23	0	80	0	0
T29	0	40	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	64819905	0	0
T1	86670	86625	0	0
T2	188614	187448	0	0
T4	69240	3328	0	0
T5	181840	181586	0	0
T6	1336	1297	0	0
T7	2129	1932	0	0
T16	1128	1097	0	0
T17	1664	1598	0	0
T18	2364	2229	0	0
T19	33852	33783	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T4,T2,T23
1	0	Covered	T5,T1,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	67152137	144269	0	0
DstReqKnown_A	48585436	48089527	0	0
SrcAckBusyChk_A	67152137	17855	0	0
SrcBusyKnown_A	67152137	64819905	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	144269	0	0
T1	86670	249	0	0
T2	188614	2134	0	0
T3	0	234	0	0
T4	69240	566	0	0
T5	181840	447	0	0
T6	1336	0	0	0
T7	2129	0	0	0
T9	0	190	0	0
T10	0	350	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	96	0	0
T23	0	966	0	0
T29	0	210	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48585436	48089527	0	0
T1	45201	45194	0	0
T2	458856	457810	0	0
T4	10338	834	0	0
T5	34974	34939	0	0
T6	1329	1312	0	0
T7	488	464	0	0
T16	1060	1053	0	0
T17	410	400	0	0
T18	564	557	0	0
T19	16570	16546	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	17855	0	0
T1	86670	32	0	0
T2	188614	151	0	0
T3	0	42	0	0
T4	69240	40	0	0
T5	181840	30	0	0
T6	1336	0	0	0
T7	2129	0	0	0
T9	0	22	0	0
T10	0	24	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	12	0	0
T23	0	80	0	0
T29	0	40	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	64819905	0	0
T1	86670	86625	0	0
T2	188614	187448	0	0
T4	69240	3328	0	0
T5	181840	181586	0	0
T6	1336	1297	0	0
T7	2129	1932	0	0
T16	1128	1097	0	0
T17	1664	1598	0	0
T18	2364	2229	0	0
T19	33852	33783	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T4,T2,T23
1	0	Covered	T5,T1,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	67152137	62630	0	0
DstReqKnown_A	209757057	205637955	0	0
SrcAckBusyChk_A	67152137	18001	0	0
SrcBusyKnown_A	67152137	64819905	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	62630	0	0
T1	86670	107	0	0
T2	188614	740	0	0
T3	0	114	0	0
T4	69240	188	0	0
T5	181840	184	0	0
T6	1336	0	0	0
T7	2129	0	0	0
T9	0	82	0	0
T10	0	119	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	41	0	0
T23	0	356	0	0
T29	0	102	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209757057	205637955	0	0
T1	188411	188314	0	0
T2	195535	194308	0	0
T4	72128	3459	0	0
T5	169840	169586	0	0
T6	5346	5191	0	0
T7	2129	1932	0	0
T16	4515	4389	0	0
T17	1734	1665	0	0
T18	2463	2322	0	0
T19	69085	68944	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	18001	0	0
T1	86670	32	0	0
T2	188614	151	0	0
T3	0	42	0	0
T4	69240	40	0	0
T5	181840	30	0	0
T6	1336	0	0	0
T7	2129	0	0	0
T9	0	22	0	0
T10	0	24	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	12	0	0
T23	0	80	0	0
T29	0	40	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	64819905	0	0
T1	86670	86625	0	0
T2	188614	187448	0	0
T4	69240	3328	0	0
T5	181840	181586	0	0
T6	1336	1297	0	0
T7	2129	1932	0	0
T16	1128	1097	0	0
T17	1664	1598	0	0
T18	2364	2229	0	0
T19	33852	33783	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T4,T2,T23
1	0	Covered	T5,T1,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T1,T4
1	1	Covered	T5,T1,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T1,T4
0	0	1	Covered	T5,T1,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	67152137	89998	0	0
DstReqKnown_A	100761961	98791180	0	0
SrcAckBusyChk_A	67152137	17723	0	0
SrcBusyKnown_A	67152137	64819905	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	89998	0	0
T1	86670	155	0	0
T2	188614	1209	0	0
T3	0	157	0	0
T4	69240	264	0	0
T5	181840	255	0	0
T6	1336	0	0	0
T7	2129	0	0	0
T9	0	142	0	0
T10	0	199	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	59	0	0
T23	0	554	0	0
T29	0	146	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100761961	98791180	0	0
T1	90439	90392	0	0
T2	944344	938454	0	0
T4	34622	1661	0	0
T5	75765	75643	0	0
T6	2566	2492	0	0
T7	1022	927	0	0
T16	2167	2107	0	0
T17	832	799	0	0
T18	1182	1115	0	0
T19	33161	33094	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	17723	0	0
T1	86670	32	0	0
T2	188614	151	0	0
T3	0	42	0	0
T4	69240	30	0	0
T5	181840	30	0	0
T6	1336	0	0	0
T7	2129	0	0	0
T9	0	22	0	0
T10	0	24	0	0
T16	1128	0	0	0
T17	1664	0	0	0
T18	2364	0	0	0
T19	33852	12	0	0
T23	0	71	0	0
T29	0	40	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67152137	64819905	0	0
T1	86670	86625	0	0
T2	188614	187448	0	0
T4	69240	3328	0	0
T5	181840	181586	0	0
T6	1336	1297	0	0
T7	2129	1932	0	0
T16	1128	1097	0	0
T17	1664	1598	0	0
T18	2364	2229	0	0
T19	33852	33783	0	0