Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	198898494	444	0	0
StatusRise_A	198898494	444	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198898494	444	0	0
T12	421737	0	0	0
T33	5907	0	0	0
T35	4011	4	0	0
T36	0	3	0	0
T37	0	3	0	0
T119	7536	0	0	0
T175	0	5	0	0
T176	0	2	0	0
T177	0	12	0	0
T178	0	9	0	0
T179	0	11	0	0
T180	0	4	0	0
T181	0	3	0	0
T182	0	2	0	0
T183	6444	0	0	0
T184	6723	0	0	0
T185	5829	0	0	0
T186	3609	0	0	0
T187	214869	0	0	0
T188	6603	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	198898494	444	0	0
T12	421737	0	0	0
T33	5907	0	0	0
T35	4011	4	0	0
T36	0	3	0	0
T37	0	3	0	0
T119	7536	0	0	0
T175	0	5	0	0
T176	0	2	0	0
T177	0	12	0	0
T178	0	9	0	0
T179	0	11	0	0
T180	0	4	0	0
T181	0	3	0	0
T182	0	2	0	0
T183	6444	0	0	0
T184	6723	0	0	0
T185	5829	0	0	0
T186	3609	0	0	0
T187	214869	0	0	0
T188	6603	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	66299498	146	0	0
StatusRise_A	66299498	146	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66299498	146	0	0
T12	140579	0	0	0
T33	1969	0	0	0
T35	1337	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T119	2512	0	0	0
T175	0	2	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	2	0	0
T183	2148	0	0	0
T184	2241	0	0	0
T185	1943	0	0	0
T186	1203	0	0	0
T187	71623	0	0	0
T188	2201	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66299498	146	0	0
T12	140579	0	0	0
T33	1969	0	0	0
T35	1337	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T119	2512	0	0	0
T175	0	2	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	2	0	0
T183	2148	0	0	0
T184	2241	0	0	0
T185	1943	0	0	0
T186	1203	0	0	0
T187	71623	0	0	0
T188	2201	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	66299498	150	0	0
StatusRise_A	66299498	150	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66299498	150	0	0
T12	140579	0	0	0
T33	1969	0	0	0
T35	1337	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T119	2512	0	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	3	0	0
T178	0	3	0	0
T179	0	3	0	0
T180	0	1	0	0
T181	0	1	0	0
T183	2148	0	0	0
T184	2241	0	0	0
T185	1943	0	0	0
T186	1203	0	0	0
T187	71623	0	0	0
T188	2201	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66299498	150	0	0
T12	140579	0	0	0
T33	1969	0	0	0
T35	1337	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T119	2512	0	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	3	0	0
T178	0	3	0	0
T179	0	3	0	0
T180	0	1	0	0
T181	0	1	0	0
T183	2148	0	0	0
T184	2241	0	0	0
T185	1943	0	0	0
T186	1203	0	0	0
T187	71623	0	0	0
T188	2201	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	66299498	148	0	0
StatusRise_A	66299498	148	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66299498	148	0	0
T12	140579	0	0	0
T33	1969	0	0	0
T35	1337	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T119	2512	0	0	0
T175	0	2	0	0
T176	0	1	0	0
T177	0	5	0	0
T178	0	4	0	0
T179	0	4	0	0
T180	0	2	0	0
T181	0	1	0	0
T183	2148	0	0	0
T184	2241	0	0	0
T185	1943	0	0	0
T186	1203	0	0	0
T187	71623	0	0	0
T188	2201	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	66299498	148	0	0
T12	140579	0	0	0
T33	1969	0	0	0
T35	1337	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T119	2512	0	0	0
T175	0	2	0	0
T176	0	1	0	0
T177	0	5	0	0
T178	0	4	0	0
T179	0	4	0	0
T180	0	2	0	0
T181	0	1	0	0
T183	2148	0	0	0
T184	2241	0	0	0
T185	1943	0	0	0
T186	1203	0	0	0
T187	71623	0	0	0
T188	2201	0	0	0