Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T29
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	29086	0	0
CgEnOn_A	2147483647	20653	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	29086	0	0
T1	693294	3	0	0
T2	4429678	243	0	0
T3	0	2	0	0
T4	244509	33	0	0
T5	244925	3	0	0
T6	9119	3	0	0
T7	7765	5	0	0
T16	16546	3	0	0
T17	6362	5	0	0
T18	14168	7	0	0
T19	403370	3	0	0
T20	6672	0	0	0
T21	8192	0	0	0
T22	3457	0	0	0
T23	204395	0	0	0
T27	49946	0	0	0
T28	5088	0	0	0
T29	527114	25	0	0
T33	2141	0	0	0
T35	1281	5	0	0
T36	0	5	0	0
T37	0	5	0	0
T175	0	5	0	0
T176	0	5	0	0
T177	0	15	0	0
T178	0	15	0	0
T179	0	15	0	0
T180	0	5	0	0
T183	2238	0	0	0
T184	2309	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	20653	0	0
T2	4050266	226	0	0
T3	0	73	0	0
T7	2129	2	0	0
T12	487970	0	0	0
T17	0	2	0	0
T18	9341	4	0	0
T19	267966	0	0	0
T20	6145	36	0	0
T21	7558	0	0	0
T22	4579	0	0	0
T23	253638	0	0	0
T27	67949	0	0	0
T28	7205	0	0	0
T29	703325	74	0	0
T33	2055	0	0	0
T35	1235	8	0	0
T36	0	5	0	0
T37	0	5	0	0
T87	0	4	0	0
T88	0	7	0	0
T119	2460	0	0	0
T175	0	5	0	0
T176	0	5	0	0
T177	0	15	0	0
T178	0	15	0	0
T179	0	15	0	0
T180	0	5	0	0
T181	0	1	0	0
T183	2148	0	0	0
T184	2218	0	0	0
T185	1963	0	0	0
T186	4621	35	0	0
T187	47840	0	0	0
T188	2177	0	0	0
T189	0	18	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T29
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	95984505	155	0	0
CgEnOn_A	95984505	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95984505	155	0	0
T2	917715	1	0	0
T18	1129	0	0	0
T19	33141	0	0	0
T20	737	0	0	0
T21	910	0	0	0
T22	748	0	0	0
T23	32829	0	0	0
T27	12003	0	0	0
T28	1411	0	0	0
T29	117475	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	3	0	0
T178	0	3	0	0
T179	0	3	0	0
T180	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95984505	155	0	0
T2	917715	1	0	0
T18	1129	0	0	0
T19	33141	0	0	0
T20	737	0	0	0
T21	910	0	0	0
T22	748	0	0	0
T23	32829	0	0	0
T27	12003	0	0	0
T28	1411	0	0	0
T29	117475	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	3	0	0
T178	0	3	0	0
T179	0	3	0	0
T180	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T29
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	47991829	155	0	0
CgEnOn_A	47991829	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47991829	155	0	0
T2	458856	1	0	0
T18	564	0	0	0
T19	16570	0	0	0
T20	368	0	0	0
T21	455	0	0	0
T22	374	0	0	0
T23	16414	0	0	0
T27	6000	0	0	0
T28	706	0	0	0
T29	58736	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	3	0	0
T178	0	3	0	0
T179	0	3	0	0
T180	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47991829	155	0	0
T2	458856	1	0	0
T18	564	0	0	0
T19	16570	0	0	0
T20	368	0	0	0
T21	455	0	0	0
T22	374	0	0	0
T23	16414	0	0	0
T27	6000	0	0	0
T28	706	0	0	0
T29	58736	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	3	0	0
T178	0	3	0	0
T179	0	3	0	0
T180	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T29
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	47991829	155	0	0
CgEnOn_A	47991829	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47991829	155	0	0
T2	458856	1	0	0
T18	564	0	0	0
T19	16570	0	0	0
T20	368	0	0	0
T21	455	0	0	0
T22	374	0	0	0
T23	16414	0	0	0
T27	6000	0	0	0
T28	706	0	0	0
T29	58736	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	3	0	0
T178	0	3	0	0
T179	0	3	0	0
T180	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47991829	155	0	0
T2	458856	1	0	0
T18	564	0	0	0
T19	16570	0	0	0
T20	368	0	0	0
T21	455	0	0	0
T22	374	0	0	0
T23	16414	0	0	0
T27	6000	0	0	0
T28	706	0	0	0
T29	58736	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	3	0	0
T178	0	3	0	0
T179	0	3	0	0
T180	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T29
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	47991829	155	0	0
CgEnOn_A	47991829	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47991829	155	0	0
T2	458856	1	0	0
T18	564	0	0	0
T19	16570	0	0	0
T20	368	0	0	0
T21	455	0	0	0
T22	374	0	0	0
T23	16414	0	0	0
T27	6000	0	0	0
T28	706	0	0	0
T29	58736	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	3	0	0
T178	0	3	0	0
T179	0	3	0	0
T180	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47991829	155	0	0
T2	458856	1	0	0
T18	564	0	0	0
T19	16570	0	0	0
T20	368	0	0	0
T21	455	0	0	0
T22	374	0	0	0
T23	16414	0	0	0
T27	6000	0	0	0
T28	706	0	0	0
T29	58736	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	3	0	0
T178	0	3	0	0
T179	0	3	0	0
T180	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T29
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	193519678	155	0	0
CgEnOn_A	193519678	150	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193519678	155	0	0
T2	183877	1	0	0
T18	2364	0	0	0
T19	66319	0	0	0
T20	1567	0	0	0
T21	1919	0	0	0
T22	1587	0	0	0
T23	122324	0	0	0
T27	19943	0	0	0
T28	1559	0	0	0
T29	233431	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	3	0	0
T178	0	3	0	0
T179	0	3	0	0
T180	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193519678	150	0	0
T12	487970	0	0	0
T33	2055	0	0	0
T35	1235	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T119	2460	0	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	3	0	0
T178	0	3	0	0
T179	0	3	0	0
T180	0	1	0	0
T181	0	1	0	0
T183	2148	0	0	0
T184	2218	0	0	0
T185	1963	0	0	0
T186	4621	0	0	0
T187	47840	0	0	0
T188	2177	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T29
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	207185345	146	0	0
CgEnOn_A	207185345	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207185345	146	0	0
T12	526319	0	0	0
T33	2141	0	0	0
T35	1281	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T119	2562	0	0	0
T175	0	2	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	2	0	0
T183	2238	0	0	0
T184	2309	0	0	0
T185	2044	0	0	0
T186	4814	0	0	0
T187	73836	0	0	0
T188	2268	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207185345	146	0	0
T12	526319	0	0	0
T33	2141	0	0	0
T35	1281	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T119	2562	0	0	0
T175	0	2	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	2	0	0
T183	2238	0	0	0
T184	2309	0	0	0
T185	2044	0	0	0
T186	4814	0	0	0
T187	73836	0	0	0
T188	2268	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T29
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	207185345	146	0	0
CgEnOn_A	207185345	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207185345	146	0	0
T12	526319	0	0	0
T33	2141	0	0	0
T35	1281	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T119	2562	0	0	0
T175	0	2	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	2	0	0
T183	2238	0	0	0
T184	2309	0	0	0
T185	2044	0	0	0
T186	4814	0	0	0
T187	73836	0	0	0
T188	2268	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207185345	146	0	0
T12	526319	0	0	0
T33	2141	0	0	0
T35	1281	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T119	2562	0	0	0
T175	0	2	0	0
T177	0	4	0	0
T178	0	2	0	0
T179	0	4	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	2	0	0
T183	2238	0	0	0
T184	2309	0	0	0
T185	2044	0	0	0
T186	4814	0	0	0
T187	73836	0	0	0
T188	2268	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T29
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99527570	150	0	0
CgEnOn_A	99527570	148	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99527570	150	0	0
T12	264157	0	0	0
T33	1027	0	0	0
T35	622	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T119	1230	0	0	0
T175	0	2	0	0
T176	0	1	0	0
T177	0	5	0	0
T178	0	4	0	0
T179	0	4	0	0
T180	0	2	0	0
T181	0	1	0	0
T183	1074	0	0	0
T184	1109	0	0	0
T185	981	0	0	0
T186	2311	0	0	0
T187	32561	0	0	0
T188	1089	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99527570	148	0	0
T12	264157	0	0	0
T33	1027	0	0	0
T35	622	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T119	1230	0	0	0
T175	0	2	0	0
T176	0	1	0	0
T177	0	5	0	0
T178	0	4	0	0
T179	0	4	0	0
T180	0	2	0	0
T181	0	1	0	0
T183	1074	0	0	0
T184	1109	0	0	0
T185	981	0	0	0
T186	2311	0	0	0
T187	32561	0	0	0
T188	1089	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	47991829	5010	0	0
CgEnOn_A	47991829	2906	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47991829	5010	0	0
T1	45201	1	0	0
T2	458856	74	0	0
T4	10338	11	0	0
T5	34974	1	0	0
T6	1329	1	0	0
T7	488	1	0	0
T16	1060	1	0	0
T17	410	1	0	0
T18	564	2	0	0
T19	16570	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47991829	2906	0	0
T2	458856	69	0	0
T3	0	23	0	0
T18	564	1	0	0
T19	16570	0	0	0
T20	368	12	0	0
T21	455	0	0	0
T22	374	0	0	0
T23	16414	0	0	0
T27	6000	0	0	0
T28	706	0	0	0
T29	58736	16	0	0
T35	0	1	0	0
T87	0	1	0	0
T88	0	2	0	0
T186	0	13	0	0
T189	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	95984505	5015	0	0
CgEnOn_A	95984505	2911	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95984505	5015	0	0
T1	90402	1	0	0
T2	917715	73	0	0
T4	20675	11	0	0
T5	69948	1	0	0
T6	2659	1	0	0
T7	975	1	0	0
T16	2121	1	0	0
T17	820	1	0	0
T18	1129	2	0	0
T19	33141	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95984505	2911	0	0
T2	917715	68	0	0
T3	0	25	0	0
T18	1129	1	0	0
T19	33141	0	0	0
T20	737	13	0	0
T21	910	0	0	0
T22	748	0	0	0
T23	32829	0	0	0
T27	12003	0	0	0
T28	1411	0	0	0
T29	117475	16	0	0
T35	0	1	0	0
T87	0	1	0	0
T88	0	3	0	0
T186	0	11	0	0
T189	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	193519678	5038	0	0
CgEnOn_A	193519678	2929	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193519678	5038	0	0
T1	180869	1	0	0
T2	183877	74	0	0
T4	69240	11	0	0
T5	140003	1	0	0
T6	5131	1	0	0
T7	2044	1	0	0
T16	4335	1	0	0
T17	1664	1	0	0
T18	2364	2	0	0
T19	66319	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193519678	2929	0	0
T2	183877	68	0	0
T3	0	23	0	0
T18	2364	1	0	0
T19	66319	0	0	0
T20	1567	11	0	0
T21	1919	0	0	0
T22	1587	0	0	0
T23	122324	0	0	0
T27	19943	0	0	0
T28	1559	0	0	0
T29	233431	17	0	0
T35	0	1	0	0
T87	0	1	0	0
T88	0	2	0	0
T186	0	11	0	0
T189	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	99527570	5029	0	0
CgEnOn_A	99527570	2920	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99527570	5029	0	0
T1	90439	1	0	0
T2	944344	71	0	0
T4	34622	11	0	0
T5	75765	1	0	0
T6	2566	1	0	0
T7	1022	1	0	0
T16	2167	1	0	0
T17	832	1	0	0
T18	1182	2	0	0
T19	33161	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	99527570	2920	0	0
T2	944344	65	0	0
T3	0	21	0	0
T18	1182	1	0	0
T19	33161	0	0	0
T20	783	11	0	0
T21	960	0	0	0
T22	793	0	0	0
T23	61165	0	0	0
T27	9972	0	0	0
T28	780	0	0	0
T29	128241	19	0	0
T35	0	2	0	0
T87	0	1	0	0
T88	0	2	0	0
T186	0	12	0	0
T189	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T29
1	0	Covered	T7,T17,T2
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	207185345	1943	0	0
CgEnOn_A	207185345	1943	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207185345	1943	0	0
T1	188411	0	0	0
T2	195535	17	0	0
T3	0	2	0	0
T4	72128	0	0	0
T7	2129	2	0	0
T16	4515	0	0	0
T17	1734	2	0	0
T18	2463	1	0	0
T19	69085	0	0	0
T20	1632	0	0	0
T21	1999	0	0	0
T29	0	25	0	0
T85	0	10	0	0
T87	0	1	0	0
T116	0	8	0	0
T117	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207185345	1943	0	0
T1	188411	0	0	0
T2	195535	17	0	0
T3	0	2	0	0
T4	72128	0	0	0
T7	2129	2	0	0
T16	4515	0	0	0
T17	1734	2	0	0
T18	2463	1	0	0
T19	69085	0	0	0
T20	1632	0	0	0
T21	1999	0	0	0
T29	0	25	0	0
T85	0	10	0	0
T87	0	1	0	0
T116	0	8	0	0
T117	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T29
1	0	Covered	T7,T17,T2
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	207185345	1946	0	0
CgEnOn_A	207185345	1946	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207185345	1946	0	0
T1	188411	0	0	0
T2	195535	20	0	0
T3	0	2	0	0
T4	72128	0	0	0
T7	2129	4	0	0
T16	4515	0	0	0
T17	1734	3	0	0
T18	2463	1	0	0
T19	69085	0	0	0
T20	1632	0	0	0
T21	1999	0	0	0
T29	0	26	0	0
T85	0	10	0	0
T87	0	1	0	0
T116	0	11	0	0
T117	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207185345	1946	0	0
T1	188411	0	0	0
T2	195535	20	0	0
T3	0	2	0	0
T4	72128	0	0	0
T7	2129	4	0	0
T16	4515	0	0	0
T17	1734	3	0	0
T18	2463	1	0	0
T19	69085	0	0	0
T20	1632	0	0	0
T21	1999	0	0	0
T29	0	26	0	0
T85	0	10	0	0
T87	0	1	0	0
T116	0	11	0	0
T117	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T29
1	0	Covered	T7,T17,T2
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	207185345	1940	0	0
CgEnOn_A	207185345	1940	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207185345	1940	0	0
T1	188411	0	0	0
T2	195535	26	0	0
T3	0	2	0	0
T4	72128	0	0	0
T7	2129	2	0	0
T16	4515	0	0	0
T17	1734	2	0	0
T18	2463	1	0	0
T19	69085	0	0	0
T20	1632	0	0	0
T21	1999	0	0	0
T29	0	21	0	0
T85	0	8	0	0
T87	0	1	0	0
T116	0	7	0	0
T117	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207185345	1940	0	0
T1	188411	0	0	0
T2	195535	26	0	0
T3	0	2	0	0
T4	72128	0	0	0
T7	2129	2	0	0
T16	4515	0	0	0
T17	1734	2	0	0
T18	2463	1	0	0
T19	69085	0	0	0
T20	1632	0	0	0
T21	1999	0	0	0
T29	0	21	0	0
T85	0	8	0	0
T87	0	1	0	0
T116	0	7	0	0
T117	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T29
1	0	Covered	T7,T2,T18
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	207185345	1948	0	0
CgEnOn_A	207185345	1948	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207185345	1948	0	0
T1	188411	0	0	0
T2	195535	25	0	0
T3	0	2	0	0
T4	72128	0	0	0
T7	2129	3	0	0
T16	4515	0	0	0
T17	1734	0	0	0
T18	2463	1	0	0
T19	69085	0	0	0
T20	1632	0	0	0
T21	1999	0	0	0
T29	0	29	0	0
T85	0	10	0	0
T87	0	1	0	0
T116	0	5	0	0
T117	0	4	0	0
T118	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207185345	1948	0	0
T1	188411	0	0	0
T2	195535	25	0	0
T3	0	2	0	0
T4	72128	0	0	0
T7	2129	3	0	0
T16	4515	0	0	0
T17	1734	0	0	0
T18	2463	1	0	0
T19	69085	0	0	0
T20	1632	0	0	0
T21	1999	0	0	0
T29	0	29	0	0
T85	0	10	0	0
T87	0	1	0	0
T116	0	5	0	0
T117	0	4	0	0
T118	0	4	0	0