Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	964019	0	0
SrcPulseCheck_M	2147483647	961178	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	964019
T1	0	494
T2	0	13047
T3	0	1832
T4	0	22
T5	0	120
T6	389357	532
T12	0	192
T24	0	808
T25	0	1142
T26	11136	0
T27	18178	0
T28	5738	0
T29	35417	0
T30	59999	0
T31	9911	0
T32	35596	0
T34	16538	0
T35	0	191
T36	0	968
T38	7419	0
T68	23512	3
T70	27444	1
T72	21752	2
T73	11240	2
T74	21934	1
T75	6505	2
T76	11130	1
T87	0	2004
T130	14704	1
T131	12804	2
T132	4968	0
T133	10802	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	961178
T1	0	494
T2	0	13047
T3	0	1832
T4	0	22
T5	0	120
T6	74966	532
T12	0	192
T24	0	808
T25	0	1142
T26	4628	0
T27	10531	0
T28	3431	0
T29	9764	0
T30	15674	0
T31	5963	0
T32	11455	0
T34	6927	0
T35	0	191
T36	0	968
T38	4533	0
T68	9160	3
T70	12232	1
T72	8560	2
T73	52272	2
T74	42496	1
T75	11646	2
T76	9912	1
T87	0	2004
T130	10536	1
T131	59942	2
T132	9383	0
T133	20006	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	434323933	25662	0	0
SrcPulseCheck_M	170052143	25662	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	434323933	25662
T1	0	36
T2	0	624
T3	0	100
T4	0	4
T5	0	24
T6	97796	20
T24	0	32
T25	0	46
T26	2564	0
T27	3849	0
T28	1214	0
T29	8428	0
T30	15408	0
T31	2099	0
T32	8316	0
T34	3777	0
T35	0	8
T36	0	36
T38	1577	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	170052143	25662
T1	0	36
T2	0	624
T3	0	100
T4	0	4
T5	0	24
T6	12586	20
T24	0	32
T25	0	46
T26	1282	0
T27	3770	0
T28	1253	0
T29	1228	0
T30	1766	0
T31	2186	0
T32	2165	0
T34	1928	0
T35	0	8
T36	0	36
T38	1667	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	434323933	31634	0	0
SrcPulseCheck_M	170052143	31655	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	434323933	31634
T1	0	36
T2	0	635
T3	0	100
T4	0	8
T5	0	48
T6	97796	20
T24	0	32
T25	0	46
T26	2564	0
T27	3849	0
T28	1214	0
T29	8428	0
T30	15408	0
T31	2099	0
T32	8316	0
T34	3777	0
T35	0	8
T36	0	36
T38	1577	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	170052143	31655
T1	0	36
T2	0	635
T3	0	100
T4	0	8
T5	0	48
T6	12586	20
T24	0	32
T25	0	46
T26	1282	0
T27	3770	0
T28	1253	0
T29	1228	0
T30	1766	0
T31	2186	0
T32	2165	0
T34	1928	0
T35	0	8
T36	0	36
T38	1667	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	170052143	31622	0	0
SrcPulseCheck_M	434323933	31639	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	170052143	31622
T1	0	36
T2	0	635
T3	0	100
T4	0	8
T5	0	48
T6	12586	20
T24	0	32
T25	0	46
T26	1282	0
T27	3770	0
T28	1253	0
T29	1228	0
T30	1766	0
T31	2186	0
T32	2165	0
T34	1928	0
T35	0	8
T36	0	36
T38	1667	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	434323933	31639
T1	0	36
T2	0	635
T3	0	100
T4	0	8
T5	0	48
T6	97796	20
T24	0	32
T25	0	46
T26	2564	0
T27	3849	0
T28	1214	0
T29	8428	0
T30	15408	0
T31	2099	0
T32	8316	0
T34	3777	0
T35	0	8
T36	0	36
T38	1577	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	216315355	25662	0	0
SrcPulseCheck_M	170052143	25662	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	216315355	25662
T1	0	36
T2	0	624
T3	0	100
T4	0	4
T5	0	24
T6	48886	20
T24	0	32
T25	0	46
T26	1320	0
T27	1871	0
T28	573	0
T29	4852	0
T30	7650	0
T31	983	0
T32	4701	0
T34	1971	0
T35	0	8
T36	0	36
T38	735	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	170052143	25662
T1	0	36
T2	0	624
T3	0	100
T4	0	4
T5	0	24
T6	12586	20
T24	0	32
T25	0	46
T26	1282	0
T27	3770	0
T28	1253	0
T29	1228	0
T30	1766	0
T31	2186	0
T32	2165	0
T34	1928	0
T35	0	8
T36	0	36
T38	1667	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	216315355	31444	0	0
SrcPulseCheck_M	170052143	31474	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	216315355	31444
T1	0	36
T2	0	635
T3	0	100
T4	0	8
T5	0	48
T6	48886	20
T24	0	32
T25	0	46
T26	1320	0
T27	1871	0
T28	573	0
T29	4852	0
T30	7650	0
T31	983	0
T32	4701	0
T34	1971	0
T35	0	8
T36	0	36
T38	735	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	170052143	31474
T1	0	36
T2	0	635
T3	0	100
T4	0	8
T5	0	48
T6	12586	20
T24	0	32
T25	0	46
T26	1282	0
T27	3770	0
T28	1253	0
T29	1228	0
T30	1766	0
T31	2186	0
T32	2165	0
T34	1928	0
T35	0	8
T36	0	36
T38	1667	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	170052143	31438	0	0
SrcPulseCheck_M	216315355	31447	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	170052143	31438
T1	0	36
T2	0	635
T3	0	100
T4	0	8
T5	0	48
T6	12586	20
T24	0	32
T25	0	46
T26	1282	0
T27	3770	0
T28	1253	0
T29	1228	0
T30	1766	0
T31	2186	0
T32	2165	0
T34	1928	0
T35	0	8
T36	0	36
T38	1667	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	216315355	31447
T1	0	36
T2	0	635
T3	0	100
T4	0	8
T5	0	48
T6	48886	20
T24	0	32
T25	0	46
T26	1320	0
T27	1871	0
T28	573	0
T29	4852	0
T30	7650	0
T31	983	0
T32	4701	0
T34	1971	0
T35	0	8
T36	0	36
T38	735	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	108157037	25662	0	0
SrcPulseCheck_M	170052143	25662	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	108157037	25662
T1	0	36
T2	0	624
T3	0	100
T4	0	4
T5	0	24
T6	24443	20
T24	0	32
T25	0	46
T26	659	0
T27	936	0
T28	287	0
T29	2425	0
T30	3825	0
T31	491	0
T32	2350	0
T34	985	0
T35	0	8
T36	0	36
T38	368	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	170052143	25662
T1	0	36
T2	0	624
T3	0	100
T4	0	4
T5	0	24
T6	12586	20
T24	0	32
T25	0	46
T26	1282	0
T27	3770	0
T28	1253	0
T29	1228	0
T30	1766	0
T31	2186	0
T32	2165	0
T34	1928	0
T35	0	8
T36	0	36
T38	1667	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	108157037	31465	0	0
SrcPulseCheck_M	170052143	31502	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	108157037	31465
T1	0	36
T2	0	635
T3	0	100
T4	0	8
T5	0	48
T6	24443	20
T24	0	32
T25	0	46
T26	659	0
T27	936	0
T28	287	0
T29	2425	0
T30	3825	0
T31	491	0
T32	2350	0
T34	985	0
T35	0	8
T36	0	36
T38	368	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	170052143	31502
T1	0	36
T2	0	635
T3	0	100
T4	0	8
T5	0	48
T6	12586	20
T24	0	32
T25	0	46
T26	1282	0
T27	3770	0
T28	1253	0
T29	1228	0
T30	1766	0
T31	2186	0
T32	2165	0
T34	1928	0
T35	0	8
T36	0	36
T38	1667	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	170052143	31457	0	0
SrcPulseCheck_M	108157037	31468	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	170052143	31457
T1	0	36
T2	0	635
T3	0	100
T4	0	8
T5	0	48
T6	12586	20
T24	0	32
T25	0	46
T26	1282	0
T27	3770	0
T28	1253	0
T29	1228	0
T30	1766	0
T31	2186	0
T32	2165	0
T34	1928	0
T35	0	8
T36	0	36
T38	1667	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	108157037	31468
T1	0	36
T2	0	635
T3	0	100
T4	0	8
T5	0	48
T6	24443	20
T24	0	32
T25	0	46
T26	659	0
T27	936	0
T28	287	0
T29	2425	0
T30	3825	0
T31	491	0
T32	2350	0
T34	985	0
T35	0	8
T36	0	36
T38	368	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	463772319	25662	0	0
SrcPulseCheck_M	170052143	25662	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	463772319	25662
T1	0	36
T2	0	624
T3	0	100
T4	0	4
T5	0	24
T6	107874	20
T24	0	32
T25	0	46
T26	2671	0
T27	4010	0
T28	1265	0
T29	8780	0
T30	16050	0
T31	2186	0
T32	8662	0
T34	3935	0
T35	0	8
T36	0	36
T38	1602	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	170052143	25662
T1	0	36
T2	0	624
T3	0	100
T4	0	4
T5	0	24
T6	12586	20
T24	0	32
T25	0	46
T26	1282	0
T27	3770	0
T28	1253	0
T29	1228	0
T30	1766	0
T31	2186	0
T32	2165	0
T34	1928	0
T35	0	8
T36	0	36
T38	1667	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	463772319	31501	0	0
SrcPulseCheck_M	170052143	31520	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	463772319	31501
T1	0	36
T2	0	635
T3	0	100
T4	0	8
T5	0	48
T6	107874	20
T24	0	32
T25	0	46
T26	2671	0
T27	4010	0
T28	1265	0
T29	8780	0
T30	16050	0
T31	2186	0
T32	8662	0
T34	3935	0
T35	0	8
T36	0	36
T38	1602	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	170052143	31520
T1	0	36
T2	0	635
T3	0	100
T4	0	8
T5	0	48
T6	12586	20
T24	0	32
T25	0	46
T26	1282	0
T27	3770	0
T28	1253	0
T29	1228	0
T30	1766	0
T31	2186	0
T32	2165	0
T34	1928	0
T35	0	8
T36	0	36
T38	1667	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	170052143	31489	0	0
SrcPulseCheck_M	463772319	31505	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	170052143	31489
T1	0	36
T2	0	635
T3	0	100
T4	0	8
T5	0	48
T6	12586	20
T24	0	32
T25	0	46
T26	1282	0
T27	3770	0
T28	1253	0
T29	1228	0
T30	1766	0
T31	2186	0
T32	2165	0
T34	1928	0
T35	0	8
T36	0	36
T38	1667	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	463772319	31505
T1	0	36
T2	0	635
T3	0	100
T4	0	8
T5	0	48
T6	107874	20
T24	0	32
T25	0	46
T26	2671	0
T27	4010	0
T28	1265	0
T29	8780	0
T30	16050	0
T31	2186	0
T32	8662	0
T34	3935	0
T35	0	8
T36	0	36
T38	1602	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	222787306	25176	0	0
SrcPulseCheck_M	170052143	25662	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	222787306	25176
T1	0	36
T2	0	624
T3	0	100
T4	0	3
T5	0	14
T6	54661	20
T24	0	32
T25	0	46
T26	1282	0
T27	1925	0
T28	607	0
T29	4214	0
T30	7704	0
T31	1049	0
T32	4158	0
T34	1888	0
T35	0	8
T36	0	36
T38	778	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	170052143	25662
T1	0	36
T2	0	624
T3	0	100
T4	0	4
T5	0	24
T6	12586	20
T24	0	32
T25	0	46
T26	1282	0
T27	3770	0
T28	1253	0
T29	1228	0
T30	1766	0
T31	2186	0
T32	2165	0
T34	1928	0
T35	0	8
T36	0	36
T38	1667	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	222787306	31366	0	0
SrcPulseCheck_M	170052143	31586	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	222787306	31366
T1	0	36
T2	0	635
T3	0	100
T4	0	8
T5	0	48
T6	54661	20
T24	0	32
T25	0	46
T26	1282	0
T27	1925	0
T28	607	0
T29	4214	0
T30	7704	0
T31	1049	0
T32	4158	0
T34	1888	0
T35	0	8
T36	0	36
T38	778	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	170052143	31586
T1	0	36
T2	0	635
T3	0	100
T4	0	8
T5	0	48
T6	12586	20
T24	0	32
T25	0	46
T26	1282	0
T27	3770	0
T28	1253	0
T29	1228	0
T30	1766	0
T31	2186	0
T32	2165	0
T34	1928	0
T35	0	8
T36	0	36
T38	1667	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T5
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	170052143	31253	0	0
SrcPulseCheck_M	222787306	31418	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	170052143	31253
T1	0	36
T2	0	635
T3	0	100
T4	0	8
T5	0	47
T6	12586	20
T24	0	32
T25	0	46
T26	1282	0
T27	3770	0
T28	1253	0
T29	1228	0
T30	1766	0
T31	2186	0
T32	2165	0
T34	1928	0
T35	0	8
T36	0	36
T38	1667	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	222787306	31418
T1	0	36
T2	0	635
T3	0	100
T4	0	8
T5	0	48
T6	54661	20
T24	0	32
T25	0	46
T26	1282	0
T27	1925	0
T28	607	0
T29	4214	0
T30	7704	0
T31	1049	0
T32	4158	0
T34	1888	0
T35	0	8
T36	0	36
T38	778	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T69,T70,T71
1	0	Covered	T69,T70,T71
1	1	Covered	T75,T134,T131

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T69,T70,T71
1	0	Covered	T75,T134,T131
1	1	Covered	T69,T70,T71

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	170052143	33	0	0
SrcPulseCheck_M	434323933	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	170052143	33
T69	6953	1
T70	13722	1
T71	10459	1
T72	10876	1
T74	10967	1
T75	6505	3
T131	6402	5
T134	5854	2
T135	6108	1
T136	12021	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	434323933	33
T69	6674	1
T70	13441	1
T71	20079	1
T72	10440	1
T74	43867	1
T75	24979	3
T131	61467	5
T134	11708	2
T135	6108	1
T136	11539	1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T71,T74,T75
1	0	Covered	T71,T74,T75
1	1	Covered	T134,T131,T137

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T71,T74,T75
1	0	Covered	T134,T131,T137
1	1	Covered	T71,T74,T75

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	170052143	30	0	0
SrcPulseCheck_M	434323933	30	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	170052143	30
T71	10459	1
T74	10967	1
T75	6505	1
T130	7352	1
T131	6402	5
T134	5854	2
T135	6108	1
T138	9267	1
T139	8014	1
T140	5694	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	434323933	30
T71	20079	1
T74	43867	1
T75	24979	1
T130	11569	1
T131	61467	5
T134	11708	2
T135	6108	1
T138	18155	1
T139	7692	1
T140	5753	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T68,T70,T73
1	0	Covered	T68,T70,T73
1	1	Covered	T68,T141

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T68,T70,T73
1	0	Covered	T68,T141
1	1	Covered	T68,T70,T73

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	170052143	36	0	0
SrcPulseCheck_M	216315355	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	170052143	36
T68	11756	3
T70	13722	1
T72	10876	2
T73	5620	2
T74	10967	1
T75	6505	2
T76	5565	1
T130	7352	1
T131	6402	2
T133	5401	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	216315355	36
T68	4580	3
T70	6116	1
T72	4280	2
T73	26136	2
T74	21248	1
T75	11646	2
T76	4956	1
T130	5268	1
T131	29971	2
T133	10003	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T68,T70,T73
1	0	Covered	T68,T70,T73
1	1	Covered	T68,T132,T139

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T68,T70,T73
1	0	Covered	T68,T132,T139
1	1	Covered	T68,T70,T73

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	170052143	43	0	0
SrcPulseCheck_M	216315355	43	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	170052143	43
T68	11756	4
T70	13722	1
T72	10876	2
T73	5620	1
T74	10967	2
T76	5565	1
T130	7352	1
T131	6402	1
T132	4968	2
T133	5401	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	216315355	43
T68	4580	4
T70	6116	1
T72	4280	2
T73	26136	1
T74	21248	2
T76	4956	1
T130	5268	1
T131	29971	1
T132	9383	2
T133	10003	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T68,T69,T73
1	0	Covered	T68,T69,T73
1	1	Covered	T73,T131,T136

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T68,T69,T73
1	0	Covered	T73,T131,T136
1	1	Covered	T68,T69,T73

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	170052143	34	0	0
SrcPulseCheck_M	108157037	34	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	170052143	34
T68	11756	2
T69	6953	1
T72	10876	1
T73	5620	2
T74	10967	1
T75	6505	2
T131	6402	4
T133	5401	1
T134	5854	1
T136	12021	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	108157037	34
T68	2289	2
T69	1371	1
T72	2140	1
T73	13069	2
T74	10622	1
T75	5822	2
T131	14985	4
T133	5002	1
T134	2712	1
T136	2402	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T68,T73,T72
1	0	Covered	T68,T73,T72
1	1	Covered	T73,T131,T140

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T68,T73,T72
1	0	Covered	T73,T131,T140
1	1	Covered	T68,T73,T72

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	170052143	28	0	0
SrcPulseCheck_M	108157037	28	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	170052143	28
T68	11756	3
T72	10876	1
T73	5620	2
T75	6505	2
T131	6402	3
T136	12021	1
T140	5694	2
T142	5365	1
T143	4707	1
T144	3954	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	108157037	28
T68	2289	3
T72	2140	1
T73	13069	2
T75	5822	2
T131	14985	3
T136	2402	1
T140	1205	2
T142	2809	1
T143	8956	1
T144	3905	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T68,T69,T70
1	0	Covered	T68,T69,T70
1	1	Covered	T73,T131,T145

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T68,T69,T70
1	0	Covered	T73,T131,T145
1	1	Covered	T68,T69,T70

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	170052143	33	0	0
SrcPulseCheck_M	463772319	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	170052143	33
T68	11756	1
T69	6953	1
T70	13722	1
T73	5620	3
T130	7352	2
T131	6402	3
T132	4968	1
T135	6108	2
T136	12021	2
T146	7510	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	463772319	33
T68	11756	1
T69	6953	1
T70	14003	1
T73	56213	3
T130	12052	2
T131	64031	3
T132	20701	1
T135	6363	2
T136	12021	2
T146	15328	2

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T68,T69,T70
1	0	Covered	T68,T69,T70
1	1	Covered	T135,T145,T147

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T68,T69,T70
1	0	Covered	T135,T145,T147
1	1	Covered	T68,T69,T70

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	170052143	29	0	0
SrcPulseCheck_M	463772319	29	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	170052143	29
T68	11756	1
T69	6953	1
T70	13722	1
T73	5620	2
T76	5565	1
T130	7352	1
T131	6402	1
T132	4968	1
T134	5854	1
T135	6108	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	463772319	29
T68	11756	1
T69	6953	1
T70	14003	1
T73	56213	2
T76	11132	1
T130	12052	1
T131	64031	1
T132	20701	1
T134	12197	1
T135	6363	3

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T69,T70,T73
1	0	Covered	T69,T70,T73
1	1	Covered	T133,T135,T136

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T69,T70,T73
1	0	Covered	T133,T135,T136
1	1	Covered	T69,T70,T73

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	170052143	33	0	0
SrcPulseCheck_M	222787306	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	170052143	33
T69	6953	1
T70	13722	1
T71	10459	1
T72	10876	1
T73	5620	2
T76	5565	1
T130	7352	1
T132	4968	1
T133	5401	3
T135	6108	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	222787306	33
T69	3338	1
T70	6721	1
T71	10040	1
T72	5220	1
T73	26983	2
T76	5343	1
T130	5785	1
T132	9937	1
T133	10371	3
T135	3055	2

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T69,T73,T71
1	0	Covered	T69,T73,T71
1	1	Covered	T69,T72,T135

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T69,T73,T71
1	0	Covered	T69,T72,T135
1	1	Covered	T69,T73,T71

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	170052143	32	0	0
SrcPulseCheck_M	222787306	32	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	170052143	32
T69	6953	2
T71	10459	1
T72	10876	2
T73	5620	1
T76	5565	1
T130	7352	1
T132	4968	1
T133	5401	1
T134	5854	1
T135	6108	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	222787306	32
T69	3338	2
T71	10040	1
T72	5220	2
T73	26983	1
T76	5343	1
T130	5785	1
T132	9937	1
T133	10371	1
T134	5854	1
T135	3055	2

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T35
1	0	Covered	T6,T35,T1
1	1	Covered	T6,T35,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T35
1	0	Covered	T6,T35,T1
1	1	Covered	T6,T4,T35

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	431855825	97035	0	0
SrcPulseCheck_M	16473151	96513	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	431855825	97035
T1	0	96
T2	0	2612
T3	0	390
T4	0	1
T6	97796	115
T24	0	152
T25	0	224
T26	2564	0
T27	3849	0
T28	1214	0
T29	8428	0
T30	15408	0
T31	2099	0
T32	8316	0
T34	3777	0
T35	0	33
T36	0	206
T38	1577	0
T87	0	462

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	16473151	96513
T1	0	96
T2	0	2612
T3	0	390
T4	0	1
T6	224	115
T24	0	152
T25	0	224
T26	186	0
T27	280	0
T28	88	0
T29	614	0
T30	1123	0
T31	152	0
T32	606	0
T34	275	0
T35	0	33
T36	0	206
T38	116	0
T87	0	462

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T35
1	0	Covered	T6,T35,T1
1	1	Covered	T6,T35,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T4,T35
1	0	Covered	T6,T35,T1
1	1	Covered	T6,T4,T35

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	215126538	96277	0	0
SrcPulseCheck_M	16473151	95756	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	215126538	96277
T1	0	96
T2	0	2589
T3	0	384
T4	0	1
T6	48886	115
T24	0	152
T25	0	224
T26	1320	0
T27	1871	0
T28	573	0
T29	4852	0
T30	7650	0
T31	983	0
T32	4701	0
T34	1971	0
T35	0	33
T36	0	206
T38	735	0
T87	0	462

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	16473151	95756
T1	0	96
T2	0	2589
T3	0	384
T4	0	1
T6	224	115
T24	0	152
T25	0	224
T26	186	0
T27	280	0
T28	88	0
T29	614	0
T30	1123	0
T31	152	0
T32	606	0
T34	275	0
T35	0	33
T36	0	206
T38	116	0
T87	0	462

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T35,T1
1	0	Covered	T6,T35,T1
1	1	Covered	T6,T35,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T35,T1
1	0	Covered	T6,T35,T1
1	1	Covered	T6,T35,T1

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	107562629	95193	0	0
SrcPulseCheck_M	16473151	94676	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	107562629	95193
T1	0	98
T2	0	2545
T3	0	348
T6	24443	115
T12	0	96
T24	0	152
T25	0	224
T26	659	0
T27	936	0
T28	287	0
T29	2425	0
T30	3825	0
T31	491	0
T32	2350	0
T34	985	0
T35	0	33
T36	0	206
T38	368	0
T87	0	462

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	16473151	94676
T1	0	98
T2	0	2545
T3	0	348
T6	224	115
T12	0	96
T24	0	152
T25	0	224
T26	186	0
T27	280	0
T28	88	0
T29	614	0
T30	1123	0
T31	152	0
T32	606	0
T34	275	0
T35	0	33
T36	0	206
T38	116	0
T87	0	462

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T35,T1
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T35,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T35,T1
1	0	Covered	T6,T35,T1
1	1	Covered	T6,T35,T1

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	461201266	116616	0	0
SrcPulseCheck_M	16658008	115789	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	461201266	116616
T1	0	96
T2	0	3407
T3	0	410
T6	107874	127
T12	0	96
T24	0	256
T25	0	332
T26	2671	0
T27	4010	0
T28	1265	0
T29	8780	0
T30	16050	0
T31	2186	0
T32	8662	0
T34	3935	0
T35	0	68
T36	0	242
T38	1602	0
T87	0	618

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	16658008	115789
T1	0	96
T2	0	3407
T3	0	410
T6	236	127
T12	0	96
T24	0	256
T25	0	332
T26	186	0
T27	280	0
T28	88	0
T29	614	0
T30	1123	0
T31	152	0
T32	606	0
T34	275	0
T35	0	68
T36	0	242
T38	116	0
T87	0	618

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T35,T1
1	0	Covered	T6,T35,T1
1	1	Covered	T6,T35,T1

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T6,T35,T1
1	0	Covered	T6,T35,T1
1	1	Covered	T6,T35,T1

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T6
0	Covered	T7,T8,T6

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	221553224	116074	0	0
SrcPulseCheck_M	16533201	114589	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	221553224	116074
T1	0	86
T2	0	3430
T3	0	431
T6	54661	139
T12	0	96
T24	0	220
T25	0	296
T26	1282	0
T27	1925	0
T28	607	0
T29	4214	0
T30	7704	0
T31	1049	0
T32	4158	0
T34	1888	0
T35	0	65
T36	0	266
T38	778	0
T87	0	591

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	16533201	114589
T1	0	86
T2	0	3430
T3	0	431
T6	248	139
T12	0	96
T24	0	220
T25	0	296
T26	186	0
T27	280	0
T28	88	0
T29	614	0
T30	1123	0
T31	152	0
T32	606	0
T34	275	0
T35	0	65
T36	0	266
T38	116	0
T87	0	591

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb