Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T4,T5,T2
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1700521430	1489872	0	0
DstReqKnown_A	2147483647	2147483647	0	0
SrcAckBusyChk_A	1700521430	285082	0	0
SrcBusyKnown_A	1700521430	1670467460	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700521430	1489872	0	0
T1	0	1240	0	0
T2	0	21550	0	0
T3	0	2962	0	0
T4	0	182	0	0
T5	0	2563	0	0
T6	125860	544	0	0
T24	0	820	0	0
T25	0	1624	0	0
T26	12820	0	0	0
T27	37700	0	0	0
T28	12530	0	0	0
T29	12280	0	0	0
T30	17660	0	0	0
T31	21860	0	0	0
T32	21650	0	0	0
T34	19280	0	0	0
T35	0	297	0	0
T36	0	2964	0	0
T38	16670	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T6	667320	666560	0	0
T7	12936	12420	0	0
T8	37378	36334	0	0
T26	16992	16264	0	0
T27	25182	24456	0	0
T28	7892	6806	0	0
T29	57398	56200	0	0
T30	101274	99826	0	0
T31	13616	12478	0	0
T32	56374	55178	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700521430	285082	0	0
T1	0	360	0	0
T2	0	6295	0	0
T3	0	1000	0	0
T4	0	59	0	0
T5	0	349	0	0
T6	125860	200	0	0
T24	0	320	0	0
T25	0	460	0	0
T26	12820	0	0	0
T27	37700	0	0	0
T28	12530	0	0	0
T29	12280	0	0	0
T30	17660	0	0	0
T31	21860	0	0	0
T32	21650	0	0	0
T34	19280	0	0	0
T35	0	80	0	0
T36	0	360	0	0
T38	16670	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700521430	1670467460	0	0
T6	125860	125740	0	0
T7	20220	19260	0	0
T8	10960	10590	0	0
T26	12820	12150	0	0
T27	37700	36380	0	0
T28	12530	10570	0	0
T29	12280	11990	0	0
T30	17660	17380	0	0
T31	21860	19740	0	0
T32	21650	21120	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Unreachable
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	170052143	92913	0	0
DstReqKnown_A	434323933	429743268	0	0
SrcAckBusyChk_A	170052143	25662	0	0
SrcBusyKnown_A	170052143	167046746	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	92913	0	0
T1	0	93	0	0
T2	0	1569	0	0
T3	0	251	0	0
T4	0	8	0	0
T5	0	115	0	0
T6	12586	51	0	0
T24	0	82	0	0
T25	0	120	0	0
T26	1282	0	0	0
T27	3770	0	0	0
T28	1253	0	0	0
T29	1228	0	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	0	0	0
T34	1928	0	0	0
T35	0	22	0	0
T36	0	180	0	0
T38	1667	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434323933	429743268	0	0
T6	97796	97675	0	0
T7	1980	1887	0	0
T8	5544	5355	0	0
T26	2564	2429	0	0
T27	3849	3714	0	0
T28	1214	1025	0	0
T29	8428	8225	0	0
T30	15408	15163	0	0
T31	2099	1896	0	0
T32	8316	8113	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	25662	0	0
T1	0	36	0	0
T2	0	624	0	0
T3	0	100	0	0
T4	0	4	0	0
T5	0	24	0	0
T6	12586	20	0	0
T24	0	32	0	0
T25	0	46	0	0
T26	1282	0	0	0
T27	3770	0	0	0
T28	1253	0	0	0
T29	1228	0	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	0	0	0
T34	1928	0	0	0
T35	0	8	0	0
T36	0	36	0	0
T38	1667	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	167046746	0	0
T6	12586	12574	0	0
T7	2022	1926	0	0
T8	1096	1059	0	0
T26	1282	1215	0	0
T27	3770	3638	0	0
T28	1253	1057	0	0
T29	1228	1199	0	0
T30	1766	1738	0	0
T31	2186	1974	0	0
T32	2165	2112	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Unreachable
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	170052143	133593	0	0
DstReqKnown_A	216315355	215184798	0	0
SrcAckBusyChk_A	170052143	25662	0	0
SrcBusyKnown_A	170052143	167046746	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	133593	0	0
T1	0	126	0	0
T2	0	2193	0	0
T3	0	296	0	0
T4	0	12	0	0
T5	0	177	0	0
T6	12586	51	0	0
T24	0	82	0	0
T25	0	166	0	0
T26	1282	0	0	0
T27	3770	0	0	0
T28	1253	0	0	0
T29	1228	0	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	0	0	0
T34	1928	0	0	0
T35	0	31	0	0
T36	0	296	0	0
T38	1667	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216315355	215184798	0	0
T6	48886	48838	0	0
T7	957	943	0	0
T8	3066	3039	0	0
T26	1320	1306	0	0
T27	1871	1857	0	0
T28	573	532	0	0
T29	4852	4797	0	0
T30	7650	7581	0	0
T31	983	948	0	0
T32	4701	4646	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	25662	0	0
T1	0	36	0	0
T2	0	624	0	0
T3	0	100	0	0
T4	0	4	0	0
T5	0	24	0	0
T6	12586	20	0	0
T24	0	32	0	0
T25	0	46	0	0
T26	1282	0	0	0
T27	3770	0	0	0
T28	1253	0	0	0
T29	1228	0	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	0	0	0
T34	1928	0	0	0
T35	0	8	0	0
T36	0	36	0	0
T38	1667	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	167046746	0	0
T6	12586	12574	0	0
T7	2022	1926	0	0
T8	1096	1059	0	0
T26	1282	1215	0	0
T27	3770	3638	0	0
T28	1253	1057	0	0
T29	1228	1199	0	0
T30	1766	1738	0	0
T31	2186	1974	0	0
T32	2165	2112	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Unreachable
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	170052143	214395	0	0
DstReqKnown_A	108157037	107591902	0	0
SrcAckBusyChk_A	170052143	25662	0	0
SrcBusyKnown_A	170052143	167046746	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	214395	0	0
T1	0	179	0	0
T2	0	3144	0	0
T3	0	392	0	0
T4	0	16	0	0
T5	0	305	0	0
T6	12586	69	0	0
T24	0	82	0	0
T25	0	240	0	0
T26	1282	0	0	0
T27	3770	0	0	0
T28	1253	0	0	0
T29	1228	0	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	0	0	0
T34	1928	0	0	0
T35	0	45	0	0
T36	0	513	0	0
T38	1667	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108157037	107591902	0	0
T6	24443	24419	0	0
T7	479	472	0	0
T8	1532	1518	0	0
T26	659	652	0	0
T27	936	929	0	0
T28	287	266	0	0
T29	2425	2398	0	0
T30	3825	3791	0	0
T31	491	474	0	0
T32	2350	2322	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	25662	0	0
T1	0	36	0	0
T2	0	624	0	0
T3	0	100	0	0
T4	0	4	0	0
T5	0	24	0	0
T6	12586	20	0	0
T24	0	32	0	0
T25	0	46	0	0
T26	1282	0	0	0
T27	3770	0	0	0
T28	1253	0	0	0
T29	1228	0	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	0	0	0
T34	1928	0	0	0
T35	0	8	0	0
T36	0	36	0	0
T38	1667	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	167046746	0	0
T6	12586	12574	0	0
T7	2022	1926	0	0
T8	1096	1059	0	0
T26	1282	1215	0	0
T27	3770	3638	0	0
T28	1253	1057	0	0
T29	1228	1199	0	0
T30	1766	1738	0	0
T31	2186	1974	0	0
T32	2165	2112	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Unreachable
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	170052143	92187	0	0
DstReqKnown_A	463772319	458930410	0	0
SrcAckBusyChk_A	170052143	25662	0	0
SrcBusyKnown_A	170052143	167046746	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	92187	0	0
T1	0	93	0	0
T2	0	1569	0	0
T3	0	251	0	0
T4	0	8	0	0
T5	0	109	0	0
T6	12586	51	0	0
T24	0	82	0	0
T25	0	120	0	0
T26	1282	0	0	0
T27	3770	0	0	0
T28	1253	0	0	0
T29	1228	0	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	0	0	0
T34	1928	0	0	0
T35	0	21	0	0
T36	0	212	0	0
T38	1667	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463772319	458930410	0	0
T6	107874	107748	0	0
T7	2063	1965	0	0
T8	5775	5578	0	0
T26	2671	2530	0	0
T27	4010	3870	0	0
T28	1265	1067	0	0
T29	8780	8568	0	0
T30	16050	15796	0	0
T31	2186	1974	0	0
T32	8662	8451	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	25662	0	0
T1	0	36	0	0
T2	0	624	0	0
T3	0	100	0	0
T4	0	4	0	0
T5	0	24	0	0
T6	12586	20	0	0
T24	0	32	0	0
T25	0	46	0	0
T26	1282	0	0	0
T27	3770	0	0	0
T28	1253	0	0	0
T29	1228	0	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	0	0	0
T34	1928	0	0	0
T35	0	8	0	0
T36	0	36	0	0
T38	1667	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	167046746	0	0
T6	12586	12574	0	0
T7	2022	1926	0	0
T8	1096	1059	0	0
T26	1282	1215	0	0
T27	3770	3638	0	0
T28	1253	1057	0	0
T29	1228	1199	0	0
T30	1766	1738	0	0
T31	2186	1974	0	0
T32	2165	2112	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Unreachable
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	170052143	131252	0	0
DstReqKnown_A	222787306	220461287	0	0
SrcAckBusyChk_A	170052143	25134	0	0
SrcBusyKnown_A	170052143	167046746	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	131252	0	0
T1	0	126	0	0
T2	0	2193	0	0
T3	0	290	0	0
T4	0	10	0	0
T5	0	131	0	0
T6	12586	51	0	0
T24	0	82	0	0
T25	0	166	0	0
T26	1282	0	0	0
T27	3770	0	0	0
T28	1253	0	0	0
T29	1228	0	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	0	0	0
T34	1928	0	0	0
T35	0	30	0	0
T36	0	288	0	0
T38	1667	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222787306	220461287	0	0
T6	54661	54600	0	0
T7	989	943	0	0
T8	2772	2677	0	0
T26	1282	1215	0	0
T27	1925	1858	0	0
T28	607	513	0	0
T29	4214	4112	0	0
T30	7704	7582	0	0
T31	1049	947	0	0
T32	4158	4057	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	25134	0	0
T1	0	36	0	0
T2	0	624	0	0
T3	0	100	0	0
T4	0	3	0	0
T5	0	14	0	0
T6	12586	20	0	0
T24	0	32	0	0
T25	0	46	0	0
T26	1282	0	0	0
T27	3770	0	0	0
T28	1253	0	0	0
T29	1228	0	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	0	0	0
T34	1928	0	0	0
T35	0	8	0	0
T36	0	36	0	0
T38	1667	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	167046746	0	0
T6	12586	12574	0	0
T7	2022	1926	0	0
T8	1096	1059	0	0
T26	1282	1215	0	0
T27	3770	3638	0	0
T28	1253	1057	0	0
T29	1228	1199	0	0
T30	1766	1738	0	0
T31	2186	1974	0	0
T32	2165	2112	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T4,T5,T2
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Unreachable
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	170052143	115406	0	0
DstReqKnown_A	434323933	429743268	0	0
SrcAckBusyChk_A	170052143	31627	0	0
SrcBusyKnown_A	170052143	167046746	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	115406	0	0
T1	0	94	0	0
T2	0	1602	0	0
T3	0	252	0	0
T4	0	18	0	0
T5	0	225	0	0
T6	12586	51	0	0
T24	0	82	0	0
T25	0	120	0	0
T26	1282	0	0	0
T27	3770	0	0	0
T28	1253	0	0	0
T29	1228	0	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	0	0	0
T34	1928	0	0	0
T35	0	24	0	0
T36	0	180	0	0
T38	1667	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	434323933	429743268	0	0
T6	97796	97675	0	0
T7	1980	1887	0	0
T8	5544	5355	0	0
T26	2564	2429	0	0
T27	3849	3714	0	0
T28	1214	1025	0	0
T29	8428	8225	0	0
T30	15408	15163	0	0
T31	2099	1896	0	0
T32	8316	8113	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	31627	0	0
T1	0	36	0	0
T2	0	635	0	0
T3	0	100	0	0
T4	0	8	0	0
T5	0	48	0	0
T6	12586	20	0	0
T24	0	32	0	0
T25	0	46	0	0
T26	1282	0	0	0
T27	3770	0	0	0
T28	1253	0	0	0
T29	1228	0	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	0	0	0
T34	1928	0	0	0
T35	0	8	0	0
T36	0	36	0	0
T38	1667	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	167046746	0	0
T6	12586	12574	0	0
T7	2022	1926	0	0
T8	1096	1059	0	0
T26	1282	1215	0	0
T27	3770	3638	0	0
T28	1253	1057	0	0
T29	1228	1199	0	0
T30	1766	1738	0	0
T31	2186	1974	0	0
T32	2165	2112	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T4,T5,T2
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Unreachable
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	170052143	164899	0	0
DstReqKnown_A	216315355	215184798	0	0
SrcAckBusyChk_A	170052143	31439	0	0
SrcBusyKnown_A	170052143	167046746	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	164899	0	0
T1	0	129	0	0
T2	0	2237	0	0
T3	0	292	0	0
T4	0	27	0	0
T5	0	350	0	0
T6	12586	51	0	0
T24	0	82	0	0
T25	0	166	0	0
T26	1282	0	0	0
T27	3770	0	0	0
T28	1253	0	0	0
T29	1228	0	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	0	0	0
T34	1928	0	0	0
T35	0	31	0	0
T36	0	288	0	0
T38	1667	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216315355	215184798	0	0
T6	48886	48838	0	0
T7	957	943	0	0
T8	3066	3039	0	0
T26	1320	1306	0	0
T27	1871	1857	0	0
T28	573	532	0	0
T29	4852	4797	0	0
T30	7650	7581	0	0
T31	983	948	0	0
T32	4701	4646	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	31439	0	0
T1	0	36	0	0
T2	0	635	0	0
T3	0	100	0	0
T4	0	8	0	0
T5	0	48	0	0
T6	12586	20	0	0
T24	0	32	0	0
T25	0	46	0	0
T26	1282	0	0	0
T27	3770	0	0	0
T28	1253	0	0	0
T29	1228	0	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	0	0	0
T34	1928	0	0	0
T35	0	8	0	0
T36	0	36	0	0
T38	1667	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	167046746	0	0
T6	12586	12574	0	0
T7	2022	1926	0	0
T8	1096	1059	0	0
T26	1282	1215	0	0
T27	3770	3638	0	0
T28	1253	1057	0	0
T29	1228	1199	0	0
T30	1766	1738	0	0
T31	2186	1974	0	0
T32	2165	2112	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T4,T5,T2
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Unreachable
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	170052143	266341	0	0
DstReqKnown_A	108157037	107591902	0	0
SrcAckBusyChk_A	170052143	31458	0	0
SrcBusyKnown_A	170052143	167046746	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	266341	0	0
T1	0	181	0	0
T2	0	3204	0	0
T3	0	393	0	0
T4	0	37	0	0
T5	0	596	0	0
T6	12586	67	0	0
T24	0	82	0	0
T25	0	240	0	0
T26	1282	0	0	0
T27	3770	0	0	0
T28	1253	0	0	0
T29	1228	0	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	0	0	0
T34	1928	0	0	0
T35	0	42	0	0
T36	0	504	0	0
T38	1667	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108157037	107591902	0	0
T6	24443	24419	0	0
T7	479	472	0	0
T8	1532	1518	0	0
T26	659	652	0	0
T27	936	929	0	0
T28	287	266	0	0
T29	2425	2398	0	0
T30	3825	3791	0	0
T31	491	474	0	0
T32	2350	2322	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	31458	0	0
T1	0	36	0	0
T2	0	635	0	0
T3	0	100	0	0
T4	0	8	0	0
T5	0	48	0	0
T6	12586	20	0	0
T24	0	32	0	0
T25	0	46	0	0
T26	1282	0	0	0
T27	3770	0	0	0
T28	1253	0	0	0
T29	1228	0	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	0	0	0
T34	1928	0	0	0
T35	0	8	0	0
T36	0	36	0	0
T38	1667	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	167046746	0	0
T6	12586	12574	0	0
T7	2022	1926	0	0
T8	1096	1059	0	0
T26	1282	1215	0	0
T27	3770	3638	0	0
T28	1253	1057	0	0
T29	1228	1199	0	0
T30	1766	1738	0	0
T31	2186	1974	0	0
T32	2165	2112	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T4,T5,T2
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Unreachable
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	170052143	113807	0	0
DstReqKnown_A	463772319	458930410	0	0
SrcAckBusyChk_A	170052143	31491	0	0
SrcBusyKnown_A	170052143	167046746	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	113807	0	0
T1	0	94	0	0
T2	0	1602	0	0
T3	0	252	0	0
T4	0	18	0	0
T5	0	214	0	0
T6	12586	51	0	0
T24	0	82	0	0
T25	0	120	0	0
T26	1282	0	0	0
T27	3770	0	0	0
T28	1253	0	0	0
T29	1228	0	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	0	0	0
T34	1928	0	0	0
T35	0	21	0	0
T36	0	212	0	0
T38	1667	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463772319	458930410	0	0
T6	107874	107748	0	0
T7	2063	1965	0	0
T8	5775	5578	0	0
T26	2671	2530	0	0
T27	4010	3870	0	0
T28	1265	1067	0	0
T29	8780	8568	0	0
T30	16050	15796	0	0
T31	2186	1974	0	0
T32	8662	8451	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	31491	0	0
T1	0	36	0	0
T2	0	635	0	0
T3	0	100	0	0
T4	0	8	0	0
T5	0	48	0	0
T6	12586	20	0	0
T24	0	32	0	0
T25	0	46	0	0
T26	1282	0	0	0
T27	3770	0	0	0
T28	1253	0	0	0
T29	1228	0	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	0	0	0
T34	1928	0	0	0
T35	0	8	0	0
T36	0	36	0	0
T38	1667	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	167046746	0	0
T6	12586	12574	0	0
T7	2022	1926	0	0
T8	1096	1059	0	0
T26	1282	1215	0	0
T27	3770	3638	0	0
T28	1253	1057	0	0
T29	1228	1199	0	0
T30	1766	1738	0	0
T31	2186	1974	0	0
T32	2165	2112	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Covered	T4,T5,T2
1	0	Covered	T6,T4,T5

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T6
0	1	Unreachable
1	0	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T4,T5
1	1	Covered	T6,T4,T5

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T6
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T7,T8,T6
0	1	-	Covered	T6,T4,T5
0	0	1	Covered	T6,T4,T5
0	0	0	Covered	T7,T8,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	170052143	165079	0	0
DstReqKnown_A	222787306	220461287	0	0
SrcAckBusyChk_A	170052143	31285	0	0
SrcBusyKnown_A	170052143	167046746	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	165079	0	0
T1	0	125	0	0
T2	0	2237	0	0
T3	0	293	0	0
T4	0	28	0	0
T5	0	341	0	0
T6	12586	51	0	0
T24	0	82	0	0
T25	0	166	0	0
T26	1282	0	0	0
T27	3770	0	0	0
T28	1253	0	0	0
T29	1228	0	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	0	0	0
T34	1928	0	0	0
T35	0	30	0	0
T36	0	291	0	0
T38	1667	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222787306	220461287	0	0
T6	54661	54600	0	0
T7	989	943	0	0
T8	2772	2677	0	0
T26	1282	1215	0	0
T27	1925	1858	0	0
T28	607	513	0	0
T29	4214	4112	0	0
T30	7704	7582	0	0
T31	1049	947	0	0
T32	4158	4057	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	31285	0	0
T1	0	36	0	0
T2	0	635	0	0
T3	0	100	0	0
T4	0	8	0	0
T5	0	47	0	0
T6	12586	20	0	0
T24	0	32	0	0
T25	0	46	0	0
T26	1282	0	0	0
T27	3770	0	0	0
T28	1253	0	0	0
T29	1228	0	0	0
T30	1766	0	0	0
T31	2186	0	0	0
T32	2165	0	0	0
T34	1928	0	0	0
T35	0	8	0	0
T36	0	36	0	0
T38	1667	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	170052143	167046746	0	0
T6	12586	12574	0	0
T7	2022	1926	0	0
T8	1096	1059	0	0
T26	1282	1215	0	0
T27	3770	3638	0	0
T28	1253	1057	0	0
T29	1228	1199	0	0
T30	1766	1738	0	0
T31	2186	1974	0	0
T32	2165	2112	0	0