Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T3,T36,T37
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	364990450	728853	0	0
DstReqKnown_A	533956988	507018556	0	0
SrcAckBusyChk_A	364990450	142388	0	0
SrcBusyKnown_A	364990450	336447170	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364990450	728853	0	0
T1	1011530	14128	0	0
T2	1996690	2835	0	0
T3	0	2279	0	0
T4	440670	972	0	0
T16	14140	0	0	0
T17	27290	0	0	0
T18	14800	0	0	0
T28	20790	0	0	0
T29	16050	0	0	0
T32	16170	0	0	0
T33	0	2394	0	0
T34	0	1580	0	0
T35	0	2429	0	0
T36	0	2301	0	0
T37	0	894	0	0
T38	0	1709	0	0
T39	30210	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533956988	507018556	0	0
T4	986114	985414	0	0
T5	52972	52326	0	0
T6	26466	25446	0	0
T7	8366	7006	0	0
T24	46248	45340	0	0
T25	19810	18634	0	0
T26	17962	17126	0	0
T27	12316	10728	0	0
T28	16302	15464	0	0
T29	10088	9078	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364990450	142388	0	0
T1	1011530	1720	0	0
T2	1996690	340	0	0
T3	0	645	0	0
T4	440670	300	0	0
T16	14140	0	0	0
T17	27290	0	0	0
T18	14800	0	0	0
T28	20790	0	0	0
T29	16050	0	0	0
T32	16170	0	0	0
T33	0	280	0	0
T34	0	220	0	0
T35	0	300	0	0
T36	0	486	0	0
T37	0	252	0	0
T38	0	220	0	0
T39	30210	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364990450	336447170	0	0
T4	440670	440370	0	0
T5	19550	19290	0	0
T6	10310	9860	0	0
T7	14050	11700	0	0
T24	36710	35870	0	0
T25	31190	29070	0	0
T26	27430	25910	0	0
T27	9510	8150	0	0
T28	20790	19500	0	0
T29	16050	14360	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	36499045	39880	0	0
DstReqKnown_A	79349664	74770465	0	0
SrcAckBusyChk_A	36499045	11338	0	0
SrcBusyKnown_A	36499045	33644717	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	39880	0	0
T1	101153	886	0	0
T2	199669	174	0	0
T3	0	153	0	0
T4	44067	71	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	0	0	0
T33	0	148	0	0
T34	0	101	0	0
T35	0	174	0	0
T36	0	114	0	0
T37	0	47	0	0
T38	0	105	0	0
T39	3021	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79349664	74770465	0	0
T4	141708	141587	0	0
T5	7823	7716	0	0
T6	3962	3786	0	0
T7	1316	1085	0	0
T24	7049	6887	0	0
T25	2995	2792	0	0
T26	2686	2538	0	0
T27	1901	1629	0	0
T28	2404	2255	0	0
T29	1541	1379	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	11338	0	0
T1	101153	172	0	0
T2	199669	34	0	0
T3	0	59	0	0
T4	44067	30	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	0	0	0
T33	0	28	0	0
T34	0	22	0	0
T35	0	30	0	0
T36	0	34	0	0
T37	0	18	0	0
T38	0	22	0	0
T39	3021	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	33644717	0	0
T4	44067	44037	0	0
T5	1955	1929	0	0
T6	1031	986	0	0
T7	1405	1170	0	0
T24	3671	3587	0	0
T25	3119	2907	0	0
T26	2743	2591	0	0
T27	951	815	0	0
T28	2079	1950	0	0
T29	1605	1436	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	36499045	56530	0	0
DstReqKnown_A	38714923	37590330	0	0
SrcAckBusyChk_A	36499045	11338	0	0
SrcBusyKnown_A	36499045	33644717	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	56530	0	0
T1	101153	1422	0	0
T2	199669	279	0	0
T3	0	212	0	0
T4	44067	101	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	0	0	0
T33	0	234	0	0
T34	0	156	0	0
T35	0	248	0	0
T36	0	160	0	0
T37	0	63	0	0
T38	0	172	0	0
T39	3021	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38714923	37590330	0	0
T4	70821	70793	0	0
T5	4402	4368	0	0
T6	2109	2067	0	0
T7	605	543	0	0
T24	3471	3443	0	0
T25	1530	1482	0	0
T26	1438	1410	0	0
T27	883	814	0	0
T28	1361	1333	0	0
T29	751	689	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	11338	0	0
T1	101153	172	0	0
T2	199669	34	0	0
T3	0	59	0	0
T4	44067	30	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	0	0	0
T33	0	28	0	0
T34	0	22	0	0
T35	0	30	0	0
T36	0	34	0	0
T37	0	18	0	0
T38	0	22	0	0
T39	3021	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	33644717	0	0
T4	44067	44037	0	0
T5	1955	1929	0	0
T6	1031	986	0	0
T7	1405	1170	0	0
T24	3671	3587	0	0
T25	3119	2907	0	0
T26	2743	2591	0	0
T27	951	815	0	0
T28	2079	1950	0	0
T29	1605	1436	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	36499045	89891	0	0
DstReqKnown_A	19357069	18794865	0	0
SrcAckBusyChk_A	36499045	11338	0	0
SrcBusyKnown_A	36499045	33644717	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	89891	0	0
T1	101153	2473	0	0
T2	199669	484	0	0
T3	0	305	0	0
T4	44067	142	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	0	0	0
T33	0	407	0	0
T34	0	281	0	0
T35	0	410	0	0
T36	0	248	0	0
T37	0	90	0	0
T38	0	298	0	0
T39	3021	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19357069	18794865	0	0
T4	35411	35397	0	0
T5	2200	2183	0	0
T6	1054	1033	0	0
T7	302	271	0	0
T24	1736	1722	0	0
T25	764	740	0	0
T26	716	702	0	0
T27	442	408	0	0
T28	680	666	0	0
T29	376	345	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	11338	0	0
T1	101153	172	0	0
T2	199669	34	0	0
T3	0	59	0	0
T4	44067	30	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	0	0	0
T33	0	28	0	0
T34	0	22	0	0
T35	0	30	0	0
T36	0	34	0	0
T37	0	18	0	0
T38	0	22	0	0
T39	3021	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	33644717	0	0
T4	44067	44037	0	0
T5	1955	1929	0	0
T6	1031	986	0	0
T7	1405	1170	0	0
T24	3671	3587	0	0
T25	3119	2907	0	0
T26	2743	2591	0	0
T27	951	815	0	0
T28	2079	1950	0	0
T29	1605	1436	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	36499045	39700	0	0
DstReqKnown_A	87581275	82728084	0	0
SrcAckBusyChk_A	36499045	11338	0	0
SrcBusyKnown_A	36499045	33644717	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	39700	0	0
T1	101153	859	0	0
T2	199669	202	0	0
T3	0	153	0	0
T4	44067	71	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	0	0	0
T33	0	170	0	0
T34	0	98	0	0
T35	0	141	0	0
T36	0	113	0	0
T37	0	47	0	0
T38	0	124	0	0
T39	3021	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87581275	82728084	0	0
T4	165619	165492	0	0
T5	8150	8038	0	0
T6	4127	3944	0	0
T7	1316	1075	0	0
T24	7343	7174	0	0
T25	3119	2907	0	0
T26	2798	2644	0	0
T27	1981	1698	0	0
T28	2504	2350	0	0
T29	1605	1436	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	11338	0	0
T1	101153	172	0	0
T2	199669	34	0	0
T3	0	59	0	0
T4	44067	30	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	0	0	0
T33	0	28	0	0
T34	0	22	0	0
T35	0	30	0	0
T36	0	34	0	0
T37	0	18	0	0
T38	0	22	0	0
T39	3021	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	33644717	0	0
T4	44067	44037	0	0
T5	1955	1929	0	0
T6	1031	986	0	0
T7	1405	1170	0	0
T24	3671	3587	0	0
T25	3119	2907	0	0
T26	2743	2591	0	0
T27	951	815	0	0
T28	2079	1950	0	0
T29	1605	1436	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	36499045	54431	0	0
DstReqKnown_A	41975563	39625534	0	0
SrcAckBusyChk_A	36499045	10891	0	0
SrcBusyKnown_A	36499045	33644717	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	54431	0	0
T1	101153	1435	0	0
T2	199669	271	0	0
T3	0	212	0	0
T4	44067	101	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	0	0	0
T33	0	238	0	0
T34	0	155	0	0
T35	0	231	0	0
T36	0	94	0	0
T37	0	41	0	0
T38	0	166	0	0
T39	3021	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41975563	39625534	0	0
T4	79498	79438	0	0
T5	3911	3858	0	0
T6	1981	1893	0	0
T7	644	529	0	0
T24	3525	3444	0	0
T25	1497	1396	0	0
T26	1343	1269	0	0
T27	951	815	0	0
T28	1202	1128	0	0
T29	771	690	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	10891	0	0
T1	101153	172	0	0
T2	199669	34	0	0
T3	0	59	0	0
T4	44067	30	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	0	0	0
T33	0	28	0	0
T34	0	22	0	0
T35	0	30	0	0
T36	0	17	0	0
T37	0	9	0	0
T38	0	22	0	0
T39	3021	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	33644717	0	0
T4	44067	44037	0	0
T5	1955	1929	0	0
T6	1031	986	0	0
T7	1405	1170	0	0
T24	3671	3587	0	0
T25	3119	2907	0	0
T26	2743	2591	0	0
T27	951	815	0	0
T28	2079	1950	0	0
T29	1605	1436	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T3,T36,T37
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	36499045	63258	0	0
DstReqKnown_A	79349664	74770465	0	0
SrcAckBusyChk_A	36499045	17356	0	0
SrcBusyKnown_A	36499045	33644717	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	63258	0	0
T1	101153	890	0	0
T2	199669	175	0	0
T3	0	184	0	0
T4	44067	71	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	0	0	0
T33	0	148	0	0
T34	0	101	0	0
T35	0	174	0	0
T36	0	229	0	0
T37	0	92	0	0
T38	0	105	0	0
T39	3021	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	79349664	74770465	0	0
T4	141708	141587	0	0
T5	7823	7716	0	0
T6	3962	3786	0	0
T7	1316	1085	0	0
T24	7049	6887	0	0
T25	2995	2792	0	0
T26	2686	2538	0	0
T27	1901	1629	0	0
T28	2404	2255	0	0
T29	1541	1379	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	17356	0	0
T1	101153	172	0	0
T2	199669	34	0	0
T3	0	70	0	0
T4	44067	30	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	0	0	0
T33	0	28	0	0
T34	0	22	0	0
T35	0	30	0	0
T36	0	68	0	0
T37	0	36	0	0
T38	0	22	0	0
T39	3021	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	33644717	0	0
T4	44067	44037	0	0
T5	1955	1929	0	0
T6	1031	986	0	0
T7	1405	1170	0	0
T24	3671	3587	0	0
T25	3119	2907	0	0
T26	2743	2591	0	0
T27	951	815	0	0
T28	2079	1950	0	0
T29	1605	1436	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T3,T36,T37
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	36499045	90175	0	0
DstReqKnown_A	38714923	37590330	0	0
SrcAckBusyChk_A	36499045	17367	0	0
SrcBusyKnown_A	36499045	33644717	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	90175	0	0
T1	101153	1413	0	0
T2	199669	277	0	0
T3	0	254	0	0
T4	44067	101	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	0	0	0
T33	0	231	0	0
T34	0	157	0	0
T35	0	252	0	0
T36	0	315	0	0
T37	0	128	0	0
T38	0	165	0	0
T39	3021	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38714923	37590330	0	0
T4	70821	70793	0	0
T5	4402	4368	0	0
T6	2109	2067	0	0
T7	605	543	0	0
T24	3471	3443	0	0
T25	1530	1482	0	0
T26	1438	1410	0	0
T27	883	814	0	0
T28	1361	1333	0	0
T29	751	689	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	17367	0	0
T1	101153	172	0	0
T2	199669	34	0	0
T3	0	70	0	0
T4	44067	30	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	0	0	0
T33	0	28	0	0
T34	0	22	0	0
T35	0	30	0	0
T36	0	68	0	0
T37	0	36	0	0
T38	0	22	0	0
T39	3021	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	33644717	0	0
T4	44067	44037	0	0
T5	1955	1929	0	0
T6	1031	986	0	0
T7	1405	1170	0	0
T24	3671	3587	0	0
T25	3119	2907	0	0
T26	2743	2591	0	0
T27	951	815	0	0
T28	2079	1950	0	0
T29	1605	1436	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T3,T36,T37
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	36499045	144517	0	0
DstReqKnown_A	19357069	18794865	0	0
SrcAckBusyChk_A	36499045	17251	0	0
SrcBusyKnown_A	36499045	33644717	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	144517	0	0
T1	101153	2473	0	0
T2	199669	498	0	0
T3	0	368	0	0
T4	44067	142	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	0	0	0
T33	0	413	0	0
T34	0	277	0	0
T35	0	426	0	0
T36	0	497	0	0
T37	0	173	0	0
T38	0	285	0	0
T39	3021	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19357069	18794865	0	0
T4	35411	35397	0	0
T5	2200	2183	0	0
T6	1054	1033	0	0
T7	302	271	0	0
T24	1736	1722	0	0
T25	764	740	0	0
T26	716	702	0	0
T27	442	408	0	0
T28	680	666	0	0
T29	376	345	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	17251	0	0
T1	101153	172	0	0
T2	199669	34	0	0
T3	0	70	0	0
T4	44067	30	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	0	0	0
T33	0	28	0	0
T34	0	22	0	0
T35	0	30	0	0
T36	0	68	0	0
T37	0	36	0	0
T38	0	22	0	0
T39	3021	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	33644717	0	0
T4	44067	44037	0	0
T5	1955	1929	0	0
T6	1031	986	0	0
T7	1405	1170	0	0
T24	3671	3587	0	0
T25	3119	2907	0	0
T26	2743	2591	0	0
T27	951	815	0	0
T28	2079	1950	0	0
T29	1605	1436	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T3,T36,T37
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	36499045	62476	0	0
DstReqKnown_A	87581275	82728084	0	0
SrcAckBusyChk_A	36499045	17297	0	0
SrcBusyKnown_A	36499045	33644717	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	62476	0	0
T1	101153	867	0	0
T2	199669	202	0	0
T3	0	184	0	0
T4	44067	71	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	0	0	0
T33	0	170	0	0
T34	0	97	0	0
T35	0	141	0	0
T36	0	228	0	0
T37	0	92	0	0
T38	0	124	0	0
T39	3021	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87581275	82728084	0	0
T4	165619	165492	0	0
T5	8150	8038	0	0
T6	4127	3944	0	0
T7	1316	1075	0	0
T24	7343	7174	0	0
T25	3119	2907	0	0
T26	2798	2644	0	0
T27	1981	1698	0	0
T28	2504	2350	0	0
T29	1605	1436	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	17297	0	0
T1	101153	172	0	0
T2	199669	34	0	0
T3	0	70	0	0
T4	44067	30	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	0	0	0
T33	0	28	0	0
T34	0	22	0	0
T35	0	30	0	0
T36	0	68	0	0
T37	0	36	0	0
T38	0	22	0	0
T39	3021	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	33644717	0	0
T4	44067	44037	0	0
T5	1955	1929	0	0
T6	1031	986	0	0
T7	1405	1170	0	0
T24	3671	3587	0	0
T25	3119	2907	0	0
T26	2743	2591	0	0
T27	951	815	0	0
T28	2079	1950	0	0
T29	1605	1436	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T3,T36,T37
1	0	Covered	T4,T1,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T1,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T4,T1,T2
0	0	1	Covered	T4,T1,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	36499045	87995	0	0
DstReqKnown_A	41975563	39625534	0	0
SrcAckBusyChk_A	36499045	16874	0	0
SrcBusyKnown_A	36499045	33644717	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	87995	0	0
T1	101153	1410	0	0
T2	199669	273	0	0
T3	0	254	0	0
T4	44067	101	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	0	0	0
T33	0	235	0	0
T34	0	157	0	0
T35	0	232	0	0
T36	0	303	0	0
T37	0	121	0	0
T38	0	165	0	0
T39	3021	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41975563	39625534	0	0
T4	79498	79438	0	0
T5	3911	3858	0	0
T6	1981	1893	0	0
T7	644	529	0	0
T24	3525	3444	0	0
T25	1497	1396	0	0
T26	1343	1269	0	0
T27	951	815	0	0
T28	1202	1128	0	0
T29	771	690	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	16874	0	0
T1	101153	172	0	0
T2	199669	34	0	0
T3	0	70	0	0
T4	44067	30	0	0
T16	1414	0	0	0
T17	2729	0	0	0
T18	1480	0	0	0
T28	2079	0	0	0
T29	1605	0	0	0
T32	1617	0	0	0
T33	0	28	0	0
T34	0	22	0	0
T35	0	30	0	0
T36	0	61	0	0
T37	0	27	0	0
T38	0	22	0	0
T39	3021	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36499045	33644717	0	0
T4	44067	44037	0	0
T5	1955	1929	0	0
T6	1031	986	0	0
T7	1405	1170	0	0
T24	3671	3587	0	0
T25	3119	2907	0	0
T26	2743	2591	0	0
T27	951	815	0	0
T28	2079	1950	0	0
T29	1605	1436	0	0