Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1212305607	418463	0	0
SrcPulseCheck_M	1058204510	416548	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1212305607	418463
T1	0	304
T2	0	1200
T4	0	180
T5	0	20
T6	0	10
T7	1139855	861
T8	256538	324
T9	0	206
T31	0	52
T32	23619	0
T33	12616	0
T34	9963	0
T35	12669	0
T36	16705	0
T37	0	562
T38	80216	0
T44	0	236
T45	0	826
T46	0	736
T49	24073	0
T50	6944	0
T72	3024	1
T73	14730	1
T74	10333	0
T76	8738	3
T78	13822	3
T132	14054	2
T133	4717	1
T134	10160	2
T135	5352	2
T136	2872	0
T137	6145	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1058204510	416548
T1	0	304
T2	0	1200
T4	0	180
T5	0	20
T6	0	10
T7	447847	861
T8	64446	324
T9	0	206
T31	0	52
T32	7519	0
T33	5325	0
T34	5828	0
T35	5401	0
T36	5122	0
T37	0	562
T38	21331	0
T44	0	236
T45	0	826
T46	0	736
T49	6509	0
T50	4082	0
T72	20138	1
T73	68254	1
T74	19024	0
T76	7134	3
T78	11348	3
T132	7674	2
T133	7480	1
T134	19695	2
T135	9317	2
T136	5523	0
T137	9568	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	71222213	10658	0	0
SrcPulseCheck_M	33464451	10658	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	71222213	10658
T4	0	36
T5	0	4
T6	0	2
T7	259188	35
T8	60073	12
T9	0	14
T32	5656	0
T33	2948	0
T34	2095	0
T35	2970	0
T36	4182	0
T37	0	26
T38	20528	0
T44	0	8
T45	0	30
T46	0	28
T49	6165	0
T50	1496	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33464451	10658
T4	0	36
T5	0	4
T6	0	2
T7	149997	35
T8	16922	12
T9	0	14
T32	1413	0
T33	1505	0
T34	2095	0
T35	1546	0
T36	915	0
T37	0	26
T38	2566	0
T44	0	8
T45	0	30
T46	0	28
T49	835	0
T50	1481	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	71222213	16516	0	0
SrcPulseCheck_M	33464451	16530	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	71222213	16516
T4	0	72
T5	0	8
T6	0	4
T7	259188	43
T8	60073	12
T9	0	14
T32	5656	0
T33	2948	0
T34	2095	0
T35	2970	0
T36	4182	0
T37	0	26
T38	20528	0
T44	0	8
T45	0	30
T46	0	28
T49	6165	0
T50	1496	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33464451	16530
T4	0	72
T5	0	8
T6	0	4
T7	149997	43
T8	16922	12
T9	0	14
T32	1413	0
T33	1505	0
T34	2095	0
T35	1546	0
T36	915	0
T37	0	26
T38	2566	0
T44	0	8
T45	0	30
T46	0	28
T49	835	0
T50	1481	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33464451	16508	0	0
SrcPulseCheck_M	71222213	16520	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33464451	16508
T4	0	72
T5	0	8
T6	0	4
T7	149997	43
T8	16922	12
T9	0	14
T32	1413	0
T33	1505	0
T34	2095	0
T35	1546	0
T36	915	0
T37	0	26
T38	2566	0
T44	0	8
T45	0	30
T46	0	28
T49	835	0
T50	1481	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	71222213	16520
T4	0	72
T5	0	8
T6	0	4
T7	259188	43
T8	60073	12
T9	0	14
T32	5656	0
T33	2948	0
T34	2095	0
T35	2970	0
T36	4182	0
T37	0	26
T38	20528	0
T44	0	8
T45	0	30
T46	0	28
T49	6165	0
T50	1496	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	34620872	10658	0	0
SrcPulseCheck_M	33464451	10658	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	34620872	10658
T4	0	36
T5	0	4
T6	0	2
T7	124765	35
T8	29990	12
T9	0	14
T32	3045	0
T33	1455	0
T34	1026	0
T35	1445	0
T36	2072	0
T37	0	26
T38	10211	0
T44	0	8
T45	0	30
T46	0	28
T49	3043	0
T50	688	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33464451	10658
T4	0	36
T5	0	4
T6	0	2
T7	149997	35
T8	16922	12
T9	0	14
T32	1413	0
T33	1505	0
T34	2095	0
T35	1546	0
T36	915	0
T37	0	26
T38	2566	0
T44	0	8
T45	0	30
T46	0	28
T49	835	0
T50	1481	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	34620872	16509	0	0
SrcPulseCheck_M	33464451	16547	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	34620872	16509
T4	0	72
T5	0	8
T6	0	4
T7	124765	43
T8	29990	12
T9	0	14
T32	3045	0
T33	1455	0
T34	1026	0
T35	1445	0
T36	2072	0
T37	0	26
T38	10211	0
T44	0	8
T45	0	30
T46	0	28
T49	3043	0
T50	688	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33464451	16547
T4	0	72
T5	0	8
T6	0	4
T7	149997	43
T8	16922	12
T9	0	14
T32	1413	0
T33	1505	0
T34	2095	0
T35	1546	0
T36	915	0
T37	0	26
T38	2566	0
T44	0	8
T45	0	30
T46	0	28
T49	835	0
T50	1481	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33464451	16499	0	0
SrcPulseCheck_M	34620872	16514	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33464451	16499
T4	0	72
T5	0	8
T6	0	4
T7	149997	43
T8	16922	12
T9	0	14
T32	1413	0
T33	1505	0
T34	2095	0
T35	1546	0
T36	915	0
T37	0	26
T38	2566	0
T44	0	8
T45	0	30
T46	0	28
T49	835	0
T50	1481	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	34620872	16514
T4	0	72
T5	0	8
T6	0	4
T7	124765	43
T8	29990	12
T9	0	14
T32	3045	0
T33	1455	0
T34	1026	0
T35	1445	0
T36	2072	0
T37	0	26
T38	10211	0
T44	0	8
T45	0	30
T46	0	28
T49	3043	0
T50	688	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	17310071	10658	0	0
SrcPulseCheck_M	33464451	10658	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	17310071	10658
T4	0	36
T5	0	4
T6	0	2
T7	62379	35
T8	14995	12
T9	0	14
T32	1523	0
T33	727	0
T34	512	0
T35	723	0
T36	1036	0
T37	0	26
T38	5105	0
T44	0	8
T45	0	30
T46	0	28
T49	1521	0
T50	344	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33464451	10658
T4	0	36
T5	0	4
T6	0	2
T7	149997	35
T8	16922	12
T9	0	14
T32	1413	0
T33	1505	0
T34	2095	0
T35	1546	0
T36	915	0
T37	0	26
T38	2566	0
T44	0	8
T45	0	30
T46	0	28
T49	835	0
T50	1481	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	17310071	16473	0	0
SrcPulseCheck_M	33464451	16508	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	17310071	16473
T4	0	72
T5	0	8
T6	0	4
T7	62379	43
T8	14995	12
T9	0	14
T32	1523	0
T33	727	0
T34	512	0
T35	723	0
T36	1036	0
T37	0	26
T38	5105	0
T44	0	8
T45	0	30
T46	0	28
T49	1521	0
T50	344	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33464451	16508
T4	0	72
T5	0	8
T6	0	4
T7	149997	43
T8	16922	12
T9	0	14
T32	1413	0
T33	1505	0
T34	2095	0
T35	1546	0
T36	915	0
T37	0	26
T38	2566	0
T44	0	8
T45	0	30
T46	0	28
T49	835	0
T50	1481	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33464451	16472	0	0
SrcPulseCheck_M	17310071	16475	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33464451	16472
T4	0	72
T5	0	8
T6	0	4
T7	149997	43
T8	16922	12
T9	0	14
T32	1413	0
T33	1505	0
T34	2095	0
T35	1546	0
T36	915	0
T37	0	26
T38	2566	0
T44	0	8
T45	0	30
T46	0	28
T49	835	0
T50	1481	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	17310071	16475
T4	0	72
T5	0	8
T6	0	4
T7	62379	43
T8	14995	12
T9	0	14
T32	1523	0
T33	727	0
T34	512	0
T35	723	0
T36	1036	0
T37	0	26
T38	5105	0
T44	0	8
T45	0	30
T46	0	28
T49	1521	0
T50	344	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	78547035	10658	0	0
SrcPulseCheck_M	33464451	10658	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	78547035	10658
T4	0	36
T5	0	4
T6	0	2
T7	293996	35
T8	74578	12
T9	0	14
T32	5892	0
T33	3071	0
T34	2183	0
T35	3095	0
T36	4356	0
T37	0	26
T38	21384	0
T44	0	8
T45	0	30
T46	0	28
T49	6423	0
T50	1559	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33464451	10658
T4	0	36
T5	0	4
T6	0	2
T7	149997	35
T8	16922	12
T9	0	14
T32	1413	0
T33	1505	0
T34	2095	0
T35	1546	0
T36	915	0
T37	0	26
T38	2566	0
T44	0	8
T45	0	30
T46	0	28
T49	835	0
T50	1481	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	78547035	16328	0	0
SrcPulseCheck_M	33464451	16337	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	78547035	16328
T4	0	72
T5	0	8
T6	0	4
T7	293996	43
T8	74578	12
T9	0	14
T32	5892	0
T33	3071	0
T34	2183	0
T35	3095	0
T36	4356	0
T37	0	26
T38	21384	0
T44	0	8
T45	0	30
T46	0	28
T49	6423	0
T50	1559	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33464451	16337
T4	0	72
T5	0	8
T6	0	4
T7	149997	43
T8	16922	12
T9	0	14
T32	1413	0
T33	1505	0
T34	2095	0
T35	1546	0
T36	915	0
T37	0	26
T38	2566	0
T44	0	8
T45	0	30
T46	0	28
T49	835	0
T50	1481	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33464451	16320	0	0
SrcPulseCheck_M	78547035	16330	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33464451	16320
T4	0	72
T5	0	8
T6	0	4
T7	149997	43
T8	16922	12
T9	0	14
T32	1413	0
T33	1505	0
T34	2095	0
T35	1546	0
T36	915	0
T37	0	26
T38	2566	0
T44	0	8
T45	0	30
T46	0	28
T49	835	0
T50	1481	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	78547035	16330
T4	0	72
T5	0	8
T6	0	4
T7	293996	43
T8	74578	12
T9	0	14
T32	5892	0
T33	3071	0
T34	2183	0
T35	3095	0
T36	4356	0
T37	0	26
T38	21384	0
T44	0	8
T45	0	30
T46	0	28
T49	6423	0
T50	1559	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	37708677	10159	0	0
SrcPulseCheck_M	33464451	10658	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	37708677	10159
T4	0	18
T5	0	2
T6	0	2
T7	132480	35
T8	32917	12
T9	0	14
T32	2828	0
T33	1474	0
T34	1047	0
T35	1485	0
T36	2091	0
T37	0	26
T38	10265	0
T44	0	8
T45	0	30
T46	0	28
T49	3082	0
T50	748	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33464451	10658
T4	0	36
T5	0	4
T6	0	2
T7	149997	35
T8	16922	12
T9	0	14
T32	1413	0
T33	1505	0
T34	2095	0
T35	1546	0
T36	915	0
T37	0	26
T38	2566	0
T44	0	8
T45	0	30
T46	0	28
T49	835	0
T50	1481	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	37708677	16153	0	0
SrcPulseCheck_M	33464451	16416	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	37708677	16153
T4	0	68
T5	0	8
T6	0	4
T7	132480	43
T8	32917	12
T9	0	14
T32	2828	0
T33	1474	0
T34	1047	0
T35	1485	0
T36	2091	0
T37	0	26
T38	10265	0
T44	0	8
T45	0	30
T46	0	28
T49	3082	0
T50	748	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	33464451	16416
T4	0	72
T5	0	8
T6	0	4
T7	149997	43
T8	16922	12
T9	0	14
T32	1413	0
T33	1505	0
T34	2095	0
T35	1546	0
T36	915	0
T37	0	26
T38	2566	0
T44	0	8
T45	0	30
T46	0	28
T49	835	0
T50	1481	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33464451	16040	0	0
SrcPulseCheck_M	37708677	16199	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33464451	16040
T4	0	64
T5	0	8
T6	0	4
T7	149997	43
T8	16922	12
T9	0	14
T32	1413	0
T33	1505	0
T34	2095	0
T35	1546	0
T36	915	0
T37	0	26
T38	2566	0
T44	0	8
T45	0	30
T46	0	28
T49	835	0
T50	1481	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	37708677	16199
T4	0	70
T5	0	8
T6	0	4
T7	132480	43
T8	32917	12
T9	0	14
T32	2828	0
T33	1474	0
T34	1047	0
T35	1485	0
T36	2091	0
T37	0	26
T38	10265	0
T44	0	8
T45	0	30
T46	0	28
T49	3082	0
T50	748	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T72,T75,T76
1	0	Covered	T72,T75,T76
1	1	Covered	T76,T138,T139

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T72,T75,T76
1	0	Covered	T76,T138,T139
1	1	Covered	T72,T75,T76

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33464451	26	0	0
SrcPulseCheck_M	71222213	26	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33464451	26
T72	1512	2
T75	15983	1
T76	4369	2
T77	8435	1
T132	7027	1
T135	5352	1
T136	2872	1
T138	13040	2
T140	11678	1
T141	8656	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	71222213	26
T72	20747	2
T75	15983	1
T76	8388	2
T77	14995	1
T132	8432	1
T135	20553	1
T136	11987	1
T138	12643	2
T140	22422	1
T141	8840	1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T72,T73,T75
1	0	Covered	T72,T73,T75
1	1	Covered	T140,T142,T139

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T72,T73,T75
1	0	Covered	T140,T142,T139
1	1	Covered	T72,T73,T75

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33464451	35	0	0
SrcPulseCheck_M	71222213	35	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33464451	35
T72	1512	2
T73	7365	2
T75	15983	1
T76	4369	1
T77	8435	2
T78	6911	1
T135	5352	2
T136	2872	1
T140	11678	3
T141	8656	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	71222213	35
T72	20747	2
T73	70705	2
T75	15983	1
T76	8388	1
T77	14995	2
T78	13269	1
T135	20553	2
T136	11987	1
T140	22422	3
T141	8840	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T72,T73,T76
1	0	Covered	T72,T73,T76
1	1	Covered	T76,T78,T136

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T72,T73,T76
1	0	Covered	T76,T78,T136
1	1	Covered	T72,T73,T76

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33464451	37	0	0
SrcPulseCheck_M	34620872	37	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33464451	37
T72	1512	1
T73	7365	1
T76	4369	3
T78	6911	3
T132	7027	2
T133	4717	1
T134	10160	2
T135	5352	2
T136	2872	2
T137	6145	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	34620872	37
T72	10069	1
T73	34127	1
T76	3567	3
T78	5674	3
T132	3837	2
T133	7480	1
T134	19695	2
T135	9317	2
T136	5523	2
T137	9568	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T72,T73,T74
1	0	Covered	T72,T73,T74
1	1	Covered	T79,T143

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T72,T73,T74
1	0	Covered	T79,T143
1	1	Covered	T72,T73,T74

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33464451	40	0	0
SrcPulseCheck_M	34620872	40	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33464451	40
T72	1512	1
T73	7365	1
T74	10333	1
T75	15983	1
T76	4369	1
T77	8435	1
T78	6911	2
T79	10985	3
T80	3342	1
T132	7027	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	34620872	40
T72	10069	1
T73	34127	1
T74	19024	1
T75	7239	1
T76	3567	1
T77	6662	1
T78	5674	2
T79	20111	3
T80	7626	1
T132	3837	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T72,T73,T74
1	0	Covered	T72,T73,T74
1	1	Covered	T74,T77,T144

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T72,T73,T74
1	0	Covered	T74,T77,T144
1	1	Covered	T72,T73,T74

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33464451	41	0	0
SrcPulseCheck_M	17310071	41	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33464451	41
T72	1512	1
T73	7365	1
T74	10333	3
T76	4369	1
T77	8435	3
T78	6911	1
T80	3342	2
T134	10160	1
T145	8674	1
T146	4405	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	17310071	41
T72	5035	1
T73	17061	1
T74	9509	3
T76	1786	1
T77	3330	3
T78	2835	1
T80	3815	2
T134	9847	1
T145	1796	1
T146	4793	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T72,T73,T74
1	0	Covered	T72,T73,T74
1	1	Covered	T74,T142,T144

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T72,T73,T74
1	0	Covered	T74,T142,T144
1	1	Covered	T72,T73,T74

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33464451	41	0	0
SrcPulseCheck_M	17310071	41	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33464451	41
T72	1512	1
T73	7365	1
T74	10333	3
T76	4369	1
T77	8435	1
T78	6911	1
T80	3342	2
T134	10160	1
T145	8674	1
T146	4405	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	17310071	41
T72	5035	1
T73	17061	1
T74	9509	3
T76	1786	1
T77	3330	1
T78	2835	1
T80	3815	2
T134	9847	1
T145	1796	1
T146	4793	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T73,T74,T79
1	0	Covered	T73,T74,T79
1	1	Covered	T77,T138,T142

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T73,T74,T79
1	0	Covered	T77,T138,T142
1	1	Covered	T73,T74,T79

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33464451	27	0	0
SrcPulseCheck_M	78547035	27	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33464451	27
T73	7365	1
T74	10333	1
T77	8435	2
T78	6911	1
T79	10985	1
T133	4717	1
T135	5352	1
T138	13040	2
T141	8656	1
T147	10338	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	78547035	27
T73	73654	1
T74	41334	1
T77	15621	2
T78	13822	1
T79	43944	1
T133	16848	1
T135	21411	1
T138	13171	2
T141	9209	1
T147	11748	2

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T73,T79,T77
1	0	Covered	T73,T79,T77
1	1	Covered	T73,T79,T77

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T73,T79,T77
1	0	Covered	T73,T79,T77
1	1	Covered	T73,T79,T77

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33464451	31	0	0
SrcPulseCheck_M	78547035	31	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33464451	31
T73	7365	4
T77	8435	3
T78	6911	1
T79	10985	2
T135	5352	2
T137	6145	1
T138	13040	1
T141	8656	2
T147	10338	1
T148	5469	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	78547035	31
T73	73654	4
T77	15621	3
T78	13822	1
T79	43944	2
T135	21411	2
T137	21193	1
T138	13171	1
T141	9209	2
T147	11748	1
T148	10517	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T72,T74,T75
1	0	Covered	T72,T74,T75
1	1	Covered	T78

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T72,T74,T75
1	0	Covered	T78
1	1	Covered	T72,T74,T75

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33464451	29	0	0
SrcPulseCheck_M	37708677	29	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33464451	29
T72	1512	2
T74	10333	1
T75	15983	1
T76	4369	1
T77	8435	1
T78	6911	4
T79	10985	1
T132	7027	1
T140	11678	1
T145	8674	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	37708677	29
T72	10374	2
T74	19840	1
T75	7992	1
T76	4194	1
T77	7497	1
T78	6635	4
T79	21092	1
T132	4216	1
T140	11212	1
T145	4206	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T72,T73,T74
1	0	Covered	T72,T73,T74
1	1	Covered	T135,T149

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T72,T73,T74
1	0	Covered	T135,T149
1	1	Covered	T72,T73,T74

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33464451	23	0	0
SrcPulseCheck_M	37708677	23	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33464451	23
T72	1512	1
T73	7365	1
T74	10333	1
T77	8435	1
T78	6911	3
T79	10985	1
T133	4717	1
T140	11678	1
T145	8674	1
T146	4405	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	37708677	23
T72	10374	1
T73	35355	1
T74	19840	1
T77	7497	1
T78	6635	3
T79	21092	1
T133	8087	1
T140	11212	1
T145	4206	1
T146	10067	1

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	68804715	37527	0	0
SrcPulseCheck_M	1050405	37233	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	68804715	37527
T1	0	76
T2	0	288
T7	259188	173
T8	60073	68
T9	0	41
T31	0	13
T32	5656	0
T33	2948	0
T34	2095	0
T35	2970	0
T36	4182	0
T37	0	112
T38	20528	0
T44	0	53
T45	0	163
T46	0	145
T49	6165	0
T50	1496	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1050405	37233
T1	0	76
T2	0	288
T7	5760	173
T8	147	68
T9	0	41
T31	0	13
T32	412	0
T33	215	0
T34	153	0
T35	216	0
T36	305	0
T37	0	112
T38	1497	0
T44	0	53
T45	0	163
T46	0	145
T49	449	0
T50	108	0

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	33458774	37295	0	0
SrcPulseCheck_M	1050405	37006	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	33458774	37295
T1	0	76
T2	0	288
T7	124765	173
T8	29990	68
T9	0	41
T31	0	13
T32	3045	0
T33	1455	0
T34	1026	0
T35	1445	0
T36	2072	0
T37	0	112
T38	10211	0
T44	0	53
T45	0	163
T46	0	145
T49	3043	0
T50	688	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1050405	37006
T1	0	76
T2	0	288
T7	5760	173
T8	147	68
T9	0	41
T31	0	13
T32	412	0
T33	215	0
T34	153	0
T35	216	0
T36	305	0
T37	0	112
T38	1497	0
T44	0	53
T45	0	163
T46	0	145
T49	449	0
T50	108	0

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	16729015	36989	0	0
SrcPulseCheck_M	1050405	36707	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	16729015	36989
T1	0	76
T2	0	288
T7	62379	173
T8	14995	66
T9	0	41
T31	0	13
T32	1523	0
T33	727	0
T34	512	0
T35	723	0
T36	1036	0
T37	0	112
T38	5105	0
T44	0	53
T45	0	163
T46	0	145
T49	1521	0
T50	344	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1050405	36707
T1	0	76
T2	0	288
T7	5760	173
T8	147	66
T9	0	41
T31	0	13
T32	412	0
T33	215	0
T34	153	0
T35	216	0
T36	305	0
T37	0	112
T38	1497	0
T44	0	53
T45	0	163
T46	0	145
T49	449	0
T50	108	0

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	76028694	45087	0	0
SrcPulseCheck_M	1085690	44365	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	76028694	45087
T1	0	76
T2	0	336
T7	293996	221
T8	74578	86
T9	0	41
T31	0	13
T32	5892	0
T33	3071	0
T34	2183	0
T35	3095	0
T36	4356	0
T37	0	148
T38	21384	0
T44	0	53
T45	0	247
T46	0	217
T49	6423	0
T50	1559	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1085690	44365
T1	0	76
T2	0	336
T7	5808	221
T8	171	86
T9	0	41
T31	0	13
T32	412	0
T33	215	0
T34	153	0
T35	216	0
T36	305	0
T37	0	148
T38	1497	0
T44	0	53
T45	0	247
T46	0	217
T49	449	0
T50	108	0

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T10,T11,T12

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	36499908	44626	0	0
SrcPulseCheck_M	1096491	43241	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	36499908	44626
T1	0	76
T2	0	348
T7	132480	185
T8	32917	73
T9	0	41
T31	0	13
T32	2828	0
T33	1474	0
T34	1047	0
T35	1485	0
T36	2091	0
T37	0	160
T38	10265	0
T44	0	53
T45	0	171
T46	0	205
T49	3082	0
T50	748	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1096491	43241
T1	0	76
T2	0	348
T7	5772	185
T8	159	73
T9	0	41
T31	0	13
T32	412	0
T33	215	0
T34	153	0
T35	216	0
T36	305	0
T37	0	160
T38	1497	0
T44	0	53
T45	0	171
T46	0	205
T49	449	0
T50	108	0

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb