Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T4,T5
1	0	Covered	T7,T8,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	334644510	680692	0	0
DstReqKnown_A	478817736	451236734	0	0
SrcAckBusyChk_A	334644510	134649	0	0
SrcBusyKnown_A	334644510	304786010	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334644510	680692	0	0
T4	0	3990	0	0
T5	0	494	0	0
T6	0	104	0	0
T7	1499970	1995	0	0
T8	169220	404	0	0
T9	0	731	0	0
T32	14130	0	0	0
T33	15050	0	0	0
T34	20950	0	0	0
T35	15460	0	0	0
T36	9150	0	0	0
T37	0	810	0	0
T38	25660	0	0	0
T44	0	425	0	0
T45	0	1283	0	0
T46	0	2299	0	0
T49	8350	0	0	0
T50	14810	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478817736	451236734	0	0
T7	1745616	1595780	0	0
T8	425106	424002	0	0
T10	57060	55898	0	0
T11	19312	18502	0	0
T12	22628	21830	0	0
T32	37888	37370	0	0
T33	19350	18252	0	0
T34	13726	12390	0	0
T35	19436	18488	0	0
T36	27474	26736	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334644510	134649	0	0
T4	0	516	0	0
T5	0	59	0	0
T6	0	29	0	0
T7	1499970	390	0	0
T8	169220	120	0	0
T9	0	140	0	0
T32	14130	0	0	0
T33	15050	0	0	0
T34	20950	0	0	0
T35	15460	0	0	0
T36	9150	0	0	0
T37	0	260	0	0
T38	25660	0	0	0
T44	0	80	0	0
T45	0	300	0	0
T46	0	280	0	0
T49	8350	0	0	0
T50	14810	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	334644510	304786010	0	0
T7	1499970	1368770	0	0
T8	169220	168800	0	0
T10	15700	15280	0	0
T11	14730	14060	0	0
T12	10490	10120	0	0
T32	14130	13900	0	0
T33	15050	14150	0	0
T34	20950	18650	0	0
T35	15460	14620	0	0
T36	9150	8890	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Unreachable
1	0	Covered	T7,T8,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	33464451	36939	0	0
DstReqKnown_A	71222213	66528530	0	0
SrcAckBusyChk_A	33464451	10658	0	0
SrcBusyKnown_A	33464451	30478601	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	36939	0	0
T4	0	180	0	0
T5	0	19	0	0
T6	0	5	0	0
T7	149997	124	0	0
T8	16922	31	0	0
T9	0	49	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	64	0	0
T38	2566	0	0	0
T44	0	32	0	0
T45	0	97	0	0
T46	0	145	0	0
T49	835	0	0	0
T50	1481	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71222213	66528530	0	0
T7	259188	233998	0	0
T8	60073	59884	0	0
T10	7539	7335	0	0
T11	2945	2810	0	0
T12	3402	3253	0	0
T32	5656	5562	0	0
T33	2948	2772	0	0
T34	2095	1865	0	0
T35	2970	2808	0	0
T36	4182	4061	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	10658	0	0
T4	0	36	0	0
T5	0	4	0	0
T6	0	2	0	0
T7	149997	35	0	0
T8	16922	12	0	0
T9	0	14	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	26	0	0
T38	2566	0	0	0
T44	0	8	0	0
T45	0	30	0	0
T46	0	28	0	0
T49	835	0	0	0
T50	1481	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	30478601	0	0
T7	149997	136877	0	0
T8	16922	16880	0	0
T10	1570	1528	0	0
T11	1473	1406	0	0
T12	1049	1012	0	0
T32	1413	1390	0	0
T33	1505	1415	0	0
T34	2095	1865	0	0
T35	1546	1462	0	0
T36	915	889	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Unreachable
1	0	Covered	T7,T8,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	33464451	52764	0	0
DstReqKnown_A	34620872	33446618	0	0
SrcAckBusyChk_A	33464451	10658	0	0
SrcBusyKnown_A	33464451	30478601	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	52764	0	0
T4	0	274	0	0
T5	0	29	0	0
T6	0	7	0	0
T7	149997	180	0	0
T8	16922	40	0	0
T9	0	70	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	84	0	0
T38	2566	0	0	0
T44	0	43	0	0
T45	0	128	0	0
T46	0	229	0	0
T49	835	0	0	0
T50	1481	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34620872	33446618	0	0
T7	124765	117503	0	0
T8	29990	29942	0	0
T10	6245	6203	0	0
T11	1447	1405	0	0
T12	1641	1627	0	0
T32	3045	3031	0	0
T33	1455	1386	0	0
T34	1026	971	0	0
T35	1445	1404	0	0
T36	2072	2031	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	10658	0	0
T4	0	36	0	0
T5	0	4	0	0
T6	0	2	0	0
T7	149997	35	0	0
T8	16922	12	0	0
T9	0	14	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	26	0	0
T38	2566	0	0	0
T44	0	8	0	0
T45	0	30	0	0
T46	0	28	0	0
T49	835	0	0	0
T50	1481	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	30478601	0	0
T7	149997	136877	0	0
T8	16922	16880	0	0
T10	1570	1528	0	0
T11	1473	1406	0	0
T12	1049	1012	0	0
T32	1413	1390	0	0
T33	1505	1415	0	0
T34	2095	1865	0	0
T35	1546	1462	0	0
T36	915	889	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Unreachable
1	0	Covered	T7,T8,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	33464451	83932	0	0
DstReqKnown_A	17310071	16723039	0	0
SrcAckBusyChk_A	33464451	10658	0	0
SrcBusyKnown_A	33464451	30478601	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	83932	0	0
T4	0	477	0	0
T5	0	55	0	0
T6	0	11	0	0
T7	149997	288	0	0
T8	16922	57	0	0
T9	0	116	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	106	0	0
T38	2566	0	0	0
T44	0	69	0	0
T45	0	191	0	0
T46	0	399	0	0
T49	835	0	0	0
T50	1481	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17310071	16723039	0	0
T7	62379	58748	0	0
T8	14995	14971	0	0
T10	3122	3101	0	0
T11	723	702	0	0
T12	820	813	0	0
T32	1523	1516	0	0
T33	727	693	0	0
T34	512	485	0	0
T35	723	702	0	0
T36	1036	1015	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	10658	0	0
T4	0	36	0	0
T5	0	4	0	0
T6	0	2	0	0
T7	149997	35	0	0
T8	16922	12	0	0
T9	0	14	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	26	0	0
T38	2566	0	0	0
T44	0	8	0	0
T45	0	30	0	0
T46	0	28	0	0
T49	835	0	0	0
T50	1481	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	30478601	0	0
T7	149997	136877	0	0
T8	16922	16880	0	0
T10	1570	1528	0	0
T11	1473	1406	0	0
T12	1049	1012	0	0
T32	1413	1390	0	0
T33	1505	1415	0	0
T34	2095	1865	0	0
T35	1546	1462	0	0
T36	915	889	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Unreachable
1	0	Covered	T7,T8,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	33464451	36532	0	0
DstReqKnown_A	78547035	73581609	0	0
SrcAckBusyChk_A	33464451	10658	0	0
SrcBusyKnown_A	33464451	30478601	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	36532	0	0
T4	0	176	0	0
T5	0	18	0	0
T6	0	5	0	0
T7	149997	122	0	0
T8	16922	31	0	0
T9	0	45	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	64	0	0
T38	2566	0	0	0
T44	0	28	0	0
T45	0	96	0	0
T46	0	141	0	0
T49	835	0	0	0
T50	1481	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78547035	73581609	0	0
T7	293996	267756	0	0
T8	74578	74381	0	0
T10	7854	7642	0	0
T11	3068	2928	0	0
T12	3732	3577	0	0
T32	5892	5795	0	0
T33	3071	2888	0	0
T34	2183	1942	0	0
T35	3095	2926	0	0
T36	4356	4230	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	10658	0	0
T4	0	36	0	0
T5	0	4	0	0
T6	0	2	0	0
T7	149997	35	0	0
T8	16922	12	0	0
T9	0	14	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	26	0	0
T38	2566	0	0	0
T44	0	8	0	0
T45	0	30	0	0
T46	0	28	0	0
T49	835	0	0	0
T50	1481	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	30478601	0	0
T7	149997	136877	0	0
T8	16922	16880	0	0
T10	1570	1528	0	0
T11	1473	1406	0	0
T12	1049	1012	0	0
T32	1413	1390	0	0
T33	1505	1415	0	0
T34	2095	1865	0	0
T35	1546	1462	0	0
T36	915	889	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Unreachable
1	0	Covered	T7,T8,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	33464451	50462	0	0
DstReqKnown_A	37708677	35338571	0	0
SrcAckBusyChk_A	33464451	10141	0	0
SrcBusyKnown_A	33464451	30478601	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	50462	0	0
T4	0	153	0	0
T5	0	30	0	0
T6	0	6	0	0
T7	149997	183	0	0
T8	16922	42	0	0
T9	0	84	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	83	0	0
T38	2566	0	0	0
T44	0	43	0	0
T45	0	127	0	0
T46	0	227	0	0
T49	835	0	0	0
T50	1481	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37708677	35338571	0	0
T7	132480	119885	0	0
T8	32917	32823	0	0
T10	3770	3668	0	0
T11	1473	1406	0	0
T12	1719	1645	0	0
T32	2828	2781	0	0
T33	1474	1387	0	0
T34	1047	932	0	0
T35	1485	1404	0	0
T36	2091	2031	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	10141	0	0
T4	0	18	0	0
T5	0	3	0	0
T6	0	1	0	0
T7	149997	35	0	0
T8	16922	12	0	0
T9	0	14	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	26	0	0
T38	2566	0	0	0
T44	0	8	0	0
T45	0	30	0	0
T46	0	28	0	0
T49	835	0	0	0
T50	1481	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	30478601	0	0
T7	149997	136877	0	0
T8	16922	16880	0	0
T10	1570	1528	0	0
T11	1473	1406	0	0
T12	1049	1012	0	0
T32	1413	1390	0	0
T33	1505	1415	0	0
T34	2095	1865	0	0
T35	1546	1462	0	0
T36	915	889	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T4,T5
1	0	Covered	T7,T8,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Unreachable
1	0	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	33464451	58783	0	0
DstReqKnown_A	71222213	66528530	0	0
SrcAckBusyChk_A	33464451	16509	0	0
SrcBusyKnown_A	33464451	30478601	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	58783	0	0
T4	0	347	0	0
T5	0	44	0	0
T6	0	11	0	0
T7	149997	154	0	0
T8	16922	31	0	0
T9	0	49	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	64	0	0
T38	2566	0	0	0
T44	0	31	0	0
T45	0	99	0	0
T46	0	145	0	0
T49	835	0	0	0
T50	1481	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	71222213	66528530	0	0
T7	259188	233998	0	0
T8	60073	59884	0	0
T10	7539	7335	0	0
T11	2945	2810	0	0
T12	3402	3253	0	0
T32	5656	5562	0	0
T33	2948	2772	0	0
T34	2095	1865	0	0
T35	2970	2808	0	0
T36	4182	4061	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	16509	0	0
T4	0	72	0	0
T5	0	8	0	0
T6	0	4	0	0
T7	149997	43	0	0
T8	16922	12	0	0
T9	0	14	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	26	0	0
T38	2566	0	0	0
T44	0	8	0	0
T45	0	30	0	0
T46	0	28	0	0
T49	835	0	0	0
T50	1481	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	30478601	0	0
T7	149997	136877	0	0
T8	16922	16880	0	0
T10	1570	1528	0	0
T11	1473	1406	0	0
T12	1049	1012	0	0
T32	1413	1390	0	0
T33	1505	1415	0	0
T34	2095	1865	0	0
T35	1546	1462	0	0
T36	915	889	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T4,T5
1	0	Covered	T7,T8,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Unreachable
1	0	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	33464451	84706	0	0
DstReqKnown_A	34620872	33446618	0	0
SrcAckBusyChk_A	33464451	16502	0	0
SrcBusyKnown_A	33464451	30478601	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	84706	0	0
T4	0	545	0	0
T5	0	70	0	0
T6	0	14	0	0
T7	149997	220	0	0
T8	16922	42	0	0
T9	0	70	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	86	0	0
T38	2566	0	0	0
T44	0	42	0	0
T45	0	127	0	0
T46	0	229	0	0
T49	835	0	0	0
T50	1481	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34620872	33446618	0	0
T7	124765	117503	0	0
T8	29990	29942	0	0
T10	6245	6203	0	0
T11	1447	1405	0	0
T12	1641	1627	0	0
T32	3045	3031	0	0
T33	1455	1386	0	0
T34	1026	971	0	0
T35	1445	1404	0	0
T36	2072	2031	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	16502	0	0
T4	0	72	0	0
T5	0	8	0	0
T6	0	4	0	0
T7	149997	43	0	0
T8	16922	12	0	0
T9	0	14	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	26	0	0
T38	2566	0	0	0
T44	0	8	0	0
T45	0	30	0	0
T46	0	28	0	0
T49	835	0	0	0
T50	1481	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	30478601	0	0
T7	149997	136877	0	0
T8	16922	16880	0	0
T10	1570	1528	0	0
T11	1473	1406	0	0
T12	1049	1012	0	0
T32	1413	1390	0	0
T33	1505	1415	0	0
T34	2095	1865	0	0
T35	1546	1462	0	0
T36	915	889	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T4,T5
1	0	Covered	T7,T8,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Unreachable
1	0	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	33464451	135550	0	0
DstReqKnown_A	17310071	16723039	0	0
SrcAckBusyChk_A	33464451	16473	0	0
SrcBusyKnown_A	33464451	30478601	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	135550	0	0
T4	0	959	0	0
T5	0	118	0	0
T6	0	20	0	0
T7	149997	355	0	0
T8	16922	56	0	0
T9	0	115	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	115	0	0
T38	2566	0	0	0
T44	0	66	0	0
T45	0	194	0	0
T46	0	410	0	0
T49	835	0	0	0
T50	1481	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17310071	16723039	0	0
T7	62379	58748	0	0
T8	14995	14971	0	0
T10	3122	3101	0	0
T11	723	702	0	0
T12	820	813	0	0
T32	1523	1516	0	0
T33	727	693	0	0
T34	512	485	0	0
T35	723	702	0	0
T36	1036	1015	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	16473	0	0
T4	0	72	0	0
T5	0	8	0	0
T6	0	4	0	0
T7	149997	43	0	0
T8	16922	12	0	0
T9	0	14	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	26	0	0
T38	2566	0	0	0
T44	0	8	0	0
T45	0	30	0	0
T46	0	28	0	0
T49	835	0	0	0
T50	1481	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	30478601	0	0
T7	149997	136877	0	0
T8	16922	16880	0	0
T10	1570	1528	0	0
T11	1473	1406	0	0
T12	1049	1012	0	0
T32	1413	1390	0	0
T33	1505	1415	0	0
T34	2095	1865	0	0
T35	1546	1462	0	0
T36	915	889	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T4,T5
1	0	Covered	T7,T8,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Unreachable
1	0	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	33464451	57628	0	0
DstReqKnown_A	78547035	73581609	0	0
SrcAckBusyChk_A	33464451	16323	0	0
SrcBusyKnown_A	33464451	30478601	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	57628	0	0
T4	0	339	0	0
T5	0	41	0	0
T6	0	10	0	0
T7	149997	149	0	0
T8	16922	31	0	0
T9	0	49	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	64	0	0
T38	2566	0	0	0
T44	0	29	0	0
T45	0	95	0	0
T46	0	143	0	0
T49	835	0	0	0
T50	1481	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78547035	73581609	0	0
T7	293996	267756	0	0
T8	74578	74381	0	0
T10	7854	7642	0	0
T11	3068	2928	0	0
T12	3732	3577	0	0
T32	5892	5795	0	0
T33	3071	2888	0	0
T34	2183	1942	0	0
T35	3095	2926	0	0
T36	4356	4230	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	16323	0	0
T4	0	72	0	0
T5	0	8	0	0
T6	0	4	0	0
T7	149997	43	0	0
T8	16922	12	0	0
T9	0	14	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	26	0	0
T38	2566	0	0	0
T44	0	8	0	0
T45	0	30	0	0
T46	0	28	0	0
T49	835	0	0	0
T50	1481	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	30478601	0	0
T7	149997	136877	0	0
T8	16922	16880	0	0
T10	1570	1528	0	0
T11	1473	1406	0	0
T12	1049	1012	0	0
T32	1413	1390	0	0
T33	1505	1415	0	0
T34	2095	1865	0	0
T35	1546	1462	0	0
T36	915	889	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Covered	T7,T4,T5
1	0	Covered	T7,T8,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T12
0	1	Unreachable
1	0	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T10,T11,T12
0	1	-	Covered	T7,T8,T9
0	0	1	Covered	T7,T8,T9
0	0	0	Covered	T10,T11,T12

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	33464451	83396	0	0
DstReqKnown_A	37708677	35338571	0	0
SrcAckBusyChk_A	33464451	16069	0	0
SrcBusyKnown_A	33464451	30478601	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	83396	0	0
T4	0	540	0	0
T5	0	70	0	0
T6	0	15	0	0
T7	149997	220	0	0
T8	16922	43	0	0
T9	0	84	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	80	0	0
T38	2566	0	0	0
T44	0	42	0	0
T45	0	129	0	0
T46	0	231	0	0
T49	835	0	0	0
T50	1481	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37708677	35338571	0	0
T7	132480	119885	0	0
T8	32917	32823	0	0
T10	3770	3668	0	0
T11	1473	1406	0	0
T12	1719	1645	0	0
T32	2828	2781	0	0
T33	1474	1387	0	0
T34	1047	932	0	0
T35	1485	1404	0	0
T36	2091	2031	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	16069	0	0
T4	0	66	0	0
T5	0	8	0	0
T6	0	4	0	0
T7	149997	43	0	0
T8	16922	12	0	0
T9	0	14	0	0
T32	1413	0	0	0
T33	1505	0	0	0
T34	2095	0	0	0
T35	1546	0	0	0
T36	915	0	0	0
T37	0	26	0	0
T38	2566	0	0	0
T44	0	8	0	0
T45	0	30	0	0
T46	0	28	0	0
T49	835	0	0	0
T50	1481	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33464451	30478601	0	0
T7	149997	136877	0	0
T8	16922	16880	0	0
T10	1570	1528	0	0
T11	1473	1406	0	0
T12	1049	1012	0	0
T32	1413	1390	0	0
T33	1505	1415	0	0
T34	2095	1865	0	0
T35	1546	1462	0	0
T36	915	889	0	0