Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42042	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

40286

1

T1

276

T2

200

T6

27

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	45872	1			T1	584		T2	98		T6	51
values[0x0]	17989	1			T1	229		T2	53		T6	22
values[0x1]	18467	1			T1	201		T2	49		T6	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29630	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

52698

1

T1

536

T2

200

T6

47

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	246	1			T8	2		T16	1		T26	7
valid_sources[0x01]	506	1			T1	7		T5	2		T17	2
valid_sources[0x02]	373	1			T2	28		T6	1		T4	2
valid_sources[0x03]	363	1			T1	1		T6	1		T8	1
valid_sources[0x04]	214	1			T1	2		T5	4		T8	2
valid_sources[0x05]	390	1			T8	2		T16	28		T7	4
valid_sources[0x06]	312	1			T1	3		T16	1		T7	13
valid_sources[0x07]	232	1			T1	4		T5	10		T8	1
valid_sources[0x08]	231	1			T5	5		T8	2		T28	6
valid_sources[0x09]	344	1			T1	9		T4	6		T5	11
valid_sources[0x0a]	424	1			T1	2		T5	1		T16	2
valid_sources[0x0b]	279	1			T1	7		T8	3		T16	4
valid_sources[0x0c]	240	1			T1	1		T8	1		T17	1
valid_sources[0x0d]	275	1			T1	8		T4	6		T8	1
valid_sources[0x0e]	332	1			T1	8		T6	1		T5	21
valid_sources[0x0f]	290	1			T1	1		T5	4		T8	1
valid_sources[0x10]	502	1			T1	4		T4	2		T8	1
valid_sources[0x11]	702	1			T1	5		T6	1		T5	1
valid_sources[0x12]	249	1			T1	5		T6	1		T5	6
valid_sources[0x13]	355	1			T1	4		T5	9		T8	5
valid_sources[0x14]	295	1			T9	11		T4	1		T8	1
valid_sources[0x15]	323	1			T1	1		T6	1		T5	3
valid_sources[0x16]	279	1			T1	4		T4	1		T8	1
valid_sources[0x17]	235	1			T1	13		T4	4		T5	8
valid_sources[0x18]	399	1			T1	1		T6	1		T4	1
valid_sources[0x19]	291	1			T1	5		T4	5		T8	1
valid_sources[0x1a]	278	1			T1	2		T6	3		T8	1
valid_sources[0x1b]	225	1			T6	2		T8	1		T16	2
valid_sources[0x1c]	374	1			T1	16		T2	8		T5	2
valid_sources[0x1d]	341	1			T1	2		T8	1		T16	3
valid_sources[0x1e]	284	1			T1	7		T6	1		T5	3
valid_sources[0x1f]	286	1			T1	8		T5	6		T8	3
valid_sources[0x20]	299	1			T5	1		T28	10		T24	3
valid_sources[0x21]	309	1			T1	9		T16	1		T28	2
valid_sources[0x22]	269	1			T1	2		T28	2		T24	2
valid_sources[0x23]	589	1			T1	3		T4	6		T16	2
valid_sources[0x24]	349	1			T1	4		T6	2		T16	1
valid_sources[0x25]	452	1			T1	4		T16	21		T17	5
valid_sources[0x26]	342	1			T4	1		T8	1		T16	14
valid_sources[0x27]	319	1			T1	1		T8	2		T16	8
valid_sources[0x28]	517	1			T1	10		T5	11		T16	11
valid_sources[0x29]	304	1			T1	8		T5	2		T16	1
valid_sources[0x2a]	320	1			T6	3		T5	5		T8	4
valid_sources[0x2b]	429	1			T1	9		T5	6		T8	1
valid_sources[0x2c]	297	1			T1	5		T4	2		T8	3
valid_sources[0x2d]	290	1			T1	6		T8	2		T7	2
valid_sources[0x2e]	376	1			T5	5		T16	8		T28	2
valid_sources[0x2f]	529	1			T1	2		T5	13		T8	2
valid_sources[0x30]	241	1			T6	1		T5	3		T16	3
valid_sources[0x31]	354	1			T1	9		T9	12		T4	1
valid_sources[0x32]	248	1			T1	1		T4	1		T5	6
valid_sources[0x33]	416	1			T8	1		T16	9		T17	2
valid_sources[0x34]	375	1			T1	6		T16	18		T28	5
valid_sources[0x35]	285	1			T8	2		T28	3		T18	1
valid_sources[0x36]	248	1			T1	8		T5	4		T8	1
valid_sources[0x37]	353	1			T1	3		T4	1		T8	2
valid_sources[0x38]	363	1			T6	2		T5	2		T8	3
valid_sources[0x39]	398	1			T1	11		T4	2		T5	4
valid_sources[0x3a]	399	1			T1	3		T4	1		T8	1
valid_sources[0x3b]	204	1			T16	7		T7	7		T17	5
valid_sources[0x3c]	290	1			T1	7		T4	2		T5	5
valid_sources[0x3d]	299	1			T5	8		T16	20		T7	4
valid_sources[0x3e]	235	1			T6	1		T8	2		T17	2
valid_sources[0x3f]	305	1			T1	9		T8	3		T17	1
valid_sources[0x40]	309	1			T1	3		T5	2		T8	4
valid_sources[0x41]	294	1			T6	1		T5	3		T8	1
valid_sources[0x42]	285	1			T1	9		T4	6		T8	2
valid_sources[0x43]	336	1			T1	2		T6	2		T4	5
valid_sources[0x44]	344	1			T1	5		T5	6		T8	1
valid_sources[0x45]	462	1			T1	7		T28	3		T29	11
valid_sources[0x46]	251	1			T1	9		T8	4		T16	1
valid_sources[0x47]	474	1			T1	18		T5	4		T8	2
valid_sources[0x48]	264	1			T8	2		T28	2		T24	3
valid_sources[0x49]	391	1			T1	4		T5	6		T8	5
valid_sources[0x4a]	284	1			T1	10		T6	1		T5	7
valid_sources[0x4b]	279	1			T1	6		T8	1		T16	6
valid_sources[0x4c]	297	1			T5	2		T8	2		T28	1
valid_sources[0x4d]	322	1			T1	11		T4	1		T8	2
valid_sources[0x4e]	278	1			T1	4		T6	1		T4	5
valid_sources[0x4f]	371	1			T1	3		T2	2		T6	2
valid_sources[0x50]	291	1			T1	1		T6	1		T4	2
valid_sources[0x51]	299	1			T1	9		T2	2		T4	1
valid_sources[0x52]	290	1			T1	4		T5	4		T16	20
valid_sources[0x53]	283	1			T4	1		T8	1		T17	1
valid_sources[0x54]	327	1			T1	12		T4	2		T5	1
valid_sources[0x55]	297	1			T1	2		T6	1		T5	1
valid_sources[0x56]	265	1			T1	5		T4	2		T5	5
valid_sources[0x57]	439	1			T1	1		T8	1		T28	3
valid_sources[0x58]	293	1			T1	12		T4	1		T8	1
valid_sources[0x59]	475	1			T1	5		T8	2		T28	4
valid_sources[0x5a]	307	1			T1	1		T5	4		T8	1
valid_sources[0x5b]	236	1			T1	9		T17	2		T28	1
valid_sources[0x5c]	231	1			T6	2		T8	1		T28	4
valid_sources[0x5d]	233	1			T1	2		T6	1		T8	3
valid_sources[0x5e]	362	1			T1	1		T5	2		T8	2
valid_sources[0x5f]	254	1			T1	1		T4	2		T28	3
valid_sources[0x60]	302	1			T1	3		T4	1		T5	5
valid_sources[0x61]	291	1			T4	3		T16	2		T7	3
valid_sources[0x62]	298	1			T1	6		T4	1		T8	2
valid_sources[0x63]	314	1			T1	4		T4	1		T5	16
valid_sources[0x64]	286	1			T1	4		T4	3		T8	3
valid_sources[0x65]	394	1			T1	2		T6	1		T16	21
valid_sources[0x66]	223	1			T1	4		T6	1		T8	2
valid_sources[0x67]	293	1			T1	4		T2	3		T6	1
valid_sources[0x68]	392	1			T5	3		T16	1		T7	8
valid_sources[0x69]	321	1			T1	1		T6	1		T5	1
valid_sources[0x6a]	321	1			T1	3		T2	6		T8	4
valid_sources[0x6b]	238	1			T1	1		T6	1		T5	6
valid_sources[0x6c]	237	1			T1	4		T5	2		T8	4
valid_sources[0x6d]	270	1			T1	11		T5	7		T8	3
valid_sources[0x6e]	330	1			T6	1		T4	1		T5	6
valid_sources[0x6f]	286	1			T6	1		T8	2		T16	6
valid_sources[0x70]	227	1			T6	1		T5	6		T8	2
valid_sources[0x71]	350	1			T1	2		T4	3		T8	5
valid_sources[0x72]	272	1			T4	2		T5	3		T8	1
valid_sources[0x73]	283	1			T1	4		T5	1		T28	6
valid_sources[0x74]	281	1			T1	7		T6	1		T5	3
valid_sources[0x75]	330	1			T1	12		T8	1		T16	1
valid_sources[0x76]	309	1			T1	3		T4	1		T5	1
valid_sources[0x77]	350	1			T1	4		T9	5		T5	14
valid_sources[0x78]	317	1			T6	1		T5	21		T8	2
valid_sources[0x79]	272	1			T8	3		T16	6		T7	6
valid_sources[0x7a]	302	1			T4	2		T16	1		T17	3
valid_sources[0x7b]	289	1			T2	27		T6	1		T4	1
valid_sources[0x7c]	296	1			T1	2		T8	1		T16	4
valid_sources[0x7d]	308	1			T1	5		T4	2		T18	5
valid_sources[0x7e]	525	1			T1	4		T4	1		T8	3
valid_sources[0x7f]	267	1			T1	5		T4	1		T8	7
valid_sources[0x80]	267	1			T1	2		T6	1		T4	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

18469

1

T1

73

T2

98

T6

9

values[0x0]

all_enables

biggest_size

12813

1

T1

137

T2

53

T6

12

values[0x1]

all_enables

biggest_size

9004

1

T1

66

T2

49

T6

6