Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_trans_cg_wrap::trans_cg

Group : clkmgr_env_pkg::clkmgr_trans_cg_wrap::trans_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
83.33	83.33	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
TransAes	83.33	1	100	1	64	64
TransHmac	83.33	1	100	1	64	64
TransKmac	83.33	1	100	1	64	64
TransOtbn	83.33	1	100	1	64	64

---

Group Instance : TransAes

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance TransAes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	3	7	70.00

Variables for Group Instance TransAes

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransAes

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	3	7	70.00	100	1	1	0

---

Group Instance : TransHmac

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance TransHmac

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	3	7	70.00

Variables for Group Instance TransHmac

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransHmac

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	3	7	70.00	100	1	1	0

---

Group Instance : TransKmac

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance TransKmac

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	3	7	70.00

Variables for Group Instance TransKmac

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransKmac

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	3	7	70.00	100	1	1	0

---

Group Instance : TransOtbn

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance TransOtbn

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	10	3	7	70.00

Variables for Group Instance TransOtbn

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_hint_cp	2	0	2	100.00	100	1	1	2
idle_cp	2	0	2	100.00	100	1	1	2
ip_clk_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance TransOtbn

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
trans_cross	10	3	7	70.00	100	1	1	0

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

354158

1

T1

2254

T2

2802

T3

2

auto[1]

2028535

1

T1

7308

T2

1613

T3

5622

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

98570

1

T1

13

T2

58

T3

959

auto[1]

2284123

1

T1

9549

T2

4357

T3

4665

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2346

1

T1

42

T2

2

T3

2

auto[1]

2380347

1

T1

9520

T2

4413

T3

5622

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2328708

1

T1

9562

T2

4357

T3

4665

auto[1]

53985

1

T2

58

T3

959

T4

919

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	3	7	70.00	3
Automatically Generated Cross Bins	10	3	7	70.00	3
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Element holes

csr_hint_cp	ip_clk_en_cp	scanmode_cp	idle_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	*	[auto[1]]	[auto[1]]	--	--	2

Uncovered bins

csr_hint_cp	ip_clk_en_cp	scanmode_cp	idle_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

1880

1

T1

40

T5

20

T16

34

auto[0]

auto[1]

auto[0]

auto[0]

6136

1

T7

159

T23

218

T10

2355

auto[0]

auto[1]

auto[0]

auto[1]

336422

1

T1

2212

T2

2800

T6

3734

auto[0]

auto[1]

auto[1]

auto[0]

9254

1

T10

1603

T77

1653

T78

740

auto[1]

auto[1]

auto[0]

auto[0]

38205

1

T1

11

T6

54

T9

9

auto[1]

auto[1]

auto[0]

auto[1]

1945821

1

T1

7297

T2

1557

T3

4665

auto[1]

auto[1]

auto[1]

auto[0]

44509

1

T2

56

T3

957

T4

917

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

358629

1

T1

1476

T2

2808

T3

2

auto[1]

2024064

1

T1

8086

T2

1607

T3

5622

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

98570

1

T1

13

T2

58

T3

959

auto[1]

2284123

1

T1

9549

T2

4357

T3

4665

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2346

1

T1

42

T2

2

T3

2

auto[1]

2380347

1

T1

9520

T2

4413

T3

5622

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2328708

1

T1

9562

T2

4357

T3

4665

auto[1]

53985

1

T2

58

T3

959

T4

919

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	3	7	70.00	3
Automatically Generated Cross Bins	10	3	7	70.00	3
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Element holes

csr_hint_cp	ip_clk_en_cp	scanmode_cp	idle_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	*	[auto[1]]	[auto[1]]	--	--	2

Uncovered bins

csr_hint_cp	ip_clk_en_cp	scanmode_cp	idle_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

1880

1

T1

40

T5

20

T16

34

auto[0]

auto[1]

auto[0]

auto[0]

2757

1

T23

218

T45

207

T79

329

auto[0]

auto[1]

auto[0]

auto[1]

345422

1

T1

1434

T2

2806

T9

1305

auto[0]

auto[1]

auto[1]

auto[0]

8104

1

T4

378

T11

1869

T77

1653

auto[1]

auto[1]

auto[0]

auto[0]

41584

1

T1

11

T6

54

T9

9

auto[1]

auto[1]

auto[0]

auto[1]

1936821

1

T1

8075

T2

1551

T3

4665

auto[1]

auto[1]

auto[1]

auto[0]

45659

1

T2

56

T3

957

T4

539

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

345972

1

T1

1869

T2

2

T3

2

auto[1]

2036721

1

T1

7693

T2

4413

T3

5622

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

98570

1

T1

13

T2

58

T3

959

auto[1]

2284123

1

T1

9549

T2

4357

T3

4665

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2346

1

T1

42

T2

2

T3

2

auto[1]

2380347

1

T1

9520

T2

4413

T3

5622

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2328708

1

T1

9562

T2

4357

T3

4665

auto[1]

53985

1

T2

58

T3

959

T4

919

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	3	7	70.00	3
Automatically Generated Cross Bins	10	3	7	70.00	3
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Element holes

csr_hint_cp	ip_clk_en_cp	scanmode_cp	idle_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	*	[auto[1]]	[auto[1]]	--	--	2

Uncovered bins

csr_hint_cp	ip_clk_en_cp	scanmode_cp	idle_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

1880

1

T1

40

T5

20

T16

34

auto[0]

auto[1]

auto[0]

auto[0]

3893

1

T18

179

T23

218

T10

2355

auto[0]

auto[1]

auto[0]

auto[1]

333039

1

T1

1827

T6

3734

T5

1666

auto[0]

auto[1]

auto[1]

auto[0]

6694

1

T4

378

T77

1653

T80

1298

auto[1]

auto[1]

auto[0]

auto[0]

40448

1

T1

11

T6

54

T9

9

auto[1]

auto[1]

auto[0]

auto[1]

1949204

1

T1

7682

T2

4357

T3

4665

auto[1]

auto[1]

auto[1]

auto[0]

47069

1

T2

56

T3

957

T4

539

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded

Summary for Variable csr_hint_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_hint_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

320447

1

T1

2208

T2

2832

T3

2

auto[1]

2062246

1

T1

7354

T2

1583

T3

5622

---

Summary for Variable idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

98570

1

T1

13

T2

58

T3

959

auto[1]

2284123

1

T1

9549

T2

4357

T3

4665

---

Summary for Variable ip_clk_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for ip_clk_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2346

1

T1

42

T2

2

T3

2

auto[1]

2380347

1

T1

9520

T2

4413

T3

5622

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2328708

1

T1

9562

T2

4357

T3

4665

auto[1]

53985

1

T2

58

T3

959

T4

919

---

Summary for Cross trans_cross

Samples crossed: csr_hint_cp ip_clk_en_cp scanmode_cp idle_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	10	3	7	70.00	3
Automatically Generated Cross Bins	10	3	7	70.00	3
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for trans_cross

Element holes

csr_hint_cp	ip_clk_en_cp	scanmode_cp	idle_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	*	[auto[1]]	[auto[1]]	--	--	2

Uncovered bins

csr_hint_cp	ip_clk_en_cp	scanmode_cp	idle_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

csr_hint_cp

ip_clk_en_cp

scanmode_cp

idle_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[1]

1880

1

T1

40

T5

20

T16

34

auto[0]

auto[1]

auto[0]

auto[0]

6704

1

T23

218

T10

2355

T81

579

auto[0]

auto[1]

auto[0]

auto[1]

304223

1

T1

2166

T2

2830

T6

5370

auto[0]

auto[1]

auto[1]

auto[0]

7174

1

T77

1653

T78

362

T80

1298

auto[1]

auto[1]

auto[0]

auto[0]

37637

1

T1

11

T6

54

T9

9

auto[1]

auto[1]

auto[0]

auto[1]

1978020

1

T1

7343

T2

1527

T3

4665

auto[1]

auto[1]

auto[1]

auto[0]

46589

1

T2

56

T3

957

T4

917

User Defined Cross Bins for trans_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore_idle_off	0	Excluded
ignore_enable_off	0	Excluded