Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1513508489	521697	0	0
SrcPulseCheck_M	1327201392	519161	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1513508489	521697
T1	0	371
T2	0	408
T4	0	40
T5	29584	20
T6	2901491	3118
T7	822124	1448
T8	10019	0
T9	4498	0
T19	0	435
T21	0	830
T23	0	542
T26	6837	0
T27	5477	0
T28	4193	0
T29	11578	0
T30	3602	0
T31	14531	0
T32	557699	626
T33	0	80
T36	6293	0
T48	14744	0
T68	5021	1
T71	3224	2
T72	9461	1
T73	0	1
T74	0	1
T76	0	2
T77	5509	0
T82	3083	0
T83	8388	0
T84	21051	0
T119	0	514
T120	0	2
T121	0	2
T122	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1327201392	519161
T1	0	371
T2	0	408
T4	0	40
T5	32486	20
T6	1720579	3118
T7	6764	1448
T8	7942	0
T9	5552	0
T19	0	435
T21	0	830
T23	0	542
T26	5520	0
T27	5518	0
T28	5287	0
T29	9092	0
T30	4372	0
T31	4713	0
T32	9928	629
T33	0	80
T36	640	0
T48	1544	0
T68	9190	1
T71	5858	2
T72	3808	1
T73	0	1
T74	0	1
T76	0	2
T77	572	0
T82	320	0
T83	856	0
T84	2200	0
T119	0	514
T120	0	2
T121	0	2
T122	0	2

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T6,T7,T32

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T6,T7,T32
1	1	Covered	T5,T6,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	90532656	13007	0	0
SrcPulseCheck_M	40346326	13007	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	90532656	13007
T1	0	20
T2	0	32
T4	0	8
T5	19849	2
T6	564137	114
T7	0	56
T8	7511	0
T9	2115	0
T19	0	16
T21	0	30
T23	0	26
T26	5177	0
T27	3704	0
T28	2105	0
T29	8459	0
T30	1913	0
T31	3638	0
T32	0	31

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	40346326	13007
T1	0	20
T2	0	32
T4	0	8
T5	11796	2
T6	713661	114
T7	0	56
T8	1955	0
T9	2202	0
T19	0	16
T21	0	30
T23	0	26
T26	1401	0
T27	1853	0
T28	2127	0
T29	2202	0
T30	1714	0
T31	947	0
T32	0	31

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	90532656	19340	0	0
SrcPulseCheck_M	40346326	19351	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	90532656	19340
T1	0	20
T2	0	32
T4	0	16
T5	19849	9
T6	564137	114
T7	0	56
T8	7511	0
T9	2115	0
T19	0	16
T21	0	30
T23	0	26
T26	5177	0
T27	3704	0
T28	2105	0
T29	8459	0
T30	1913	0
T31	3638	0
T32	0	44

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	40346326	19351
T1	0	20
T2	0	32
T4	0	16
T5	11796	9
T6	713661	114
T7	0	56
T8	1955	0
T9	2202	0
T19	0	16
T21	0	30
T23	0	26
T26	1401	0
T27	1853	0
T28	2127	0
T29	2202	0
T30	1714	0
T31	947	0
T32	0	44

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	40346326	19329	0	0
SrcPulseCheck_M	90532656	19347	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	40346326	19329
T1	0	20
T2	0	32
T4	0	16
T5	11796	9
T6	713661	114
T7	0	56
T8	1955	0
T9	2202	0
T19	0	16
T21	0	30
T23	0	26
T26	1401	0
T27	1853	0
T28	2127	0
T29	2202	0
T30	1714	0
T31	947	0
T32	0	44

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	90532656	19347
T1	0	20
T2	0	32
T4	0	16
T5	19849	9
T6	564137	114
T7	0	56
T8	7511	0
T9	2115	0
T19	0	16
T21	0	30
T23	0	26
T26	5177	0
T27	3704	0
T28	2105	0
T29	8459	0
T30	1913	0
T31	3638	0
T32	0	44

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T6,T7,T32

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T6,T7,T32
1	1	Covered	T5,T6,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	44405581	13007	0	0
SrcPulseCheck_M	40346326	13007	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	44405581	13007
T1	0	20
T2	0	32
T4	0	8
T5	8894	2
T6	282297	114
T7	0	56
T8	4032	0
T9	1148	0
T19	0	16
T21	0	30
T23	0	26
T26	2718	0
T27	1812	0
T28	1033	0
T29	4688	0
T30	944	0
T31	1759	0
T32	0	31

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	40346326	13007
T1	0	20
T2	0	32
T4	0	8
T5	11796	2
T6	713661	114
T7	0	56
T8	1955	0
T9	2202	0
T19	0	16
T21	0	30
T23	0	26
T26	1401	0
T27	1853	0
T28	2127	0
T29	2202	0
T30	1714	0
T31	947	0
T32	0	31

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	44405581	19360	0	0
SrcPulseCheck_M	40346326	19381	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	44405581	19360
T1	0	20
T2	0	32
T4	0	16
T5	8894	9
T6	282297	114
T7	0	56
T8	4032	0
T9	1148	0
T19	0	16
T21	0	30
T23	0	26
T26	2718	0
T27	1812	0
T28	1033	0
T29	4688	0
T30	944	0
T31	1759	0
T32	0	44

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	40346326	19381
T1	0	20
T2	0	32
T4	0	16
T5	11796	9
T6	713661	114
T7	0	56
T8	1955	0
T9	2202	0
T19	0	16
T21	0	30
T23	0	26
T26	1401	0
T27	1853	0
T28	2127	0
T29	2202	0
T30	1714	0
T31	947	0
T32	0	44

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	40346326	19351	0	0
SrcPulseCheck_M	44405581	19361	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	40346326	19351
T1	0	20
T2	0	32
T4	0	16
T5	11796	9
T6	713661	114
T7	0	56
T8	1955	0
T9	2202	0
T19	0	16
T21	0	30
T23	0	26
T26	1401	0
T27	1853	0
T28	2127	0
T29	2202	0
T30	1714	0
T31	947	0
T32	0	44

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	44405581	19361
T1	0	20
T2	0	32
T4	0	16
T5	8894	9
T6	282297	114
T7	0	56
T8	4032	0
T9	1148	0
T19	0	16
T21	0	30
T23	0	26
T26	2718	0
T27	1812	0
T28	1033	0
T29	4688	0
T30	944	0
T31	1759	0
T32	0	44

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T6,T7,T32

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T6,T7,T32
1	1	Covered	T5,T6,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	22202332	13007	0	0
SrcPulseCheck_M	40346326	13007	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	22202332	13007
T1	0	20
T2	0	32
T4	0	8
T5	4446	2
T6	141141	114
T7	0	56
T8	2015	0
T9	573	0
T19	0	16
T21	0	30
T23	0	26
T26	1357	0
T27	906	0
T28	517	0
T29	2342	0
T30	472	0
T31	879	0
T32	0	31

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	40346326	13007
T1	0	20
T2	0	32
T4	0	8
T5	11796	2
T6	713661	114
T7	0	56
T8	1955	0
T9	2202	0
T19	0	16
T21	0	30
T23	0	26
T26	1401	0
T27	1853	0
T28	2127	0
T29	2202	0
T30	1714	0
T31	947	0
T32	0	31

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	22202332	19526	0	0
SrcPulseCheck_M	40346326	19569	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	22202332	19526
T1	0	20
T2	0	32
T4	0	16
T5	4446	9
T6	141141	114
T7	0	56
T8	2015	0
T9	573	0
T19	0	16
T21	0	30
T23	0	26
T26	1357	0
T27	906	0
T28	517	0
T29	2342	0
T30	472	0
T31	879	0
T32	0	44

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	40346326	19569
T1	0	20
T2	0	32
T4	0	16
T5	11796	9
T6	713661	114
T7	0	56
T8	1955	0
T9	2202	0
T19	0	16
T21	0	30
T23	0	26
T26	1401	0
T27	1853	0
T28	2127	0
T29	2202	0
T30	1714	0
T31	947	0
T32	0	44

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	40346326	19523	0	0
SrcPulseCheck_M	22202332	19533	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	40346326	19523
T1	0	20
T2	0	32
T4	0	16
T5	11796	9
T6	713661	114
T7	0	56
T8	1955	0
T9	2202	0
T19	0	16
T21	0	30
T23	0	26
T26	1401	0
T27	1853	0
T28	2127	0
T29	2202	0
T30	1714	0
T31	947	0
T32	0	44

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	22202332	19533
T1	0	20
T2	0	32
T4	0	16
T5	4446	9
T6	141141	114
T7	0	56
T8	2015	0
T9	573	0
T19	0	16
T21	0	30
T23	0	26
T26	1357	0
T27	906	0
T28	517	0
T29	2342	0
T30	472	0
T31	879	0
T32	0	44

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T6,T7,T32

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T6,T7,T32
1	1	Covered	T5,T6,T7

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	100314413	13007	0	0
SrcPulseCheck_M	40346326	13007	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	100314413	13007
T1	0	20
T2	0	32
T4	0	8
T5	24574	2
T6	635661	114
T7	0	56
T8	7824	0
T9	2202	0
T19	0	16
T21	0	30
T23	0	26
T26	5393	0
T27	3859	0
T28	2192	0
T29	8812	0
T30	1993	0
T31	3790	0
T32	0	31

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	40346326	13007
T1	0	20
T2	0	32
T4	0	8
T5	11796	2
T6	713661	114
T7	0	56
T8	1955	0
T9	2202	0
T19	0	16
T21	0	30
T23	0	26
T26	1401	0
T27	1853	0
T28	2127	0
T29	2202	0
T30	1714	0
T31	947	0
T32	0	31

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	100314413	19369	0	0
SrcPulseCheck_M	40346326	19388	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	100314413	19369
T1	0	20
T2	0	32
T4	0	16
T5	24574	9
T6	635661	114
T7	0	56
T8	7824	0
T9	2202	0
T19	0	16
T21	0	30
T23	0	26
T26	5393	0
T27	3859	0
T28	2192	0
T29	8812	0
T30	1993	0
T31	3790	0
T32	0	44

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	40346326	19388
T1	0	20
T2	0	32
T4	0	16
T5	11796	9
T6	713661	114
T7	0	56
T8	1955	0
T9	2202	0
T19	0	16
T21	0	30
T23	0	26
T26	1401	0
T27	1853	0
T28	2127	0
T29	2202	0
T30	1714	0
T31	947	0
T32	0	44

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	40346326	19358	0	0
SrcPulseCheck_M	100314413	19372	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	40346326	19358
T1	0	20
T2	0	32
T4	0	16
T5	11796	9
T6	713661	114
T7	0	56
T8	1955	0
T9	2202	0
T19	0	16
T21	0	30
T23	0	26
T26	1401	0
T27	1853	0
T28	2127	0
T29	2202	0
T30	1714	0
T31	947	0
T32	0	44

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	100314413	19372
T1	0	20
T2	0	32
T4	0	16
T5	24574	9
T6	635661	114
T7	0	56
T8	7824	0
T9	2202	0
T19	0	16
T21	0	30
T23	0	26
T26	5393	0
T27	3859	0
T28	2192	0
T29	8812	0
T30	1993	0
T31	3790	0
T32	0	44

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T6,T7,T32

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T6,T7,T32
1	1	Covered	T5,T6,T7

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	48040659	12613	0	0
SrcPulseCheck_M	40346326	13007	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	48040659	12613
T1	0	20
T2	0	32
T4	0	4
T5	11796	2
T6	305123	114
T7	0	56
T8	3755	0
T9	1057	0
T19	0	16
T21	0	30
T23	0	26
T26	2589	0
T27	1853	0
T28	1052	0
T29	4230	0
T30	956	0
T31	1819	0
T32	0	31

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	40346326	13007
T1	0	20
T2	0	32
T4	0	8
T5	11796	2
T6	713661	114
T7	0	56
T8	1955	0
T9	2202	0
T19	0	16
T21	0	30
T23	0	26
T26	1401	0
T27	1853	0
T28	2127	0
T29	2202	0
T30	1714	0
T31	947	0
T32	0	31

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	48040659	19245	0	0
SrcPulseCheck_M	40346326	19421	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	48040659	19245
T1	0	20
T2	0	32
T4	0	15
T5	11796	9
T6	305123	114
T7	0	56
T8	3755	0
T9	1057	0
T19	0	16
T21	0	30
T23	0	26
T26	2589	0
T27	1853	0
T28	1052	0
T29	4230	0
T30	956	0
T31	1819	0
T32	0	44

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	40346326	19421
T1	0	20
T2	0	32
T4	0	16
T5	11796	9
T6	713661	114
T7	0	56
T8	1955	0
T9	2202	0
T19	0	16
T21	0	30
T23	0	26
T26	1401	0
T27	1853	0
T28	2127	0
T29	2202	0
T30	1714	0
T31	947	0
T32	0	44

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	40346326	19105	0	0
SrcPulseCheck_M	48040659	19271	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	40346326	19105
T1	0	20
T2	0	32
T4	0	15
T5	11796	9
T6	713661	114
T7	0	56
T8	1955	0
T9	2202	0
T19	0	16
T21	0	30
T23	0	26
T26	1401	0
T27	1853	0
T28	2127	0
T29	2202	0
T30	1714	0
T31	947	0
T32	0	44

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	48040659	19271
T1	0	20
T2	0	32
T4	0	15
T5	11796	9
T6	305123	114
T7	0	56
T8	3755	0
T9	1057	0
T19	0	16
T21	0	30
T23	0	26
T26	2589	0
T27	1853	0
T28	1052	0
T29	4230	0
T30	956	0
T31	1819	0
T32	0	44

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T68,T69,T72
1	0	Covered	T68,T69,T72
1	1	Covered	T123,T124,T125

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T68,T69,T72
1	0	Covered	T123,T124,T125
1	1	Covered	T68,T69,T72

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	40346326	28	0	0
SrcPulseCheck_M	90532656	28	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	40346326	28
T68	5021	1
T69	16886	1
T72	9461	2
T74	6412	1
T75	6404	1
T76	13198	1
T120	3020	2
T121	8806	2
T122	5000	1
T126	6465	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	90532656	28
T68	19280	1
T69	16373	1
T72	9082	2
T74	25648	1
T75	25615	1
T76	13060	1
T120	14494	2
T121	16907	2
T122	17143	1
T126	25859	1

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T68,T72,T75
1	0	Covered	T68,T72,T75
1	1	Covered	T122,T123,T124

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T68,T72,T75
1	0	Covered	T122,T123,T124
1	1	Covered	T68,T72,T75

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	40346326	28	0	0
SrcPulseCheck_M	90532656	28	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	40346326	28
T68	5021	1
T72	9461	3
T74	6412	1
T75	6404	1
T76	13198	4
T92	3015	1
T120	3020	1
T121	8806	2
T122	5000	3
T127	5256	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	90532656	28
T68	19280	1
T72	9082	3
T74	25648	1
T75	25615	1
T76	13060	4
T92	19296	1
T120	14494	1
T121	16907	2
T122	17143	3
T127	12306	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T68,T71,T72
1	0	Covered	T68,T71,T72
1	1	Covered	T121,T128,T129

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T68,T71,T72
1	0	Covered	T121,T128,T129
1	1	Covered	T68,T71,T72

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	40346326	34	0	0
SrcPulseCheck_M	44405581	34	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	40346326	34
T68	5021	1
T71	3224	2
T72	9461	1
T73	10877	1
T74	6412	1
T76	13198	2
T120	3020	2
T121	8806	2
T122	5000	2
T130	13015	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	44405581	34
T68	9190	1
T71	5858	2
T72	3808	1
T73	4556	1
T74	11866	1
T76	5448	2
T120	6706	2
T121	7562	2
T122	7836	2
T130	5633	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T71,T72,T73
1	0	Covered	T71,T72,T73
1	1	Covered	T121,T128,T131

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T71,T72,T73
1	0	Covered	T121,T128,T131
1	1	Covered	T71,T72,T73

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	40346326	27	0	0
SrcPulseCheck_M	44405581	27	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	40346326	27
T71	3224	1
T72	9461	1
T73	10877	1
T74	6412	1
T76	13198	1
T120	3020	2
T121	8806	2
T122	5000	2
T128	4034	4
T132	8511	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	44405581	27
T71	5858	1
T72	3808	1
T73	4556	1
T74	11866	1
T76	5448	1
T120	6706	2
T121	7562	2
T122	7836	2
T128	7447	4
T132	15339	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T68,T69,T72
1	0	Covered	T68,T69,T72
1	1	Covered	T92,T122,T127

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T68,T69,T72
1	0	Covered	T92,T122,T127
1	1	Covered	T68,T69,T72

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	40346326	36	0	0
SrcPulseCheck_M	22202332	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	40346326	36
T68	5021	1
T69	16886	2
T72	9461	1
T73	10877	2
T75	6404	1
T76	13198	2
T92	3015	3
T121	8806	1
T122	5000	2
T126	6465	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	22202332	36
T68	4598	1
T69	3615	2
T72	1903	1
T73	2281	2
T75	6217	1
T76	2723	2
T92	4624	3
T121	3780	1
T122	3918	2
T126	6140	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T69,T72,T75
1	0	Covered	T69,T72,T75
1	1	Covered	T122,T132,T129

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T69,T72,T75
1	0	Covered	T122,T132,T129
1	1	Covered	T69,T72,T75

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	40346326	34	0	0
SrcPulseCheck_M	22202332	34	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	40346326	34
T69	16886	1
T72	9461	1
T73	10877	1
T75	6404	2
T76	13198	2
T92	3015	2
T121	8806	3
T122	5000	2
T126	6465	1
T130	13015	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	22202332	34
T69	3615	1
T72	1903	1
T73	2281	1
T75	6217	2
T76	2723	2
T92	4624	2
T121	3780	3
T122	3918	2
T126	6140	1
T130	2817	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T69,T73,T76
1	0	Covered	T69,T73,T76
1	1	Covered	T128,T125

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T69,T73,T76
1	0	Covered	T128,T125
1	1	Covered	T69,T73,T76

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	40346326	27	0	0
SrcPulseCheck_M	100314413	27	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	40346326	27
T69	16886	1
T73	10877	2
T76	13198	1
T122	5000	1
T128	4034	2
T132	8511	2
T133	5549	1
T134	4075	1
T135	14615	2
T136	2841	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	100314413	27
T69	17057	1
T73	11099	2
T76	13605	1
T122	17859	1
T128	16810	2
T132	34045	2
T133	32643	1
T134	4245	1
T135	29230	2
T136	31579	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T69,T72,T75
1	0	Covered	T69,T72,T75
1	1	Covered	T76,T128,T124

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T69,T72,T75
1	0	Covered	T76,T128,T124
1	1	Covered	T69,T72,T75

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	40346326	33	0	0
SrcPulseCheck_M	100314413	33	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	40346326	33
T69	16886	1
T72	9461	2
T73	10877	1
T74	6412	1
T75	6404	1
T76	13198	2
T122	5000	2
T126	6465	1
T133	5549	1
T134	4075	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	100314413	33
T69	17057	1
T72	9461	2
T73	11099	1
T74	26718	1
T75	26684	1
T76	13605	2
T122	17859	2
T126	26938	1
T133	32643	1
T134	4245	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T71,T69,T70
1	0	Covered	T71,T69,T70
1	1	Covered	T122,T132

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T71,T69,T70
1	0	Covered	T122,T132
1	1	Covered	T71,T69,T70

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	40346326	29	0	0
SrcPulseCheck_M	48040659	29	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	40346326	29
T69	16886	1
T70	11917	1
T71	3224	1
T72	9461	1
T74	6412	1
T76	13198	1
T92	3015	1
T121	8806	2
T122	5000	3
T137	6681	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	48040659	29
T69	8187	1
T70	11674	1
T71	6191	1
T72	4541	1
T74	12825	1
T76	6530	1
T92	9649	1
T121	8454	2
T122	8572	3
T137	3340	2

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T71,T69,T72
1	0	Covered	T71,T69,T72
1	1	Covered	T121,T128,T132

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T71,T69,T72
1	0	Covered	T121,T128,T132
1	1	Covered	T71,T69,T72

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	40346326	32	0	0
SrcPulseCheck_M	48040659	32	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	40346326	32
T69	16886	1
T71	3224	2
T72	9461	1
T74	6412	1
T76	13198	1
T92	3015	1
T121	8806	2
T122	5000	2
T135	14615	1
T138	6913	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	48040659	32
T69	8187	1
T71	6191	2
T72	4541	1
T74	12825	1
T76	6530	1
T92	9649	1
T121	8454	2
T122	8572	2
T135	14031	1
T138	6772	1

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T6,T7,T32
1	0	Covered	T6,T7,T32
1	1	Covered	T6,T7,T32

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T6,T7,T32
1	0	Covered	T6,T7,T32
1	1	Covered	T6,T7,T32

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	88028435	49441	0	0
SrcPulseCheck_M	1444438	48806	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	88028435	49441
T1	0	83
T2	0	78
T6	564137	670
T7	281376	302
T19	0	89
T21	0	170
T23	0	86
T31	3638	0
T32	193150	117
T33	0	21
T36	2200	0
T48	5306	0
T77	1967	0
T82	1105	0
T83	2933	0
T84	7551	0
T119	0	114

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1444438	48806
T1	0	83
T2	0	78
T6	2716	670
T7	1673	302
T19	0	89
T21	0	170
T23	0	86
T31	265	0
T32	2470	118
T33	0	21
T36	160	0
T48	386	0
T77	143	0
T82	80	0
T83	214	0
T84	550	0
T119	0	114

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T6,T7,T32
1	0	Covered	T6,T7,T32
1	1	Covered	T6,T7,T32

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T6,T7,T32
1	0	Covered	T6,T7,T32
1	1	Covered	T6,T7,T32

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	43200033	48858	0	0
SrcPulseCheck_M	1444438	48231	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	43200033	48858
T1	0	76
T2	0	78
T6	282297	670
T7	141093	302
T19	0	81
T21	0	170
T23	0	86
T31	1759	0
T32	92900	117
T33	0	21
T36	1202	0
T48	2607	0
T77	995	0
T82	552	0
T83	1600	0
T84	3756	0
T119	0	111

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1444438	48231
T1	0	76
T2	0	78
T6	2716	670
T7	1673	302
T19	0	81
T21	0	170
T23	0	86
T31	265	0
T32	2470	118
T33	0	21
T36	160	0
T48	386	0
T77	143	0
T82	80	0
T83	214	0
T84	550	0
T119	0	111

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T6,T7,T32
1	0	Covered	T6,T7,T32
1	1	Covered	T6,T7,T32

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T6,T7,T32
1	0	Covered	T6,T7,T32
1	1	Covered	T6,T7,T32

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	21599568	48109	0	0
SrcPulseCheck_M	1444438	47498	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	21599568	48109
T1	0	79
T2	0	78
T6	141141	670
T7	70546	302
T19	0	80
T21	0	170
T23	0	86
T31	879	0
T32	46445	117
T33	0	20
T36	599	0
T48	1303	0
T77	498	0
T82	276	0
T83	800	0
T84	1878	0
T119	0	103

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1444438	47498
T1	0	79
T2	0	78
T6	2716	670
T7	1673	302
T19	0	80
T21	0	170
T23	0	86
T31	265	0
T32	2470	118
T33	0	20
T36	160	0
T48	386	0
T77	143	0
T82	80	0
T83	214	0
T84	550	0
T119	0	103

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T6,T7,T32
1	0	Covered	T6,T7,T32
1	1	Covered	T6,T7,T32

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T6,T7,T32
1	0	Covered	T6,T7,T32
1	1	Covered	T6,T7,T32

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	97705756	59152	0	0
SrcPulseCheck_M	1460010	58276	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	97705756	59152
T1	0	73
T2	0	78
T6	635661	766
T7	329109	374
T19	0	137
T21	0	230
T23	0	206
T31	3790	0
T32	225204	156
T33	0	18
T36	2292	0
T48	5528	0
T77	2049	0
T82	1150	0
T83	3055	0
T84	7866	0
T119	0	186

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1460010	58276
T1	0	73
T2	0	78
T6	2812	766
T7	1745	374
T19	0	137
T21	0	230
T23	0	206
T31	265	0
T32	2518	156
T33	0	18
T36	160	0
T48	386	0
T77	143	0
T82	80	0
T83	214	0
T84	550	0
T119	0	186

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T6,T7,T32
1	0	Covered	T6,T7,T32
1	1	Covered	T6,T7,T32

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T6,T7,T32
1	0	Covered	T6,T7,T32
1	1	Covered	T6,T7,T32

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T5,T8,T9

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	46788525	57682	0	0
SrcPulseCheck_M	1457885	57013	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	46788525	57682
T1	0	65
T2	0	78
T6	305123	766
T7	172375	434
T19	0	133
T21	0	170
T23	0	182
T31	1819	0
T32	102917	144
T33	0	18
T36	1100	0
T48	2653	0
T77	984	0
T82	552	0
T83	1467	0
T84	3775	0
T119	0	155

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1457885	57013
T1	0	65
T2	0	78
T6	2812	766
T7	1805	434
T19	0	133
T21	0	170
T23	0	182
T31	265	0
T32	1707	99
T33	0	18
T36	160	0
T48	386	0
T77	143	0
T82	80	0
T83	214	0
T84	550	0
T119	0	155

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb