Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	100.00	86.67			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_en_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc	97.92	100.00	91.67			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	97.74	86.76			94.92	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.44	96.94	84.78			93.02	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.66	96.24	80.88			91.53	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	83.59	94.90	76.09			88.37	75.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.39	100.00	93.55			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.91	100.00	99.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T32,T4
1	0	Covered	T5,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	403463260	801870	0	0
DstReqKnown_A	610991282	585181792	0	0
SrcAckBusyChk_A	403463260	161293	0	0
SrcBusyKnown_A	403463260	378205910	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403463260	801870	0	0
T1	0	561	0	0
T2	0	2747	0	0
T4	0	598	0	0
T5	117960	287	0	0
T6	7136610	9585	0	0
T7	0	2242	0	0
T8	19550	0	0	0
T9	22020	0	0	0
T19	0	399	0	0
T21	0	2667	0	0
T23	0	2220	0	0
T26	14010	0	0	0
T27	18530	0	0	0
T28	21270	0	0	0
T29	22020	0	0	0
T30	17140	0	0	0
T31	9470	0	0	0
T32	0	1869	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	610991282	585181792	0	0
T5	139118	81394	0	0
T6	3856718	3844796	0	0
T8	50274	49576	0	0
T9	14190	13222	0	0
T26	34468	33160	0	0
T27	24268	23502	0	0
T28	13798	13332	0	0
T29	57062	56362	0	0
T30	12556	11618	0	0
T31	23770	22430	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403463260	161293	0	0
T1	0	200	0	0
T2	0	320	0	0
T4	0	115	0	0
T5	117960	55	0	0
T6	7136610	1140	0	0
T7	0	560	0	0
T8	19550	0	0	0
T9	22020	0	0	0
T19	0	160	0	0
T21	0	300	0	0
T23	0	260	0	0
T26	14010	0	0	0
T27	18530	0	0	0
T28	21270	0	0	0
T29	22020	0	0	0
T30	17140	0	0	0
T31	9470	0	0	0
T32	0	375	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403463260	378205910	0	0
T5	117960	61590	0	0
T6	7136610	7115520	0	0
T8	19550	19240	0	0
T9	22020	20330	0	0
T26	14010	13430	0	0
T27	18530	17850	0	0
T28	21270	20460	0	0
T29	22020	21710	0	0
T30	17140	15810	0	0
T31	9470	8870	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Unreachable
1	0	Covered	T5,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	40346326	45126	0	0
DstReqKnown_A	90532656	86164422	0	0
SrcAckBusyChk_A	40346326	13007	0	0
SrcBusyKnown_A	40346326	37820591	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	45126	0	0
T1	0	53	0	0
T2	0	164	0	0
T4	0	29	0	0
T5	11796	8	0	0
T6	713661	581	0	0
T7	0	170	0	0
T8	1955	0	0	0
T9	2202	0	0	0
T19	0	39	0	0
T21	0	161	0	0
T23	0	135	0	0
T26	1401	0	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	106	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90532656	86164422	0	0
T5	19849	12294	0	0
T6	564137	562111	0	0
T8	7511	7390	0	0
T9	2115	1953	0	0
T26	5177	4960	0	0
T27	3704	3570	0	0
T28	2105	2025	0	0
T29	8459	8338	0	0
T30	1913	1765	0	0
T31	3638	3407	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	13007	0	0
T1	0	20	0	0
T2	0	32	0	0
T4	0	8	0	0
T5	11796	2	0	0
T6	713661	114	0	0
T7	0	56	0	0
T8	1955	0	0	0
T9	2202	0	0	0
T19	0	16	0	0
T21	0	30	0	0
T23	0	26	0	0
T26	1401	0	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	31	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	37820591	0	0
T5	11796	6159	0	0
T6	713661	711552	0	0
T8	1955	1924	0	0
T9	2202	2033	0	0
T26	1401	1343	0	0
T27	1853	1785	0	0
T28	2127	2046	0	0
T29	2202	2171	0	0
T30	1714	1581	0	0
T31	947	887	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Unreachable
1	0	Covered	T5,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	40346326	63222	0	0
DstReqKnown_A	44405581	43301895	0	0
SrcAckBusyChk_A	40346326	13007	0	0
SrcBusyKnown_A	40346326	37820591	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	63222	0	0
T1	0	53	0	0
T2	0	274	0	0
T4	0	42	0	0
T5	11796	12	0	0
T6	713661	934	0	0
T7	0	225	0	0
T8	1955	0	0	0
T9	2202	0	0	0
T19	0	39	0	0
T21	0	265	0	0
T23	0	225	0	0
T26	1401	0	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	150	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44405581	43301895	0	0
T5	8894	6274	0	0
T6	282297	281755	0	0
T8	4032	4004	0	0
T9	1148	1100	0	0
T26	2718	2649	0	0
T27	1812	1785	0	0
T28	1033	1012	0	0
T29	4688	4660	0	0
T30	944	882	0	0
T31	1759	1704	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	13007	0	0
T1	0	20	0	0
T2	0	32	0	0
T4	0	8	0	0
T5	11796	2	0	0
T6	713661	114	0	0
T7	0	56	0	0
T8	1955	0	0	0
T9	2202	0	0	0
T19	0	16	0	0
T21	0	30	0	0
T23	0	26	0	0
T26	1401	0	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	31	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	37820591	0	0
T5	11796	6159	0	0
T6	713661	711552	0	0
T8	1955	1924	0	0
T9	2202	2033	0	0
T26	1401	1343	0	0
T27	1853	1785	0	0
T28	2127	2046	0	0
T29	2202	2171	0	0
T30	1714	1581	0	0
T31	947	887	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Unreachable
1	0	Covered	T5,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	40346326	99497	0	0
DstReqKnown_A	22202332	21650598	0	0
SrcAckBusyChk_A	40346326	13007	0	0
SrcBusyKnown_A	40346326	37820591	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	99497	0	0
T1	0	69	0	0
T2	0	467	0	0
T4	0	68	0	0
T5	11796	18	0	0
T6	713661	1657	0	0
T7	0	333	0	0
T8	1955	0	0	0
T9	2202	0	0	0
T19	0	43	0	0
T21	0	454	0	0
T23	0	377	0	0
T26	1401	0	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	241	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22202332	21650598	0	0
T5	4446	3136	0	0
T6	141141	140869	0	0
T8	2015	2001	0	0
T9	573	549	0	0
T26	1357	1323	0	0
T27	906	892	0	0
T28	517	507	0	0
T29	2342	2328	0	0
T30	472	441	0	0
T31	879	851	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	13007	0	0
T1	0	20	0	0
T2	0	32	0	0
T4	0	8	0	0
T5	11796	2	0	0
T6	713661	114	0	0
T7	0	56	0	0
T8	1955	0	0	0
T9	2202	0	0	0
T19	0	16	0	0
T21	0	30	0	0
T23	0	26	0	0
T26	1401	0	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	31	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	37820591	0	0
T5	11796	6159	0	0
T6	713661	711552	0	0
T8	1955	1924	0	0
T9	2202	2033	0	0
T26	1401	1343	0	0
T27	1853	1785	0	0
T28	2127	2046	0	0
T29	2202	2171	0	0
T30	1714	1581	0	0
T31	947	887	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Unreachable
1	0	Covered	T5,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	40346326	44402	0	0
DstReqKnown_A	100314413	95670363	0	0
SrcAckBusyChk_A	40346326	13007	0	0
SrcBusyKnown_A	40346326	37820591	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	44402	0	0
T1	0	53	0	0
T2	0	194	0	0
T4	0	29	0	0
T5	11796	8	0	0
T6	713661	682	0	0
T7	0	169	0	0
T8	1955	0	0	0
T9	2202	0	0	0
T19	0	39	0	0
T21	0	190	0	0
T23	0	158	0	0
T26	1401	0	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	104	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100314413	95670363	0	0
T5	24574	12834	0	0
T6	635661	633552	0	0
T8	7824	7698	0	0
T9	2202	2033	0	0
T26	5393	5167	0	0
T27	3859	3719	0	0
T28	2192	2109	0	0
T29	8812	8686	0	0
T30	1993	1839	0	0
T31	3790	3550	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	13007	0	0
T1	0	20	0	0
T2	0	32	0	0
T4	0	8	0	0
T5	11796	2	0	0
T6	713661	114	0	0
T7	0	56	0	0
T8	1955	0	0	0
T9	2202	0	0	0
T19	0	16	0	0
T21	0	30	0	0
T23	0	26	0	0
T26	1401	0	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	31	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	37820591	0	0
T5	11796	6159	0	0
T6	713661	711552	0	0
T8	1955	1924	0	0
T9	2202	2033	0	0
T26	1401	1343	0	0
T27	1853	1785	0	0
T28	2127	2046	0	0
T29	2202	2171	0	0
T30	1714	1581	0	0
T31	947	887	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Unreachable
1	0	Covered	T5,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	40346326	61441	0	0
DstReqKnown_A	48040659	45803618	0	0
SrcAckBusyChk_A	40346326	12564	0	0
SrcBusyKnown_A	40346326	37820591	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	61441	0	0
T1	0	53	0	0
T2	0	265	0	0
T4	0	26	0	0
T5	11796	14	0	0
T6	713661	925	0	0
T7	0	226	0	0
T8	1955	0	0	0
T9	2202	0	0	0
T19	0	39	0	0
T21	0	263	0	0
T23	0	217	0	0
T26	1401	0	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	181	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48040659	45803618	0	0
T5	11796	6159	0	0
T6	305123	304111	0	0
T8	3755	3695	0	0
T9	1057	976	0	0
T26	2589	2481	0	0
T27	1853	1785	0	0
T28	1052	1013	0	0
T29	4230	4169	0	0
T30	956	882	0	0
T31	1819	1703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	12564	0	0
T1	0	20	0	0
T2	0	32	0	0
T4	0	4	0	0
T5	11796	2	0	0
T6	713661	114	0	0
T7	0	56	0	0
T8	1955	0	0	0
T9	2202	0	0	0
T19	0	16	0	0
T21	0	30	0	0
T23	0	26	0	0
T26	1401	0	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	31	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	37820591	0	0
T5	11796	6159	0	0
T6	713661	711552	0	0
T8	1955	1924	0	0
T9	2202	2033	0	0
T26	1401	1343	0	0
T27	1853	1785	0	0
T28	2127	2046	0	0
T29	2202	2171	0	0
T30	1714	1581	0	0
T31	947	887	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T32,T4
1	0	Covered	T5,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Unreachable
1	0	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	40346326	68961	0	0
DstReqKnown_A	90532656	86164422	0	0
SrcAckBusyChk_A	40346326	19332	0	0
SrcBusyKnown_A	40346326	37820591	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	68961	0	0
T1	0	53	0	0
T2	0	169	0	0
T4	0	56	0	0
T5	11796	31	0	0
T6	713661	587	0	0
T7	0	171	0	0
T8	1955	0	0	0
T9	2202	0	0	0
T19	0	39	0	0
T21	0	163	0	0
T23	0	136	0	0
T26	1401	0	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	148	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90532656	86164422	0	0
T5	19849	12294	0	0
T6	564137	562111	0	0
T8	7511	7390	0	0
T9	2115	1953	0	0
T26	5177	4960	0	0
T27	3704	3570	0	0
T28	2105	2025	0	0
T29	8459	8338	0	0
T30	1913	1765	0	0
T31	3638	3407	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	19332	0	0
T1	0	20	0	0
T2	0	32	0	0
T4	0	16	0	0
T5	11796	9	0	0
T6	713661	114	0	0
T7	0	56	0	0
T8	1955	0	0	0
T9	2202	0	0	0
T19	0	16	0	0
T21	0	30	0	0
T23	0	26	0	0
T26	1401	0	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	44	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	37820591	0	0
T5	11796	6159	0	0
T6	713661	711552	0	0
T8	1955	1924	0	0
T9	2202	2033	0	0
T26	1401	1343	0	0
T27	1853	1785	0	0
T28	2127	2046	0	0
T29	2202	2171	0	0
T30	1714	1581	0	0
T31	947	887	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T32,T4
1	0	Covered	T5,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Unreachable
1	0	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	40346326	97279	0	0
DstReqKnown_A	44405581	43301895	0	0
SrcAckBusyChk_A	40346326	19353	0	0
SrcBusyKnown_A	40346326	37820591	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	97279	0	0
T1	0	53	0	0
T2	0	273	0	0
T4	0	80	0	0
T5	11796	44	0	0
T6	713661	929	0	0
T7	0	228	0	0
T8	1955	0	0	0
T9	2202	0	0	0
T19	0	39	0	0
T21	0	264	0	0
T23	0	216	0	0
T26	1401	0	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	208	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44405581	43301895	0	0
T5	8894	6274	0	0
T6	282297	281755	0	0
T8	4032	4004	0	0
T9	1148	1100	0	0
T26	2718	2649	0	0
T27	1812	1785	0	0
T28	1033	1012	0	0
T29	4688	4660	0	0
T30	944	882	0	0
T31	1759	1704	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	19353	0	0
T1	0	20	0	0
T2	0	32	0	0
T4	0	16	0	0
T5	11796	9	0	0
T6	713661	114	0	0
T7	0	56	0	0
T8	1955	0	0	0
T9	2202	0	0	0
T19	0	16	0	0
T21	0	30	0	0
T23	0	26	0	0
T26	1401	0	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	44	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	37820591	0	0
T5	11796	6159	0	0
T6	713661	711552	0	0
T8	1955	1924	0	0
T9	2202	2033	0	0
T26	1401	1343	0	0
T27	1853	1785	0	0
T28	2127	2046	0	0
T29	2202	2171	0	0
T30	1714	1581	0	0
T31	947	887	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T32,T4
1	0	Covered	T5,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Unreachable
1	0	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	40346326	157399	0	0
DstReqKnown_A	22202332	21650598	0	0
SrcAckBusyChk_A	40346326	19526	0	0
SrcBusyKnown_A	40346326	37820591	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	157399	0	0
T1	0	68	0	0
T2	0	472	0	0
T4	0	132	0	0
T5	11796	68	0	0
T6	713661	1671	0	0
T7	0	335	0	0
T8	1955	0	0	0
T9	2202	0	0	0
T19	0	44	0	0
T21	0	453	0	0
T23	0	379	0	0
T26	1401	0	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	333	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22202332	21650598	0	0
T5	4446	3136	0	0
T6	141141	140869	0	0
T8	2015	2001	0	0
T9	573	549	0	0
T26	1357	1323	0	0
T27	906	892	0	0
T28	517	507	0	0
T29	2342	2328	0	0
T30	472	441	0	0
T31	879	851	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	19526	0	0
T1	0	20	0	0
T2	0	32	0	0
T4	0	16	0	0
T5	11796	9	0	0
T6	713661	114	0	0
T7	0	56	0	0
T8	1955	0	0	0
T9	2202	0	0	0
T19	0	16	0	0
T21	0	30	0	0
T23	0	26	0	0
T26	1401	0	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	44	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	37820591	0	0
T5	11796	6159	0	0
T6	713661	711552	0	0
T8	1955	1924	0	0
T9	2202	2033	0	0
T26	1401	1343	0	0
T27	1853	1785	0	0
T28	2127	2046	0	0
T29	2202	2171	0	0
T30	1714	1581	0	0
T31	947	887	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T32,T4
1	0	Covered	T5,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Unreachable
1	0	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	40346326	67433	0	0
DstReqKnown_A	100314413	95670363	0	0
SrcAckBusyChk_A	40346326	19358	0	0
SrcBusyKnown_A	40346326	37820591	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	67433	0	0
T1	0	53	0	0
T2	0	196	0	0
T4	0	56	0	0
T5	11796	31	0	0
T6	713661	682	0	0
T7	0	161	0	0
T8	1955	0	0	0
T9	2202	0	0	0
T19	0	39	0	0
T21	0	190	0	0
T23	0	158	0	0
T26	1401	0	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	146	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100314413	95670363	0	0
T5	24574	12834	0	0
T6	635661	633552	0	0
T8	7824	7698	0	0
T9	2202	2033	0	0
T26	5393	5167	0	0
T27	3859	3719	0	0
T28	2192	2109	0	0
T29	8812	8686	0	0
T30	1993	1839	0	0
T31	3790	3550	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	19358	0	0
T1	0	20	0	0
T2	0	32	0	0
T4	0	16	0	0
T5	11796	9	0	0
T6	713661	114	0	0
T7	0	56	0	0
T8	1955	0	0	0
T9	2202	0	0	0
T19	0	16	0	0
T21	0	30	0	0
T23	0	26	0	0
T26	1401	0	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	44	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	37820591	0	0
T5	11796	6159	0	0
T6	713661	711552	0	0
T8	1955	1924	0	0
T9	2202	2033	0	0
T26	1401	1343	0	0
T27	1853	1785	0	0
T28	2127	2046	0	0
T29	2202	2171	0	0
T30	1714	1581	0	0
T31	947	887	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T32,T4
1	0	Covered	T5,T6,T7

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Unreachable
1	0	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T9
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T8,T9
0	1	-	Covered	T5,T6,T7
0	0	1	Covered	T5,T6,T7
0	0	0	Covered	T5,T8,T9

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	40346326	97110	0	0
DstReqKnown_A	48040659	45803618	0	0
SrcAckBusyChk_A	40346326	19132	0	0
SrcBusyKnown_A	40346326	37820591	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	97110	0	0
T1	0	53	0	0
T2	0	273	0	0
T4	0	80	0	0
T5	11796	53	0	0
T6	713661	937	0	0
T7	0	224	0	0
T8	1955	0	0	0
T9	2202	0	0	0
T19	0	39	0	0
T21	0	264	0	0
T23	0	219	0	0
T26	1401	0	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	252	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48040659	45803618	0	0
T5	11796	6159	0	0
T6	305123	304111	0	0
T8	3755	3695	0	0
T9	1057	976	0	0
T26	2589	2481	0	0
T27	1853	1785	0	0
T28	1052	1013	0	0
T29	4230	4169	0	0
T30	956	882	0	0
T31	1819	1703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	19132	0	0
T1	0	20	0	0
T2	0	32	0	0
T4	0	15	0	0
T5	11796	9	0	0
T6	713661	114	0	0
T7	0	56	0	0
T8	1955	0	0	0
T9	2202	0	0	0
T19	0	16	0	0
T21	0	30	0	0
T23	0	26	0	0
T26	1401	0	0	0
T27	1853	0	0	0
T28	2127	0	0	0
T29	2202	0	0	0
T30	1714	0	0	0
T31	947	0	0	0
T32	0	44	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40346326	37820591	0	0
T5	11796	6159	0	0
T6	713661	711552	0	0
T8	1955	1924	0	0
T9	2202	2033	0	0
T26	1401	1343	0	0
T27	1853	1785	0	0
T28	2127	2046	0	0
T29	2202	2171	0	0
T30	1714	1581	0	0
T31	947	887	0	0