Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T28
0	1	Covered	T6,T105,T22
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T49
1	0	Covered	T28,T47,T21
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	200347508	8481	0	0
GateOpen_A	200347508	14800	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200347508	8481	0	0
T5	3584	3	0	0
T6	3275	20	0	0
T21	0	20	0	0
T22	0	40	0	0
T27	7803	0	0	0
T28	6063	16	0	0
T29	13979	0	0	0
T30	43480	0	0	0
T31	4058	0	0	0
T32	3497	0	0	0
T33	3381	0	0	0
T44	0	4	0	0
T47	0	12	0	0
T49	11326	4	0	0
T87	4404	0	0	0
T105	0	26	0	0
T122	0	1	0	0
T182	0	21	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200347508	14800	0	0
T4	5814	4	0	0
T5	4028	3	0	0
T6	3275	24	0	0
T27	7803	4	0	0
T28	6063	20	0	0
T29	13979	4	0	0
T30	43480	4	0	0
T31	4058	4	0	0
T32	3497	4	0	0
T33	3381	0	0	0
T49	0	4	0	0
T87	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T28,T49
0	1	Covered	T6,T105,T22
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T49,T105
1	0	Covered	T28,T47,T21
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	21655120	2038	0	0
GateOpen_A	21655120	3614	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21655120	2038	0	0
T6	349	4	0	0
T21	0	5	0	0
T22	0	10	0	0
T27	854	0	0	0
T28	661	4	0	0
T29	1549	0	0	0
T30	5199	0	0	0
T31	454	0	0	0
T32	382	0	0	0
T33	358	0	0	0
T44	0	1	0	0
T47	0	3	0	0
T49	1248	1	0	0
T87	4404	0	0	0
T105	0	6	0	0
T122	0	1	0	0
T182	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21655120	3614	0	0
T4	679	1	0	0
T5	444	0	0	0
T6	349	5	0	0
T27	854	1	0	0
T28	661	5	0	0
T29	1549	1	0	0
T30	5199	1	0	0
T31	454	1	0	0
T32	382	1	0	0
T33	358	0	0	0
T49	0	1	0	0
T87	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T28
0	1	Covered	T6,T105,T22
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T49
1	0	Covered	T28,T47,T21
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	43310700	2163	0	0
GateOpen_A	43310700	3739	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43310700	2163	0	0
T5	887	1	0	0
T6	697	5	0	0
T21	0	5	0	0
T22	0	10	0	0
T27	1708	0	0	0
T28	1321	4	0	0
T29	3098	0	0	0
T30	10398	0	0	0
T31	910	0	0	0
T32	763	0	0	0
T33	716	0	0	0
T44	0	1	0	0
T47	0	3	0	0
T49	2495	1	0	0
T105	0	7	0	0
T182	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43310700	3739	0	0
T4	1361	1	0	0
T5	887	1	0	0
T6	697	6	0	0
T27	1708	1	0	0
T28	1321	5	0	0
T29	3098	1	0	0
T30	10398	1	0	0
T31	910	1	0	0
T32	763	1	0	0
T33	716	0	0	0
T49	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T28
0	1	Covered	T6,T105,T22
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T49
1	0	Covered	T28,T47,T21
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	88308290	2154	0	0
GateOpen_A	88308290	3738	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88308290	2154	0	0
T5	1798	1	0	0
T6	1486	5	0	0
T21	0	5	0	0
T22	0	10	0	0
T27	3494	0	0	0
T28	2763	4	0	0
T29	6221	0	0	0
T30	18589	0	0	0
T31	1796	0	0	0
T32	1568	0	0	0
T33	1538	0	0	0
T44	0	1	0	0
T47	0	3	0	0
T49	5055	1	0	0
T105	0	6	0	0
T182	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88308290	3738	0	0
T4	2516	1	0	0
T5	1798	1	0	0
T6	1486	6	0	0
T27	3494	1	0	0
T28	2763	5	0	0
T29	6221	1	0	0
T30	18589	1	0	0
T31	1796	1	0	0
T32	1568	1	0	0
T33	1538	0	0	0
T49	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T28
0	1	Covered	T6,T105,T22
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T49
1	0	Covered	T28,T47,T21
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	47073398	2126	0	0
GateOpen_A	47073398	3709	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47073398	2126	0	0
T5	899	1	0	0
T6	743	6	0	0
T21	0	5	0	0
T22	0	10	0	0
T27	1747	0	0	0
T28	1318	4	0	0
T29	3111	0	0	0
T30	9294	0	0	0
T31	898	0	0	0
T32	784	0	0	0
T33	769	0	0	0
T44	0	1	0	0
T47	0	3	0	0
T49	2528	1	0	0
T105	0	7	0	0
T182	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47073398	3709	0	0
T4	1258	1	0	0
T5	899	1	0	0
T6	743	7	0	0
T27	1747	1	0	0
T28	1318	5	0	0
T29	3111	1	0	0
T30	9294	1	0	0
T31	898	1	0	0
T32	784	1	0	0
T33	769	0	0	0
T49	0	1	0	0