Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : clkmgr
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.65 100.00 93.24 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 98.65 100.00 93.24 100.00 100.00 100.00


Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.65 100.00 93.24 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.47 99.15 95.84 100.00 100.00 98.81 97.02


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
clkmgr_aes_trans_sva_if 100.00 100.00
clkmgr_aon_cg_aon_peri 100.00 100.00
clkmgr_aon_cg_aon_powerup 100.00 100.00
clkmgr_aon_cg_aon_secure 100.00 100.00
clkmgr_aon_cg_aon_timers 100.00 100.00
clkmgr_aon_cg_io_div2_powerup 100.00 100.00
clkmgr_aon_cg_io_div4_powerup 100.00 100.00
clkmgr_aon_cg_io_powerup 100.00 100.00
clkmgr_aon_cg_main_powerup 100.00 100.00
clkmgr_aon_cg_usb_powerup 100.00 100.00
clkmgr_cg_io_div2_infra 100.00 100.00 100.00 100.00
clkmgr_cg_io_div2_peri 100.00 100.00 100.00 100.00
clkmgr_cg_io_div4_infra 100.00 100.00 100.00 100.00
clkmgr_cg_io_div4_peri 100.00 100.00 100.00 100.00
clkmgr_cg_io_div4_secure 100.00 100.00 100.00 100.00
clkmgr_cg_io_div4_timers 100.00 100.00 100.00 100.00
clkmgr_cg_io_infra 100.00 100.00 100.00 100.00
clkmgr_cg_io_peri 100.00 100.00 100.00 100.00
clkmgr_cg_main_aes 100.00 100.00 100.00 100.00
clkmgr_cg_main_hmac 100.00 100.00 100.00 100.00
clkmgr_cg_main_infra 100.00 100.00 100.00 100.00
clkmgr_cg_main_kmac 100.00 100.00 100.00 100.00
clkmgr_cg_main_otbn 100.00 100.00 100.00 100.00
clkmgr_cg_main_secure 100.00 100.00 100.00 100.00
clkmgr_cg_usb_infra 100.00 100.00 100.00 100.00
clkmgr_cg_usb_peri 100.00 100.00 100.00 100.00
clkmgr_csr_assert 100.00 100.00
clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
clkmgr_div4_sva_if 100.00 100.00 100.00 100.00
clkmgr_extclk_sva_if 100.00 100.00 100.00 100.00
clkmgr_hmac_trans_sva_if 100.00 100.00
clkmgr_io_div2_peri_sva_if 100.00 100.00 100.00 100.00
clkmgr_io_div4_peri_sva_if 100.00 100.00 100.00 100.00
clkmgr_io_peri_sva_if 100.00 100.00 100.00 100.00
clkmgr_kmac_trans_sva_if 100.00 100.00
clkmgr_lost_calib_io_ctrl_en_sva_if 100.00 100.00
clkmgr_lost_calib_io_div2_ctrl_en_sva_if 100.00 100.00
clkmgr_lost_calib_io_div4_ctrl_en_sva_if 100.00 100.00
clkmgr_lost_calib_main_ctrl_en_sva_if 100.00 100.00
clkmgr_lost_calib_regwen_sva_if 100.00 100.00
clkmgr_lost_calib_usb_ctrl_en_sva_if 100.00 100.00
clkmgr_otbn_trans_sva_if 100.00 100.00
clkmgr_pwrmgr_io_sva_if 100.00 100.00
clkmgr_pwrmgr_main_sva_if 100.00 100.00
clkmgr_pwrmgr_usb_sva_if 100.00 100.00
clkmgr_sec_cm_checker_assert 100.00 100.00 100.00 100.00
clkmgr_usb_peri_sva_if 100.00 100.00 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
tlul_assert_device 99.30 100.00 100.00 97.90
u_calib_rdy_sync 100.00 100.00 100.00 100.00
u_clk_aon_buf 100.00 100.00
u_clk_aon_peri_buf 100.00 100.00
u_clk_aon_powerup_buf 100.00 100.00
u_clk_aon_secure_buf 100.00 100.00
u_clk_aon_timers_buf 100.00 100.00
u_clk_io_buf 100.00 100.00
u_clk_io_div2_peri_cg 100.00 100.00 100.00 100.00
u_clk_io_div2_peri_scanmode_sync 100.00 100.00 100.00
u_clk_io_div2_peri_sw_en_sync 100.00 100.00 100.00
u_clk_io_div2_powerup_buf 100.00 100.00
u_clk_io_div4_peri_cg 100.00 100.00 100.00 100.00
u_clk_io_div4_peri_scanmode_sync 100.00 100.00 100.00
u_clk_io_div4_peri_sw_en_sync 100.00 100.00 100.00
u_clk_io_div4_powerup_buf 100.00 100.00
u_clk_io_peri_cg 100.00 100.00 100.00 100.00
u_clk_io_peri_scanmode_sync 100.00 100.00 100.00
u_clk_io_peri_sw_en_sync 100.00 100.00 100.00
u_clk_io_powerup_buf 100.00 100.00
u_clk_main_aes_trans 100.00 100.00 100.00 100.00 100.00 100.00
u_clk_main_buf 100.00 100.00
u_clk_main_hmac_trans 100.00 100.00 100.00 100.00 100.00 100.00
u_clk_main_kmac_trans 100.00 100.00 100.00 100.00 100.00 100.00
u_clk_main_otbn_trans 100.00 100.00 100.00 100.00 100.00 100.00
u_clk_main_powerup_buf 100.00 100.00
u_clk_usb_buf 100.00 100.00
u_clk_usb_peri_cg 100.00 100.00 100.00 100.00
u_clk_usb_peri_scanmode_sync 100.00 100.00 100.00
u_clk_usb_peri_sw_en_sync 100.00 100.00 100.00
u_clk_usb_powerup_buf 100.00 100.00
u_clkmgr_byp 100.00 100.00 100.00 100.00 100.00
u_io_div2_div_scanmode_sync 100.00 100.00 100.00
u_io_div2_meas 95.78 100.00 95.56 100.00 100.00 83.33
u_io_div2_root_ctrl 100.00 100.00 100.00 100.00 100.00
u_io_div4_div_scanmode_sync 100.00 100.00 100.00
u_io_div4_meas 95.78 100.00 95.56 100.00 100.00 83.33
u_io_div4_root_ctrl 100.00 100.00 100.00 100.00 100.00
u_io_meas 95.78 100.00 95.56 100.00 100.00 83.33
u_io_root_ctrl 100.00 100.00 100.00 100.00 100.00
u_io_status 100.00 100.00 100.00
u_io_step_down_req_sync 100.00 100.00 100.00 100.00 100.00
u_main_meas 95.78 100.00 95.56 100.00 100.00 83.33
u_main_root_ctrl 100.00 100.00 100.00 100.00 100.00
u_main_status 100.00 100.00 100.00
u_no_scan_io_div2_div 100.00 100.00 100.00 100.00 100.00
u_no_scan_io_div4_div 100.00 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_div2_infra 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_div2_peri 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_div4_infra 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_div4_peri 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_div4_secure 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_div4_timers 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_infra 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_io_peri 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_main_infra 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_main_secure 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_usb_infra 100.00 100.00 100.00 100.00
u_prim_mubi4_sender_clk_usb_peri 100.00 100.00 100.00 100.00
u_reg 97.64 98.39 95.42 100.00 97.91 96.48
u_usb_meas 95.78 100.00 95.56 100.00 100.00 83.33
u_usb_root_ctrl 100.00 100.00 100.00 100.00 100.00
u_usb_status 100.00 100.00 100.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : clkmgr
Line No.TotalCoveredPercent
TOTAL3434100.00
CONT_ASSIGN26011100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN30911100.00
CONT_ASSIGN31011100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41311100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN41811100.00
CONT_ASSIGN43711100.00
CONT_ASSIGN46211100.00
CONT_ASSIGN47411100.00
CONT_ASSIGN48611100.00
CONT_ASSIGN51111100.00
ALWAYS55255100.00
CONT_ASSIGN69911100.00
CONT_ASSIGN71011100.00
CONT_ASSIGN72111100.00
CONT_ASSIGN73211100.00
CONT_ASSIGN74311100.00
CONT_ASSIGN75411100.00
CONT_ASSIGN76511100.00
CONT_ASSIGN77611100.00
CONT_ASSIGN81911100.00
CONT_ASSIGN86111100.00
CONT_ASSIGN90311100.00
CONT_ASSIGN94511100.00
CONT_ASSIGN106211100.00
CONT_ASSIGN107111100.00


259                     
260        1/1            assign alert_test = {
           Tests:       T4 T5 T6 
261                         reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe,
262                         reg2hw.alert_test.recov_fault.q & reg2hw.alert_test.recov_fault.qe
263                       };
264                     
265                       logic recov_alert;
266        1/1            assign recov_alert =
           Tests:       T2 T3 T36 
267                         hw2reg.recov_err_code.io_measure_err.de |
268                         hw2reg.recov_err_code.io_timeout_err.de |
269                         hw2reg.recov_err_code.io_div2_measure_err.de |
270                         hw2reg.recov_err_code.io_div2_timeout_err.de |
271                         hw2reg.recov_err_code.io_div4_measure_err.de |
272                         hw2reg.recov_err_code.io_div4_timeout_err.de |
273                         hw2reg.recov_err_code.main_measure_err.de |
274                         hw2reg.recov_err_code.main_timeout_err.de |
275                         hw2reg.recov_err_code.usb_measure_err.de |
276                         hw2reg.recov_err_code.usb_timeout_err.de |
277                         hw2reg.recov_err_code.shadow_update_err.de;
278                     
279        1/1            assign alerts = {
           Tests:       T46 T2 T19 
280                         |reg2hw.fatal_err_code,
281                         recov_alert
282                       };
283                     
284                       localparam logic [NumAlerts-1:0] AlertFatal = {1'b1, 1'b0};
285                     
286                       for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
287                         prim_alert_sender #(
288                           .AsyncOn(AlertAsyncOn[i]),
289                           .IsFatal(AlertFatal[i])
290                         ) u_prim_alert_sender (
291                           .clk_i,
292                           .rst_ni,
293                           .alert_test_i  ( alert_test[i] ),
294                           .alert_req_i   ( alerts[i]     ),
295                           .alert_ack_o   (               ),
296                           .alert_state_o (               ),
297                           .alert_rx_i    ( alert_rx_i[i] ),
298                           .alert_tx_o    ( alert_tx_o[i] )
299                         );
300                       end
301                     
302                       ////////////////////////////////////////////////////
303                       // Clock bypass request
304                       ////////////////////////////////////////////////////
305                     
306                       mubi4_t extclk_ctrl_sel;
307                       mubi4_t extclk_ctrl_hi_speed_sel;
308                     
309        1/1            assign extclk_ctrl_sel = mubi4_t'(reg2hw.extclk_ctrl.sel.q);
           Tests:       T4 T30 T31 
310        1/1            assign extclk_ctrl_hi_speed_sel = mubi4_t'(reg2hw.extclk_ctrl.hi_speed_sel.q);
           Tests:       T4 T30 T31 
311                     
312                       clkmgr_byp #(
313                         .NumDivClks(2)
314                       ) u_clkmgr_byp (
315                         .clk_i,
316                         .rst_ni,
317                         .en_i(lc_hw_debug_en_i),
318                         .lc_clk_byp_req_i,
319                         .lc_clk_byp_ack_o,
320                         .byp_req_i(extclk_ctrl_sel),
321                         .byp_ack_o(hw2reg.extclk_status.d),
322                         .hi_speed_sel_i(extclk_ctrl_hi_speed_sel),
323                         .all_clk_byp_req_o,
324                         .all_clk_byp_ack_i,
325                         .io_clk_byp_req_o,
326                         .io_clk_byp_ack_i,
327                         .hi_speed_sel_o,
328                     
329                         // divider step down controls
330                         .step_down_acks_i(step_down_acks)
331                       );
332                     
333                       ////////////////////////////////////////////////////
334                       // Feed through clocks
335                       // Feed through clocks do not actually need to be in clkmgr, as they are
336                       // completely untouched. The only reason they are here is for easier
337                       // bundling management purposes through clocks_o
338                       ////////////////////////////////////////////////////
339                       prim_clock_buf u_clk_io_div4_powerup_buf (
340                         .clk_i(clk_io_div4),
341                         .clk_o(clocks_o.clk_io_div4_powerup)
342                       );
343                     
344                       // clock gated indication for alert handler: these clocks are never gated.
345                       assign cg_en_o.io_div4_powerup = MuBi4False;
346                       prim_clock_buf u_clk_aon_powerup_buf (
347                         .clk_i(clk_aon),
348                         .clk_o(clocks_o.clk_aon_powerup)
349                       );
350                     
351                       // clock gated indication for alert handler: these clocks are never gated.
352                       assign cg_en_o.aon_powerup = MuBi4False;
353                       prim_clock_buf u_clk_main_powerup_buf (
354                         .clk_i(clk_main),
355                         .clk_o(clocks_o.clk_main_powerup)
356                       );
357                     
358                       // clock gated indication for alert handler: these clocks are never gated.
359                       assign cg_en_o.main_powerup = MuBi4False;
360                       prim_clock_buf u_clk_io_powerup_buf (
361                         .clk_i(clk_io),
362                         .clk_o(clocks_o.clk_io_powerup)
363                       );
364                     
365                       // clock gated indication for alert handler: these clocks are never gated.
366                       assign cg_en_o.io_powerup = MuBi4False;
367                       prim_clock_buf u_clk_usb_powerup_buf (
368                         .clk_i(clk_usb),
369                         .clk_o(clocks_o.clk_usb_powerup)
370                       );
371                     
372                       // clock gated indication for alert handler: these clocks are never gated.
373                       assign cg_en_o.usb_powerup = MuBi4False;
374                       prim_clock_buf u_clk_io_div2_powerup_buf (
375                         .clk_i(clk_io_div2),
376                         .clk_o(clocks_o.clk_io_div2_powerup)
377                       );
378                     
379                       // clock gated indication for alert handler: these clocks are never gated.
380                       assign cg_en_o.io_div2_powerup = MuBi4False;
381                       prim_clock_buf u_clk_aon_secure_buf (
382                         .clk_i(clk_aon),
383                         .clk_o(clocks_o.clk_aon_secure)
384                       );
385                     
386                       // clock gated indication for alert handler: these clocks are never gated.
387                       assign cg_en_o.aon_secure = MuBi4False;
388                       prim_clock_buf u_clk_aon_peri_buf (
389                         .clk_i(clk_aon),
390                         .clk_o(clocks_o.clk_aon_peri)
391                       );
392                     
393                       // clock gated indication for alert handler: these clocks are never gated.
394                       assign cg_en_o.aon_peri = MuBi4False;
395                       prim_clock_buf u_clk_aon_timers_buf (
396                         .clk_i(clk_aon),
397                         .clk_o(clocks_o.clk_aon_timers)
398                       );
399                     
400                       // clock gated indication for alert handler: these clocks are never gated.
401                       assign cg_en_o.aon_timers = MuBi4False;
402                     
403                       ////////////////////////////////////////////////////
404                       // Distribute pwrmgr ip_clk_en requests to each family
405                       ////////////////////////////////////////////////////
406                       // clk_main family
407                       logic pwrmgr_main_en;
408        1/1            assign pwrmgr_main_en = pwr_i.main_ip_clk_en;
           Tests:       T28 T47 T21 
409                       // clk_io family
410                       logic pwrmgr_io_en;
411                       logic pwrmgr_io_div2_en;
412                       logic pwrmgr_io_div4_en;
413        1/1            assign pwrmgr_io_en = pwr_i.io_ip_clk_en;
           Tests:       T28 T47 T21 
414        1/1            assign pwrmgr_io_div2_en = pwr_i.io_ip_clk_en;
           Tests:       T28 T47 T21 
415        1/1            assign pwrmgr_io_div4_en = pwr_i.io_ip_clk_en;
           Tests:       T28 T47 T21 
416                       // clk_usb family
417                       logic pwrmgr_usb_en;
418        1/1            assign pwrmgr_usb_en = pwr_i.usb_ip_clk_en;
           Tests:       T28 T47 T21 
419                     
420                       ////////////////////////////////////////////////////
421                       // Root gating
422                       ////////////////////////////////////////////////////
423                     
424                       // clk_main family
425                       logic [0:0] main_ens;
426                     
427                       logic clk_main_en;
428                       logic clk_main_root;
429                       clkmgr_root_ctrl u_main_root_ctrl (
430                         .clk_i(clk_main),
431                         .rst_ni(rst_root_main_ni),
432                         .scanmode_i,
433                         .async_en_i(pwrmgr_main_en),
434                         .en_o(clk_main_en),
435                         .clk_o(clk_main_root)
436                       );
437        1/1            assign main_ens[0] = clk_main_en;
           Tests:       T4 T5 T6 
438                     
439                       // create synchronized status
440                       clkmgr_clk_status #(
441                         .NumClocks(1)
442                       ) u_main_status (
443                         .clk_i,
444                         .rst_ni(rst_root_ni),
445                         .ens_i(main_ens),
446                         .status_o(pwr_o.main_status)
447                       );
448                     
449                       // clk_io family
450                       logic [2:0] io_ens;
451                     
452                       logic clk_io_en;
453                       logic clk_io_root;
454                       clkmgr_root_ctrl u_io_root_ctrl (
455                         .clk_i(clk_io),
456                         .rst_ni(rst_root_io_ni),
457                         .scanmode_i,
458                         .async_en_i(pwrmgr_io_en),
459                         .en_o(clk_io_en),
460                         .clk_o(clk_io_root)
461                       );
462        1/1            assign io_ens[0] = clk_io_en;
           Tests:       T4 T5 T6 
463                     
464                       logic clk_io_div2_en;
465                       logic clk_io_div2_root;
466                       clkmgr_root_ctrl u_io_div2_root_ctrl (
467                         .clk_i(clk_io_div2),
468                         .rst_ni(rst_root_io_div2_ni),
469                         .scanmode_i,
470                         .async_en_i(pwrmgr_io_div2_en),
471                         .en_o(clk_io_div2_en),
472                         .clk_o(clk_io_div2_root)
473                       );
474        1/1            assign io_ens[1] = clk_io_div2_en;
           Tests:       T4 T5 T6 
475                     
476                       logic clk_io_div4_en;
477                       logic clk_io_div4_root;
478                       clkmgr_root_ctrl u_io_div4_root_ctrl (
479                         .clk_i(clk_io_div4),
480                         .rst_ni(rst_root_io_div4_ni),
481                         .scanmode_i,
482                         .async_en_i(pwrmgr_io_div4_en),
483                         .en_o(clk_io_div4_en),
484                         .clk_o(clk_io_div4_root)
485                       );
486        1/1            assign io_ens[2] = clk_io_div4_en;
           Tests:       T4 T5 T6 
487                     
488                       // create synchronized status
489                       clkmgr_clk_status #(
490                         .NumClocks(3)
491                       ) u_io_status (
492                         .clk_i,
493                         .rst_ni(rst_root_ni),
494                         .ens_i(io_ens),
495                         .status_o(pwr_o.io_status)
496                       );
497                     
498                       // clk_usb family
499                       logic [0:0] usb_ens;
500                     
501                       logic clk_usb_en;
502                       logic clk_usb_root;
503                       clkmgr_root_ctrl u_usb_root_ctrl (
504                         .clk_i(clk_usb),
505                         .rst_ni(rst_root_usb_ni),
506                         .scanmode_i,
507                         .async_en_i(pwrmgr_usb_en),
508                         .en_o(clk_usb_en),
509                         .clk_o(clk_usb_root)
510                       );
511        1/1            assign usb_ens[0] = clk_usb_en;
           Tests:       T4 T5 T6 
512                     
513                       // create synchronized status
514                       clkmgr_clk_status #(
515                         .NumClocks(1)
516                       ) u_usb_status (
517                         .clk_i,
518                         .rst_ni(rst_root_ni),
519                         .ens_i(usb_ens),
520                         .status_o(pwr_o.usb_status)
521                       );
522                     
523                       ////////////////////////////////////////////////////
524                       // Clock Measurement for the roots
525                       // SEC_CM: TIMEOUT.CLK.BKGN_CHK, MEAS.CLK.BKGN_CHK
526                       ////////////////////////////////////////////////////
527                     
528                       typedef enum logic [2:0] {
529                         BaseIdx,
530                         ClkIoIdx,
531                         ClkIoDiv2Idx,
532                         ClkIoDiv4Idx,
533                         ClkMainIdx,
534                         ClkUsbIdx,
535                         CalibRdyLastIdx
536                       } clkmgr_calib_idx_e;
537                     
538                       // if clocks become uncalibrated, allow the measurement control configurations to change
539                       mubi4_t [CalibRdyLastIdx-1:0] calib_rdy;
540                       prim_mubi4_sync #(
541                         .AsyncOn(1),
542                         .NumCopies(int'(CalibRdyLastIdx)),
543                         .ResetValue(MuBi4False)
544                       ) u_calib_rdy_sync (
545                         .clk_i,
546                         .rst_ni,
547                         .mubi_i(calib_rdy_i),
548                         .mubi_o({calib_rdy})
549                       );
550                     
551                       always_comb begin
552        1/1              hw2reg.measure_ctrl_regwen.de = '0;
           Tests:       T4 T5 T6 
553        1/1              hw2reg.measure_ctrl_regwen.d = reg2hw.measure_ctrl_regwen;
           Tests:       T4 T5 T6 
554                     
555        1/1              if (mubi4_test_false_strict(calib_rdy[BaseIdx])) begin
           Tests:       T4 T5 T6 
556        1/1                hw2reg.measure_ctrl_regwen.de = 1'b1;
           Tests:       T46 T1 T2 
557        1/1                hw2reg.measure_ctrl_regwen.d = 1'b1;
           Tests:       T46 T1 T2 
558                         end
                        MISSING_ELSE
559                       end
560                     
561                       clkmgr_meas_chk #(
562                         .Cnt(960),
563                         .RefCnt(1)
564                       ) u_io_meas (
565                         .clk_i,
566                         .rst_ni,
567                         .clk_src_i(clk_io),
568                         .rst_src_ni(rst_io_ni),
569                         .clk_ref_i(clk_aon),
570                         .rst_ref_ni(rst_aon_ni),
571                         // signals on source domain
572                         .src_en_i(clk_io_en & mubi4_test_true_loose(mubi4_t'(reg2hw.io_meas_ctrl_en))),
573                         .src_max_cnt_i(reg2hw.io_meas_ctrl_shadowed.hi.q),
574                         .src_min_cnt_i(reg2hw.io_meas_ctrl_shadowed.lo.q),
575                         .src_cfg_meas_en_i(mubi4_t'(reg2hw.io_meas_ctrl_en.q)),
576                         .src_cfg_meas_en_valid_o(hw2reg.io_meas_ctrl_en.de),
577                         .src_cfg_meas_en_o(hw2reg.io_meas_ctrl_en.d),
578                         // signals on local clock domain
579                         .calib_rdy_i(calib_rdy[ClkIoIdx]),
580                         .meas_err_o(hw2reg.recov_err_code.io_measure_err.de),
581                         .timeout_err_o(hw2reg.recov_err_code.io_timeout_err.de)
582                       );
583                     
584                       assign hw2reg.recov_err_code.io_measure_err.d = 1'b1;
585                       assign hw2reg.recov_err_code.io_timeout_err.d = 1'b1;
586                     
587                     
588                       clkmgr_meas_chk #(
589                         .Cnt(480),
590                         .RefCnt(1)
591                       ) u_io_div2_meas (
592                         .clk_i,
593                         .rst_ni,
594                         .clk_src_i(clk_io_div2),
595                         .rst_src_ni(rst_io_div2_ni),
596                         .clk_ref_i(clk_aon),
597                         .rst_ref_ni(rst_aon_ni),
598                         // signals on source domain
599                         .src_en_i(clk_io_div2_en & mubi4_test_true_loose(mubi4_t'(reg2hw.io_div2_meas_ctrl_en))),
600                         .src_max_cnt_i(reg2hw.io_div2_meas_ctrl_shadowed.hi.q),
601                         .src_min_cnt_i(reg2hw.io_div2_meas_ctrl_shadowed.lo.q),
602                         .src_cfg_meas_en_i(mubi4_t'(reg2hw.io_div2_meas_ctrl_en.q)),
603                         .src_cfg_meas_en_valid_o(hw2reg.io_div2_meas_ctrl_en.de),
604                         .src_cfg_meas_en_o(hw2reg.io_div2_meas_ctrl_en.d),
605                         // signals on local clock domain
606                         .calib_rdy_i(calib_rdy[ClkIoDiv2Idx]),
607                         .meas_err_o(hw2reg.recov_err_code.io_div2_measure_err.de),
608                         .timeout_err_o(hw2reg.recov_err_code.io_div2_timeout_err.de)
609                       );
610                     
611                       assign hw2reg.recov_err_code.io_div2_measure_err.d = 1'b1;
612                       assign hw2reg.recov_err_code.io_div2_timeout_err.d = 1'b1;
613                     
614                     
615                       clkmgr_meas_chk #(
616                         .Cnt(240),
617                         .RefCnt(1)
618                       ) u_io_div4_meas (
619                         .clk_i,
620                         .rst_ni,
621                         .clk_src_i(clk_io_div4),
622                         .rst_src_ni(rst_io_div4_ni),
623                         .clk_ref_i(clk_aon),
624                         .rst_ref_ni(rst_aon_ni),
625                         // signals on source domain
626                         .src_en_i(clk_io_div4_en & mubi4_test_true_loose(mubi4_t'(reg2hw.io_div4_meas_ctrl_en))),
627                         .src_max_cnt_i(reg2hw.io_div4_meas_ctrl_shadowed.hi.q),
628                         .src_min_cnt_i(reg2hw.io_div4_meas_ctrl_shadowed.lo.q),
629                         .src_cfg_meas_en_i(mubi4_t'(reg2hw.io_div4_meas_ctrl_en.q)),
630                         .src_cfg_meas_en_valid_o(hw2reg.io_div4_meas_ctrl_en.de),
631                         .src_cfg_meas_en_o(hw2reg.io_div4_meas_ctrl_en.d),
632                         // signals on local clock domain
633                         .calib_rdy_i(calib_rdy[ClkIoDiv4Idx]),
634                         .meas_err_o(hw2reg.recov_err_code.io_div4_measure_err.de),
635                         .timeout_err_o(hw2reg.recov_err_code.io_div4_timeout_err.de)
636                       );
637                     
638                       assign hw2reg.recov_err_code.io_div4_measure_err.d = 1'b1;
639                       assign hw2reg.recov_err_code.io_div4_timeout_err.d = 1'b1;
640                     
641                     
642                       clkmgr_meas_chk #(
643                         .Cnt(1000),
644                         .RefCnt(1)
645                       ) u_main_meas (
646                         .clk_i,
647                         .rst_ni,
648                         .clk_src_i(clk_main),
649                         .rst_src_ni(rst_main_ni),
650                         .clk_ref_i(clk_aon),
651                         .rst_ref_ni(rst_aon_ni),
652                         // signals on source domain
653                         .src_en_i(clk_main_en & mubi4_test_true_loose(mubi4_t'(reg2hw.main_meas_ctrl_en))),
654                         .src_max_cnt_i(reg2hw.main_meas_ctrl_shadowed.hi.q),
655                         .src_min_cnt_i(reg2hw.main_meas_ctrl_shadowed.lo.q),
656                         .src_cfg_meas_en_i(mubi4_t'(reg2hw.main_meas_ctrl_en.q)),
657                         .src_cfg_meas_en_valid_o(hw2reg.main_meas_ctrl_en.de),
658                         .src_cfg_meas_en_o(hw2reg.main_meas_ctrl_en.d),
659                         // signals on local clock domain
660                         .calib_rdy_i(calib_rdy[ClkMainIdx]),
661                         .meas_err_o(hw2reg.recov_err_code.main_measure_err.de),
662                         .timeout_err_o(hw2reg.recov_err_code.main_timeout_err.de)
663                       );
664                     
665                       assign hw2reg.recov_err_code.main_measure_err.d = 1'b1;
666                       assign hw2reg.recov_err_code.main_timeout_err.d = 1'b1;
667                     
668                     
669                       clkmgr_meas_chk #(
670                         .Cnt(480),
671                         .RefCnt(1)
672                       ) u_usb_meas (
673                         .clk_i,
674                         .rst_ni,
675                         .clk_src_i(clk_usb),
676                         .rst_src_ni(rst_usb_ni),
677                         .clk_ref_i(clk_aon),
678                         .rst_ref_ni(rst_aon_ni),
679                         // signals on source domain
680                         .src_en_i(clk_usb_en & mubi4_test_true_loose(mubi4_t'(reg2hw.usb_meas_ctrl_en))),
681                         .src_max_cnt_i(reg2hw.usb_meas_ctrl_shadowed.hi.q),
682                         .src_min_cnt_i(reg2hw.usb_meas_ctrl_shadowed.lo.q),
683                         .src_cfg_meas_en_i(mubi4_t'(reg2hw.usb_meas_ctrl_en.q)),
684                         .src_cfg_meas_en_valid_o(hw2reg.usb_meas_ctrl_en.de),
685                         .src_cfg_meas_en_o(hw2reg.usb_meas_ctrl_en.d),
686                         // signals on local clock domain
687                         .calib_rdy_i(calib_rdy[ClkUsbIdx]),
688                         .meas_err_o(hw2reg.recov_err_code.usb_measure_err.de),
689                         .timeout_err_o(hw2reg.recov_err_code.usb_timeout_err.de)
690                       );
691                     
692                       assign hw2reg.recov_err_code.usb_measure_err.d = 1'b1;
693                       assign hw2reg.recov_err_code.usb_timeout_err.d = 1'b1;
694                     
695                     
696                       ////////////////////////////////////////////////////
697                       // Clocks with only root gate
698                       ////////////////////////////////////////////////////
699        1/1            assign clocks_o.clk_io_div4_infra = clk_io_div4_root;
           Tests:       T4 T5 T6 
700                     
701                       // clock gated indication for alert handler
702                       prim_mubi4_sender #(
703                         .ResetValue(MuBi4True)
704                       ) u_prim_mubi4_sender_clk_io_div4_infra (
705                         .clk_i(clk_io_div4),
706                         .rst_ni(rst_io_div4_ni),
707                         .mubi_i(((clk_io_div4_en) ? MuBi4False : MuBi4True)),
708                         .mubi_o(cg_en_o.io_div4_infra)
709                       );
710        1/1            assign clocks_o.clk_main_infra = clk_main_root;
           Tests:       T4 T5 T6 
711                     
712                       // clock gated indication for alert handler
713                       prim_mubi4_sender #(
714                         .ResetValue(MuBi4True)
715                       ) u_prim_mubi4_sender_clk_main_infra (
716                         .clk_i(clk_main),
717                         .rst_ni(rst_main_ni),
718                         .mubi_i(((clk_main_en) ? MuBi4False : MuBi4True)),
719                         .mubi_o(cg_en_o.main_infra)
720                       );
721        1/1            assign clocks_o.clk_usb_infra = clk_usb_root;
           Tests:       T4 T5 T6 
722                     
723                       // clock gated indication for alert handler
724                       prim_mubi4_sender #(
725                         .ResetValue(MuBi4True)
726                       ) u_prim_mubi4_sender_clk_usb_infra (
727                         .clk_i(clk_usb),
728                         .rst_ni(rst_usb_ni),
729                         .mubi_i(((clk_usb_en) ? MuBi4False : MuBi4True)),
730                         .mubi_o(cg_en_o.usb_infra)
731                       );
732        1/1            assign clocks_o.clk_io_infra = clk_io_root;
           Tests:       T4 T5 T6 
733                     
734                       // clock gated indication for alert handler
735                       prim_mubi4_sender #(
736                         .ResetValue(MuBi4True)
737                       ) u_prim_mubi4_sender_clk_io_infra (
738                         .clk_i(clk_io),
739                         .rst_ni(rst_io_ni),
740                         .mubi_i(((clk_io_en) ? MuBi4False : MuBi4True)),
741                         .mubi_o(cg_en_o.io_infra)
742                       );
743        1/1            assign clocks_o.clk_io_div2_infra = clk_io_div2_root;
           Tests:       T4 T5 T6 
744                     
745                       // clock gated indication for alert handler
746                       prim_mubi4_sender #(
747                         .ResetValue(MuBi4True)
748                       ) u_prim_mubi4_sender_clk_io_div2_infra (
749                         .clk_i(clk_io_div2),
750                         .rst_ni(rst_io_div2_ni),
751                         .mubi_i(((clk_io_div2_en) ? MuBi4False : MuBi4True)),
752                         .mubi_o(cg_en_o.io_div2_infra)
753                       );
754        1/1            assign clocks_o.clk_io_div4_secure = clk_io_div4_root;
           Tests:       T4 T5 T6 
755                     
756                       // clock gated indication for alert handler
757                       prim_mubi4_sender #(
758                         .ResetValue(MuBi4True)
759                       ) u_prim_mubi4_sender_clk_io_div4_secure (
760                         .clk_i(clk_io_div4),
761                         .rst_ni(rst_io_div4_ni),
762                         .mubi_i(((clk_io_div4_en) ? MuBi4False : MuBi4True)),
763                         .mubi_o(cg_en_o.io_div4_secure)
764                       );
765        1/1            assign clocks_o.clk_main_secure = clk_main_root;
           Tests:       T4 T5 T6 
766                     
767                       // clock gated indication for alert handler
768                       prim_mubi4_sender #(
769                         .ResetValue(MuBi4True)
770                       ) u_prim_mubi4_sender_clk_main_secure (
771                         .clk_i(clk_main),
772                         .rst_ni(rst_main_ni),
773                         .mubi_i(((clk_main_en) ? MuBi4False : MuBi4True)),
774                         .mubi_o(cg_en_o.main_secure)
775                       );
776        1/1            assign clocks_o.clk_io_div4_timers = clk_io_div4_root;
           Tests:       T4 T5 T6 
777                     
778                       // clock gated indication for alert handler
779                       prim_mubi4_sender #(
780                         .ResetValue(MuBi4True)
781                       ) u_prim_mubi4_sender_clk_io_div4_timers (
782                         .clk_i(clk_io_div4),
783                         .rst_ni(rst_io_div4_ni),
784                         .mubi_i(((clk_io_div4_en) ? MuBi4False : MuBi4True)),
785                         .mubi_o(cg_en_o.io_div4_timers)
786                       );
787                     
788                       ////////////////////////////////////////////////////
789                       // Software direct control group
790                       ////////////////////////////////////////////////////
791                     
792                       logic clk_io_div4_peri_sw_en;
793                       logic clk_io_div2_peri_sw_en;
794                       logic clk_io_peri_sw_en;
795                       logic clk_usb_peri_sw_en;
796                     
797                       prim_flop_2sync #(
798                         .Width(1)
799                       ) u_clk_io_div4_peri_sw_en_sync (
800                         .clk_i(clk_io_div4),
801                         .rst_ni(rst_io_div4_ni),
802                         .d_i(reg2hw.clk_enables.clk_io_div4_peri_en.q),
803                         .q_o(clk_io_div4_peri_sw_en)
804                       );
805                     
806                       // Declared as size 1 packed array to avoid FPV warning.
807                       prim_mubi_pkg::mubi4_t [0:0] clk_io_div4_peri_scanmode;
808                       prim_mubi4_sync #(
809                         .NumCopies(1),
810                         .AsyncOn(0)
811                       ) u_clk_io_div4_peri_scanmode_sync  (
812                         .clk_i,
813                         .rst_ni,
814                         .mubi_i(scanmode_i),
815                         .mubi_o(clk_io_div4_peri_scanmode)
816                       );
817                     
818                       logic clk_io_div4_peri_combined_en;
819        1/1            assign clk_io_div4_peri_combined_en = clk_io_div4_peri_sw_en & clk_io_div4_en;
           Tests:       T4 T5 T6 
820                       prim_clock_gating #(
821                         .FpgaBufGlobal(1'b1) // This clock spans across multiple clock regions.
822                       ) u_clk_io_div4_peri_cg (
823                         .clk_i(clk_io_div4),
824                         .en_i(clk_io_div4_peri_combined_en),
825                         .test_en_i(mubi4_test_true_strict(clk_io_div4_peri_scanmode[0])),
826                         .clk_o(clocks_o.clk_io_div4_peri)
827                       );
828                     
829                       // clock gated indication for alert handler
830                       prim_mubi4_sender #(
831                         .ResetValue(MuBi4True)
832                       ) u_prim_mubi4_sender_clk_io_div4_peri (
833                         .clk_i(clk_io_div4),
834                         .rst_ni(rst_io_div4_ni),
835                         .mubi_i(((clk_io_div4_peri_combined_en) ? MuBi4False : MuBi4True)),
836                         .mubi_o(cg_en_o.io_div4_peri)
837                       );
838                     
839                       prim_flop_2sync #(
840                         .Width(1)
841                       ) u_clk_io_div2_peri_sw_en_sync (
842                         .clk_i(clk_io_div2),
843                         .rst_ni(rst_io_div2_ni),
844                         .d_i(reg2hw.clk_enables.clk_io_div2_peri_en.q),
845                         .q_o(clk_io_div2_peri_sw_en)
846                       );
847                     
848                       // Declared as size 1 packed array to avoid FPV warning.
849                       prim_mubi_pkg::mubi4_t [0:0] clk_io_div2_peri_scanmode;
850                       prim_mubi4_sync #(
851                         .NumCopies(1),
852                         .AsyncOn(0)
853                       ) u_clk_io_div2_peri_scanmode_sync  (
854                         .clk_i,
855                         .rst_ni,
856                         .mubi_i(scanmode_i),
857                         .mubi_o(clk_io_div2_peri_scanmode)
858                       );
859                     
860                       logic clk_io_div2_peri_combined_en;
861        1/1            assign clk_io_div2_peri_combined_en = clk_io_div2_peri_sw_en & clk_io_div2_en;
           Tests:       T4 T5 T6 
862                       prim_clock_gating #(
863                         .FpgaBufGlobal(1'b1) // This clock spans across multiple clock regions.
864                       ) u_clk_io_div2_peri_cg (
865                         .clk_i(clk_io_div2),
866                         .en_i(clk_io_div2_peri_combined_en),
867                         .test_en_i(mubi4_test_true_strict(clk_io_div2_peri_scanmode[0])),
868                         .clk_o(clocks_o.clk_io_div2_peri)
869                       );
870                     
871                       // clock gated indication for alert handler
872                       prim_mubi4_sender #(
873                         .ResetValue(MuBi4True)
874                       ) u_prim_mubi4_sender_clk_io_div2_peri (
875                         .clk_i(clk_io_div2),
876                         .rst_ni(rst_io_div2_ni),
877                         .mubi_i(((clk_io_div2_peri_combined_en) ? MuBi4False : MuBi4True)),
878                         .mubi_o(cg_en_o.io_div2_peri)
879                       );
880                     
881                       prim_flop_2sync #(
882                         .Width(1)
883                       ) u_clk_io_peri_sw_en_sync (
884                         .clk_i(clk_io),
885                         .rst_ni(rst_io_ni),
886                         .d_i(reg2hw.clk_enables.clk_io_peri_en.q),
887                         .q_o(clk_io_peri_sw_en)
888                       );
889                     
890                       // Declared as size 1 packed array to avoid FPV warning.
891                       prim_mubi_pkg::mubi4_t [0:0] clk_io_peri_scanmode;
892                       prim_mubi4_sync #(
893                         .NumCopies(1),
894                         .AsyncOn(0)
895                       ) u_clk_io_peri_scanmode_sync  (
896                         .clk_i,
897                         .rst_ni,
898                         .mubi_i(scanmode_i),
899                         .mubi_o(clk_io_peri_scanmode)
900                       );
901                     
902                       logic clk_io_peri_combined_en;
903        1/1            assign clk_io_peri_combined_en = clk_io_peri_sw_en & clk_io_en;
           Tests:       T4 T5 T6 
904                       prim_clock_gating #(
905                         .FpgaBufGlobal(1'b1) // This clock spans across multiple clock regions.
906                       ) u_clk_io_peri_cg (
907                         .clk_i(clk_io),
908                         .en_i(clk_io_peri_combined_en),
909                         .test_en_i(mubi4_test_true_strict(clk_io_peri_scanmode[0])),
910                         .clk_o(clocks_o.clk_io_peri)
911                       );
912                     
913                       // clock gated indication for alert handler
914                       prim_mubi4_sender #(
915                         .ResetValue(MuBi4True)
916                       ) u_prim_mubi4_sender_clk_io_peri (
917                         .clk_i(clk_io),
918                         .rst_ni(rst_io_ni),
919                         .mubi_i(((clk_io_peri_combined_en) ? MuBi4False : MuBi4True)),
920                         .mubi_o(cg_en_o.io_peri)
921                       );
922                     
923                       prim_flop_2sync #(
924                         .Width(1)
925                       ) u_clk_usb_peri_sw_en_sync (
926                         .clk_i(clk_usb),
927                         .rst_ni(rst_usb_ni),
928                         .d_i(reg2hw.clk_enables.clk_usb_peri_en.q),
929                         .q_o(clk_usb_peri_sw_en)
930                       );
931                     
932                       // Declared as size 1 packed array to avoid FPV warning.
933                       prim_mubi_pkg::mubi4_t [0:0] clk_usb_peri_scanmode;
934                       prim_mubi4_sync #(
935                         .NumCopies(1),
936                         .AsyncOn(0)
937                       ) u_clk_usb_peri_scanmode_sync  (
938                         .clk_i,
939                         .rst_ni,
940                         .mubi_i(scanmode_i),
941                         .mubi_o(clk_usb_peri_scanmode)
942                       );
943                     
944                       logic clk_usb_peri_combined_en;
945        1/1            assign clk_usb_peri_combined_en = clk_usb_peri_sw_en & clk_usb_en;
           Tests:       T4 T5 T6 
946                       prim_clock_gating #(
947                         .FpgaBufGlobal(1'b1) // This clock spans across multiple clock regions.
948                       ) u_clk_usb_peri_cg (
949                         .clk_i(clk_usb),
950                         .en_i(clk_usb_peri_combined_en),
951                         .test_en_i(mubi4_test_true_strict(clk_usb_peri_scanmode[0])),
952                         .clk_o(clocks_o.clk_usb_peri)
953                       );
954                     
955                       // clock gated indication for alert handler
956                       prim_mubi4_sender #(
957                         .ResetValue(MuBi4True)
958                       ) u_prim_mubi4_sender_clk_usb_peri (
959                         .clk_i(clk_usb),
960                         .rst_ni(rst_usb_ni),
961                         .mubi_i(((clk_usb_peri_combined_en) ? MuBi4False : MuBi4True)),
962                         .mubi_o(cg_en_o.usb_peri)
963                       );
964                     
965                     
966                       ////////////////////////////////////////////////////
967                       // Software hint group
968                       // The idle hint feedback is assumed to be synchronous to the
969                       // clock target
970                       ////////////////////////////////////////////////////
971                     
972                       logic [3:0] idle_cnt_err;
973                     
974                       clkmgr_trans #(
975                         .FpgaBufGlobal(1'b0) // This clock is used primarily locally.
976                       ) u_clk_main_aes_trans (
977                         .clk_i(clk_main),
978                         .clk_gated_i(clk_main_root),
979                         .rst_ni(rst_main_ni),
980                         .en_i(clk_main_en),
981                         .idle_i(idle_i[HintMainAes]),
982                         .sw_hint_i(reg2hw.clk_hints.clk_main_aes_hint.q),
983                         .scanmode_i,
984                         .alert_cg_en_o(cg_en_o.main_aes),
985                         .clk_o(clocks_o.clk_main_aes),
986                         .clk_reg_i(clk_i),
987                         .rst_reg_ni(rst_ni),
988                         .reg_en_o(hw2reg.clk_hints_status.clk_main_aes_val.d),
989                         .reg_cnt_err_o(idle_cnt_err[HintMainAes])
990                       );
991                       `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(
992                         ClkMainAesCountCheck_A,
993                         u_clk_main_aes_trans.u_idle_cnt,
994                         alert_tx_o[1])
995                     
996                       clkmgr_trans #(
997                         .FpgaBufGlobal(1'b0) // This clock is used primarily locally.
998                       ) u_clk_main_hmac_trans (
999                         .clk_i(clk_main),
1000                        .clk_gated_i(clk_main_root),
1001                        .rst_ni(rst_main_ni),
1002                        .en_i(clk_main_en),
1003                        .idle_i(idle_i[HintMainHmac]),
1004                        .sw_hint_i(reg2hw.clk_hints.clk_main_hmac_hint.q),
1005                        .scanmode_i,
1006                        .alert_cg_en_o(cg_en_o.main_hmac),
1007                        .clk_o(clocks_o.clk_main_hmac),
1008                        .clk_reg_i(clk_i),
1009                        .rst_reg_ni(rst_ni),
1010                        .reg_en_o(hw2reg.clk_hints_status.clk_main_hmac_val.d),
1011                        .reg_cnt_err_o(idle_cnt_err[HintMainHmac])
1012                      );
1013                      `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(
1014                        ClkMainHmacCountCheck_A,
1015                        u_clk_main_hmac_trans.u_idle_cnt,
1016                        alert_tx_o[1])
1017                    
1018                      clkmgr_trans #(
1019                        .FpgaBufGlobal(1'b1) // KMAC is getting too big for a single clock region.
1020                      ) u_clk_main_kmac_trans (
1021                        .clk_i(clk_main),
1022                        .clk_gated_i(clk_main_root),
1023                        .rst_ni(rst_main_ni),
1024                        .en_i(clk_main_en),
1025                        .idle_i(idle_i[HintMainKmac]),
1026                        .sw_hint_i(reg2hw.clk_hints.clk_main_kmac_hint.q),
1027                        .scanmode_i,
1028                        .alert_cg_en_o(cg_en_o.main_kmac),
1029                        .clk_o(clocks_o.clk_main_kmac),
1030                        .clk_reg_i(clk_i),
1031                        .rst_reg_ni(rst_ni),
1032                        .reg_en_o(hw2reg.clk_hints_status.clk_main_kmac_val.d),
1033                        .reg_cnt_err_o(idle_cnt_err[HintMainKmac])
1034                      );
1035                      `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(
1036                        ClkMainKmacCountCheck_A,
1037                        u_clk_main_kmac_trans.u_idle_cnt,
1038                        alert_tx_o[1])
1039                    
1040                      clkmgr_trans #(
1041                        .FpgaBufGlobal(1'b0) // This clock is used primarily locally.
1042                      ) u_clk_main_otbn_trans (
1043                        .clk_i(clk_main),
1044                        .clk_gated_i(clk_main_root),
1045                        .rst_ni(rst_main_ni),
1046                        .en_i(clk_main_en),
1047                        .idle_i(idle_i[HintMainOtbn]),
1048                        .sw_hint_i(reg2hw.clk_hints.clk_main_otbn_hint.q),
1049                        .scanmode_i,
1050                        .alert_cg_en_o(cg_en_o.main_otbn),
1051                        .clk_o(clocks_o.clk_main_otbn),
1052                        .clk_reg_i(clk_i),
1053                        .rst_reg_ni(rst_ni),
1054                        .reg_en_o(hw2reg.clk_hints_status.clk_main_otbn_val.d),
1055                        .reg_cnt_err_o(idle_cnt_err[HintMainOtbn])
1056                      );
1057                      `ASSERT_PRIM_COUNT_ERROR_TRIGGER_ALERT(
1058                        ClkMainOtbnCountCheck_A,
1059                        u_clk_main_otbn_trans.u_idle_cnt,
1060                        alert_tx_o[1])
1061                      assign hw2reg.fatal_err_code.idle_cnt.d = 1'b1;
1062       1/1            assign hw2reg.fatal_err_code.idle_cnt.de = |idle_cnt_err;
           Tests:       T46 T19 T48 
1063                    
1064                      // state readback
1065                      assign hw2reg.clk_hints_status.clk_main_aes_val.de = 1'b1;
1066                      assign hw2reg.clk_hints_status.clk_main_hmac_val.de = 1'b1;
1067                      assign hw2reg.clk_hints_status.clk_main_kmac_val.de = 1'b1;
1068                      assign hw2reg.clk_hints_status.clk_main_otbn_val.de = 1'b1;
1069                    
1070                      // SEC_CM: JITTER.CONFIG.MUBI
1071       1/1            assign jitter_en_o = mubi4_t'(reg2hw.jitter_enable.q);
           Tests:       T5 T49 T44 
Cond Coverage for Module : clkmgr
TotalCoveredPercent
Conditions14813893.24
Logical14813893.24
Non-Logical00
Event00

 LINE       37
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       46
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       55
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       64
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       74
 EXPRESSION (idle_i[HintMainAes] == MuBi4True)
            -----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       74
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       84
 EXPRESSION (idle_i[HintMainHmac] == MuBi4True)
            -----------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       84
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       94
 EXPRESSION (idle_i[HintMainKmac] == MuBi4True)
            -----------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       94
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       104
 EXPRESSION (idle_i[HintMainOtbn] == MuBi4True)
            -----------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       104
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       128
 EXPRESSION (div_step_down_req_i == MuBi4True)
            -----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T30,T31 

 LINE       128
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       139
 EXPRESSION (div_step_down_req_i == MuBi4True)
            -----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T30,T31 

 LINE       139
 EXPRESSION (scanmode_i == MuBi4True)
            ------------1------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       148
 EXPRESSION (cg_en_o.aon_peri == MuBi4True)
            ---------------1---------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered 

 LINE       152
 EXPRESSION (cg_en_o.aon_powerup == MuBi4True)
            -----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered 

 LINE       156
 EXPRESSION (cg_en_o.aon_secure == MuBi4True)
            ----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered 

 LINE       160
 EXPRESSION (cg_en_o.aon_timers == MuBi4True)
            ----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered 

 LINE       164
 EXPRESSION (cg_en_o.io_div2_powerup == MuBi4True)
            -------------------1------------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered 

 LINE       168
 EXPRESSION (cg_en_o.io_div4_powerup == MuBi4True)
            -------------------1------------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered 

 LINE       172
 EXPRESSION (cg_en_o.io_powerup == MuBi4True)
            ----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered 

 LINE       176
 EXPRESSION (cg_en_o.main_powerup == MuBi4True)
            -----------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered 

 LINE       180
 EXPRESSION (cg_en_o.usb_powerup == MuBi4True)
            -----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1Not Covered 

 LINE       185
 EXPRESSION (cg_en_o.io_div2_infra == MuBi4True)
            ------------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       194
 EXPRESSION (cg_en_o.io_div4_infra == MuBi4True)
            ------------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       203
 EXPRESSION (cg_en_o.io_div4_secure == MuBi4True)
            ------------------1------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       212
 EXPRESSION (cg_en_o.io_div4_timers == MuBi4True)
            ------------------1------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       221
 EXPRESSION (cg_en_o.io_infra == MuBi4True)
            ---------------1---------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       230
 EXPRESSION (cg_en_o.main_infra == MuBi4True)
            ----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       239
 EXPRESSION (cg_en_o.main_secure == MuBi4True)
            -----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       248
 EXPRESSION (cg_en_o.usb_infra == MuBi4True)
            ----------------1---------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       258
 EXPRESSION (cg_en_o.io_div4_peri == MuBi4True)
            -----------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       260
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault.q & reg2hw.alert_test.fatal_fault.qe)
                 ---------------1---------------   ----------------2---------------
-1--2-StatusTests
01CoveredT33,T42,T50
10CoveredT4,T5,T6
11CoveredT33,T42,T51 

 LINE       260
 SUB-EXPRESSION (reg2hw.alert_test.recov_fault.q & reg2hw.alert_test.recov_fault.qe)
                 ---------------1---------------   ----------------2---------------
-1--2-StatusTests
01CoveredT33,T42,T50
10CoveredT4,T5,T6
11CoveredT33,T42,T50 

 LINE       266
 EXPRESSION 
 Number  Term
      1  hw2reg.recov_err_code.io_measure_err.de | 
      2  hw2reg.recov_err_code.io_timeout_err.de | 
      3  hw2reg.recov_err_code.io_div2_measure_err.de | 
      4  hw2reg.recov_err_code.io_div2_timeout_err.de | 
      5  hw2reg.recov_err_code.io_div4_measure_err.de | 
      6  hw2reg.recov_err_code.io_div4_timeout_err.de | 
      7  hw2reg.recov_err_code.main_measure_err.de | 
      8  hw2reg.recov_err_code.main_timeout_err.de | 
      9  hw2reg.recov_err_code.usb_measure_err.de | 
     10  hw2reg.recov_err_code.usb_timeout_err.de | 
     11  hw2reg.recov_err_code.shadow_update_err.de)
-1--2--3--4--5--6--7--8--9--10--11-StatusTests
00000000000CoveredT4,T5,T6
00000000001Not Covered
00000000010CoveredT3,T41,T13
00000000100CoveredT2,T9,T12
00000001000CoveredT3,T36,T37
00000010000CoveredT2,T9,T10
00000100000CoveredT39,T41,T13
00001000000CoveredT2,T9,T10
00010000000CoveredT52
00100000000CoveredT2,T9,T10
01000000000CoveredT52
10000000000CoveredT2,T9,T10 

 LINE       267
 EXPRESSION (cg_en_o.io_div2_peri == MuBi4True)
            -----------------1-----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       276
 EXPRESSION (cg_en_o.io_peri == MuBi4True)
            ---------------1--------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       285
 EXPRESSION (cg_en_o.usb_peri == MuBi4True)
            ---------------1---------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       295
 EXPRESSION (clkmgr.u_clk_main_aes_trans.sw_hint_synced || ((!clkmgr.u_clk_main_aes_trans.idle_valid)))
             ---------------------1--------------------    ---------------------2---------------------
-1--2-StatusTests
00CoveredT5,T27,T29
01CoveredT4,T5,T6
10CoveredT4,T5,T6 

 LINE       295
 EXPRESSION (cg_en_o.main_aes == MuBi4True)
            ---------------1---------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       304
 EXPRESSION (clkmgr.u_clk_main_hmac_trans.sw_hint_synced || ((!clkmgr.u_clk_main_hmac_trans.idle_valid)))
             ---------------------1---------------------    ----------------------2---------------------
-1--2-StatusTests
00CoveredT5,T27,T29
01CoveredT4,T5,T6
10CoveredT4,T5,T6 

 LINE       304
 EXPRESSION (cg_en_o.main_hmac == MuBi4True)
            ----------------1---------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       313
 EXPRESSION (clkmgr.u_clk_main_kmac_trans.sw_hint_synced || ((!clkmgr.u_clk_main_kmac_trans.idle_valid)))
             ---------------------1---------------------    ----------------------2---------------------
-1--2-StatusTests
00CoveredT5,T29,T49
01CoveredT4,T5,T6
10CoveredT4,T5,T6 

 LINE       313
 EXPRESSION (cg_en_o.main_kmac == MuBi4True)
            ----------------1---------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       322
 EXPRESSION (clkmgr.u_clk_main_otbn_trans.sw_hint_synced || ((!clkmgr.u_clk_main_otbn_trans.idle_valid)))
             ---------------------1---------------------    ----------------------2---------------------
-1--2-StatusTests
00CoveredT5,T27,T29
01CoveredT4,T5,T6
10CoveredT4,T5,T6 

 LINE       322
 EXPRESSION (cg_en_o.main_otbn == MuBi4True)
            ----------------1---------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       704
 EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       715
 EXPRESSION (clk_main_en ? MuBi4False : MuBi4True)
             -----1-----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       726
 EXPRESSION (clk_usb_en ? MuBi4False : MuBi4True)
             -----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       737
 EXPRESSION (clk_io_en ? MuBi4False : MuBi4True)
             ----1----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       748
 EXPRESSION (clk_io_div2_en ? MuBi4False : MuBi4True)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       759
 EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       770
 EXPRESSION (clk_main_en ? MuBi4False : MuBi4True)
             -----1-----
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       781
 EXPRESSION (clk_io_div4_en ? MuBi4False : MuBi4True)
             -------1------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       819
 EXPRESSION (clk_io_div4_peri_sw_en & clk_io_div4_en)
             -----------1----------   -------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT28,T47,T21
11CoveredT4,T5,T6 

 LINE       832
 EXPRESSION (clk_io_div4_peri_combined_en ? MuBi4False : MuBi4True)
             --------------1-------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       861
 EXPRESSION (clk_io_div2_peri_sw_en & clk_io_div2_en)
             -----------1----------   -------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT28,T47,T21
11CoveredT4,T5,T6 

 LINE       874
 EXPRESSION (clk_io_div2_peri_combined_en ? MuBi4False : MuBi4True)
             --------------1-------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       903
 EXPRESSION (clk_io_peri_sw_en & clk_io_en)
             --------1--------   ----2----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT28,T47,T21
11CoveredT4,T5,T6 

 LINE       916
 EXPRESSION (clk_io_peri_combined_en ? MuBi4False : MuBi4True)
             -----------1-----------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       945
 EXPRESSION (clk_usb_peri_sw_en & clk_usb_en)
             ---------1--------   -----2----
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT28,T47,T21
11CoveredT4,T5,T6 

 LINE       958
 EXPRESSION (clk_usb_peri_combined_en ? MuBi4False : MuBi4True)
             ------------1-----------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6
Toggle Coverage for Module : clkmgr
TotalCoveredPercent
Totals 106 106 100.00
Total Bits 660 660 100.00
Total Bits 0->1 330 330 100.00
Total Bits 1->0 330 330 100.00

Ports 106 106 100.00
Port Bits 660 660 100.00
Port Bits 0->1 330 330 100.00
Port Bits 1->0 330 330 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_ni Yes Yes T46,T1,T19 Yes T4,T5,T6 INPUT
rst_shadowed_ni Yes Yes T46,T1,T19 Yes T4,T5,T6 INPUT
clk_main_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_main_ni Yes Yes T46,T1,T19 Yes T4,T5,T6 INPUT
clk_io_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_io_ni Yes Yes T46,T1,T19 Yes T4,T5,T6 INPUT
clk_usb_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_usb_ni Yes Yes T46,T1,T19 Yes T4,T5,T6 INPUT
clk_aon_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
rst_aon_ni Yes Yes T46,T1,T19 Yes T4,T5,T6 INPUT
rst_io_div2_ni Yes Yes T46,T1,T19 Yes T4,T5,T6 INPUT
rst_io_div4_ni Yes Yes T46,T1,T19 Yes T4,T5,T6 INPUT
rst_root_ni Yes Yes T46,T1,T19 Yes T4,T5,T6 INPUT
rst_root_main_ni Yes Yes T46,T1,T19 Yes T4,T5,T6 INPUT
rst_root_io_ni Yes Yes T46,T1,T19 Yes T4,T5,T6 INPUT
rst_root_io_div2_ni Yes Yes T46,T1,T19 Yes T4,T5,T6 INPUT
rst_root_io_div4_ni Yes Yes T46,T1,T19 Yes T4,T5,T6 INPUT
rst_root_usb_ni Yes Yes T46,T1,T19 Yes T4,T5,T6 INPUT
tl_i.d_ready Yes Yes T4,T6,T27 Yes T4,T5,T6 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_mask[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_address[31:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_source[7:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_size[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_i.a_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
tl_o.a_ready Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_error Yes Yes T34,T15,T16 Yes T34,T15,T16 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T4,T5,T27 Yes T4,T5,T27 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T4,*T5,*T6 Yes T4,T5,T6 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T4,T5,T27 Yes T4,T5,T6 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_size[1:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T4,*T5,*T27 Yes T4,T5,T27 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_rx_i[0].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[0].ack_p Yes Yes T33,T42,T2 Yes T33,T42,T2 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
alert_rx_i[1].ack_p Yes Yes T33,T46,T42 Yes T33,T46,T42 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[0].alert_p Yes Yes T33,T42,T2 Yes T33,T42,T2 OUTPUT
alert_tx_o[1].alert_n Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
alert_tx_o[1].alert_p Yes Yes T33,T46,T42 Yes T33,T46,T42 OUTPUT
pwr_i.usb_ip_clk_en Yes Yes T28,T47,T21 Yes T28,T47,T21 INPUT
pwr_i.io_ip_clk_en Yes Yes T28,T47,T21 Yes T28,T47,T21 INPUT
pwr_i.main_ip_clk_en Yes Yes T28,T47,T21 Yes T28,T47,T21 INPUT
pwr_o.usb_status Yes Yes T28,T47,T46 Yes T4,T5,T6 OUTPUT
pwr_o.io_status Yes Yes T28,T47,T46 Yes T4,T5,T6 OUTPUT
pwr_o.main_status Yes Yes T28,T47,T46 Yes T4,T5,T6 OUTPUT
scanmode_i[3:0] Yes Yes T4,T6,T29 Yes T4,T5,T6 INPUT
lc_hw_debug_en_i[3:0] Yes Yes T4,T30,T31 Yes T4,T30,T31 INPUT
lc_clk_byp_req_i[3:0] Yes Yes T4,T30,T31 Yes T4,T30,T31 INPUT
lc_clk_byp_ack_o[3:0] Yes Yes T4,T30,T31 Yes T4,T30,T31 OUTPUT
io_clk_byp_req_o[3:0] Yes Yes T4,T30,T31 Yes T4,T30,T31 OUTPUT
io_clk_byp_ack_i[3:0] Yes Yes T4,T30,T31 Yes T4,T30,T31 INPUT
all_clk_byp_req_o[3:0] Yes Yes T4,T30,T31 Yes T4,T30,T31 OUTPUT
all_clk_byp_ack_i[3:0] Yes Yes T4,T30,T31 Yes T4,T30,T32 INPUT
hi_speed_sel_o[3:0] Yes Yes T4,T30,T31 Yes T4,T5,T6 OUTPUT
calib_rdy_i[3:0] Yes Yes T2,T9,T10 Yes T2,T9,T10 INPUT
jitter_en_o[3:0] Yes Yes T5,T49,T44 Yes T5,T49,T44 OUTPUT
div_step_down_req_i[3:0] Yes Yes T4,T30,T31 Yes T4,T30,T31 INPUT
cg_en_o.usb_peri[3:0] Yes Yes T5,T6,T28 Yes T4,T5,T6 OUTPUT
cg_en_o.io_peri[3:0] Yes Yes T5,T6,T28 Yes T4,T5,T6 OUTPUT
cg_en_o.io_div2_peri[3:0] Yes Yes T5,T6,T28 Yes T4,T5,T6 OUTPUT
cg_en_o.io_div4_peri[3:0] Yes Yes T6,T28,T49 Yes T4,T5,T6 OUTPUT
cg_en_o.io_div4_timers[3:0] Yes Yes T28,T47,T46 Yes T4,T5,T6 OUTPUT
cg_en_o.main_secure[3:0] Yes Yes T28,T47,T46 Yes T4,T5,T6 OUTPUT
cg_en_o.io_div4_secure[3:0] Yes Yes T28,T47,T46 Yes T4,T5,T6 OUTPUT
cg_en_o.io_div2_infra[3:0] Yes Yes T28,T47,T46 Yes T4,T5,T6 OUTPUT
cg_en_o.io_infra[3:0] Yes Yes T28,T47,T46 Yes T4,T5,T6 OUTPUT
cg_en_o.usb_infra[3:0] Yes Yes T28,T47,T46 Yes T4,T5,T6 OUTPUT
cg_en_o.main_infra[3:0] Yes Yes T28,T47,T46 Yes T4,T5,T6 OUTPUT
cg_en_o.io_div4_infra[3:0] Yes Yes T28,T47,T46 Yes T4,T5,T6 OUTPUT
cg_en_o.main_otbn[3:0] Yes Yes T5,T27,T28 Yes T4,T5,T6 OUTPUT
cg_en_o.main_kmac[3:0] Yes Yes T5,T28,T29 Yes T4,T5,T6 OUTPUT
cg_en_o.main_hmac[3:0] Yes Yes T5,T27,T28 Yes T4,T5,T6 OUTPUT
cg_en_o.main_aes[3:0] Yes Yes T5,T27,T28 Yes T4,T5,T6 OUTPUT
cg_en_o.aon_timers[3:0] Unreachable Unreachable Unreachable OUTPUT
cg_en_o.aon_peri[3:0] Unreachable Unreachable Unreachable OUTPUT
cg_en_o.aon_secure[3:0] Unreachable Unreachable Unreachable OUTPUT
cg_en_o.io_div2_powerup[3:0] Unreachable Unreachable Unreachable OUTPUT
cg_en_o.usb_powerup[3:0] Unreachable Unreachable Unreachable OUTPUT
cg_en_o.io_powerup[3:0] Unreachable Unreachable Unreachable OUTPUT
cg_en_o.main_powerup[3:0] Unreachable Unreachable Unreachable OUTPUT
cg_en_o.aon_powerup[3:0] Unreachable Unreachable Unreachable OUTPUT
cg_en_o.io_div4_powerup[3:0] Unreachable Unreachable Unreachable OUTPUT
clocks_o.clk_usb_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_io_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_io_div2_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_io_div4_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_io_div4_timers Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_main_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_io_div4_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_io_div2_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_io_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_usb_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_main_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_io_div4_infra Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_main_otbn Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_main_kmac Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_main_hmac Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_main_aes Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_aon_timers Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_aon_peri Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_aon_secure Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_io_div2_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_usb_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_io_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_main_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_aon_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
clocks_o.clk_io_div4_powerup Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT

*Tests covering at least one bit in the range
Branch Coverage for Module : clkmgr
Line No.TotalCoveredPercent
Branches 26 26 100.00
TERNARY 704 2 2 100.00
TERNARY 715 2 2 100.00
TERNARY 726 2 2 100.00
TERNARY 737 2 2 100.00
TERNARY 748 2 2 100.00
TERNARY 759 2 2 100.00
TERNARY 770 2 2 100.00
TERNARY 781 2 2 100.00
TERNARY 832 2 2 100.00
TERNARY 874 2 2 100.00
TERNARY 916 2 2 100.00
TERNARY 958 2 2 100.00
IF 555 2 2 100.00 



704          ) u_prim_mubi4_sender_clk_io_div4_infra (
                                                      
705            .clk_i(clk_io_div4),
                                   
706            .rst_ni(rst_io_div4_ni),
                                       
707            .mubi_i(((clk_io_div4_en) ? MuBi4False : MuBi4True)),
                                         -1-  
                                         ==>  
                                         ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



715          ) u_prim_mubi4_sender_clk_main_infra (
                                                   
716            .clk_i(clk_main),
                                
717            .rst_ni(rst_main_ni),
                                    
718            .mubi_i(((clk_main_en) ? MuBi4False : MuBi4True)),
                                      -1-  
                                      ==>  
                                      ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



726          ) u_prim_mubi4_sender_clk_usb_infra (
                                                  
727            .clk_i(clk_usb),
                               
728            .rst_ni(rst_usb_ni),
                                   
729            .mubi_i(((clk_usb_en) ? MuBi4False : MuBi4True)),
                                     -1-  
                                     ==>  
                                     ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



737          ) u_prim_mubi4_sender_clk_io_infra (
                                                 
738            .clk_i(clk_io),
                              
739            .rst_ni(rst_io_ni),
                                  
740            .mubi_i(((clk_io_en) ? MuBi4False : MuBi4True)),
                                    -1-  
                                    ==>  
                                    ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



748          ) u_prim_mubi4_sender_clk_io_div2_infra (
                                                      
749            .clk_i(clk_io_div2),
                                   
750            .rst_ni(rst_io_div2_ni),
                                       
751            .mubi_i(((clk_io_div2_en) ? MuBi4False : MuBi4True)),
                                         -1-  
                                         ==>  
                                         ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



759          ) u_prim_mubi4_sender_clk_io_div4_secure (
                                                       
760            .clk_i(clk_io_div4),
                                   
761            .rst_ni(rst_io_div4_ni),
                                       
762            .mubi_i(((clk_io_div4_en) ? MuBi4False : MuBi4True)),
                                         -1-  
                                         ==>  
                                         ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



770          ) u_prim_mubi4_sender_clk_main_secure (
                                                    
771            .clk_i(clk_main),
                                
772            .rst_ni(rst_main_ni),
                                    
773            .mubi_i(((clk_main_en) ? MuBi4False : MuBi4True)),
                                      -1-  
                                      ==>  
                                      ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



781          ) u_prim_mubi4_sender_clk_io_div4_timers (
                                                       
782            .clk_i(clk_io_div4),
                                   
783            .rst_ni(rst_io_div4_ni),
                                       
784            .mubi_i(((clk_io_div4_en) ? MuBi4False : MuBi4True)),
                                         -1-  
                                         ==>  
                                         ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



832          ) u_prim_mubi4_sender_clk_io_div4_peri (
                                                     
833            .clk_i(clk_io_div4),
                                   
834            .rst_ni(rst_io_div4_ni),
                                       
835            .mubi_i(((clk_io_div4_peri_combined_en) ? MuBi4False : MuBi4True)),
                                                       -1-  
                                                       ==>  
                                                       ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



874          ) u_prim_mubi4_sender_clk_io_div2_peri (
                                                     
875            .clk_i(clk_io_div2),
                                   
876            .rst_ni(rst_io_div2_ni),
                                       
877            .mubi_i(((clk_io_div2_peri_combined_en) ? MuBi4False : MuBi4True)),
                                                       -1-  
                                                       ==>  
                                                       ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



916          ) u_prim_mubi4_sender_clk_io_peri (
                                                
917            .clk_i(clk_io),
                              
918            .rst_ni(rst_io_ni),
                                  
919            .mubi_i(((clk_io_peri_combined_en) ? MuBi4False : MuBi4True)),
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



958          ) u_prim_mubi4_sender_clk_usb_peri (
                                                 
959            .clk_i(clk_usb),
                               
960            .rst_ni(rst_usb_ni),
                                   
961            .mubi_i(((clk_usb_peri_combined_en) ? MuBi4False : MuBi4True)),
                                                   -1-  
                                                   ==>  
                                                   ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



555            if (mubi4_test_false_strict(calib_rdy[BaseIdx])) begin
               -1-  
556              hw2reg.measure_ctrl_regwen.de = 1'b1;
                 ==>
557              hw2reg.measure_ctrl_regwen.d = 1'b1;
558            end
               MISSING_ELSE
               ==>

Branches:
-1-StatusTests
1 Covered T46,T1,T2
0 Covered T4,T5,T6

Assert Coverage for Module : clkmgr
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertsKnownO_A 38333870 35673180 0 0
AllClkBypReqKnownO_A 38333870 35673180 0 0
CgEnKnownO_A 38333870 35673180 0 0
ClocksKownO_A 38333870 35673180 0 0
FpvSecCmClkMainAesCountCheck_A 38333870 43 0 0
FpvSecCmClkMainHmacCountCheck_A 38333870 41 0 0
FpvSecCmClkMainKmacCountCheck_A 38333870 39 0 0
FpvSecCmClkMainOtbnCountCheck_A 38333870 39 0 0
FpvSecCmRegWeOnehotCheck_A 38333870 70 0 0
IoClkBypReqKnownO_A 38333870 35673180 0 0
JitterEnableKnownO_A 38333870 35673180 0 0
LcCtrlClkBypAckKnownO_A 38333870 35673180 0 0
PwrMgrKnownO_A 38333870 35673180 0 0
TlAReadyKnownO_A 38333870 35673180 0 0
TlDValidKnownO_A 38333870 35673180 0 0


AlertsKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 38333870 35673180 0 0
T4 2018 1899 0 0
T5 1797 1662 0 0
T6 1547 1307 0 0
T27 909 878 0 0
T28 1453 1365 0 0
T29 1295 1285 0 0
T30 1548 1534 0 0
T31 1104 970 0 0
T32 1632 1449 0 0
T33 1586 1334 0 0

AllClkBypReqKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 38333870 35673180 0 0
T4 2018 1899 0 0
T5 1797 1662 0 0
T6 1547 1307 0 0
T27 909 878 0 0
T28 1453 1365 0 0
T29 1295 1285 0 0
T30 1548 1534 0 0
T31 1104 970 0 0
T32 1632 1449 0 0
T33 1586 1334 0 0

CgEnKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 38333870 35673180 0 0
T4 2018 1899 0 0
T5 1797 1662 0 0
T6 1547 1307 0 0
T27 909 878 0 0
T28 1453 1365 0 0
T29 1295 1285 0 0
T30 1548 1534 0 0
T31 1104 970 0 0
T32 1632 1449 0 0
T33 1586 1334 0 0

ClocksKownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 38333870 35673180 0 0
T4 2018 1899 0 0
T5 1797 1662 0 0
T6 1547 1307 0 0
T27 909 878 0 0
T28 1453 1365 0 0
T29 1295 1285 0 0
T30 1548 1534 0 0
T31 1104 970 0 0
T32 1632 1449 0 0
T33 1586 1334 0 0

FpvSecCmClkMainAesCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 38333870 43 0 0
T3 229830 0 0 0
T19 20297 6 0 0
T20 1487 0 0 0
T21 1098 0 0 0
T22 901 0 0 0
T23 1643 0 0 0
T24 2061 0 0 0
T25 1148 0 0 0
T26 2878 0 0 0
T48 0 9 0 0
T53 0 8 0 0
T54 0 20 0 0
T55 1843 0 0 0

FpvSecCmClkMainHmacCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 38333870 41 0 0
T3 229830 0 0 0
T19 20297 4 0 0
T20 1487 0 0 0
T21 1098 0 0 0
T22 901 0 0 0
T23 1643 0 0 0
T24 2061 0 0 0
T25 1148 0 0 0
T26 2878 0 0 0
T48 0 10 0 0
T53 0 7 0 0
T54 0 20 0 0
T55 1843 0 0 0

FpvSecCmClkMainKmacCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 38333870 39 0 0
T3 229830 0 0 0
T19 20297 2 0 0
T20 1487 0 0 0
T21 1098 0 0 0
T22 901 0 0 0
T23 1643 0 0 0
T24 2061 0 0 0
T25 1148 0 0 0
T26 2878 0 0 0
T48 0 10 0 0
T53 0 7 0 0
T54 0 20 0 0
T55 1843 0 0 0

FpvSecCmClkMainOtbnCountCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 38333870 39 0 0
T3 229830 0 0 0
T19 20297 4 0 0
T20 1487 0 0 0
T21 1098 0 0 0
T22 901 0 0 0
T23 1643 0 0 0
T24 2061 0 0 0
T25 1148 0 0 0
T26 2878 0 0 0
T48 0 9 0 0
T53 0 7 0 0
T54 0 19 0 0
T55 1843 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 38333870 70 0 0
T1 70021 0 0 0
T19 0 20 0 0
T42 998 0 0 0
T43 1640 0 0 0
T46 14694 10 0 0
T48 0 10 0 0
T53 0 10 0 0
T54 0 20 0 0
T56 1450 0 0 0
T57 786 0 0 0
T58 1911 0 0 0
T59 1953 0 0 0
T60 2470 0 0 0
T61 1386 0 0 0

IoClkBypReqKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 38333870 35673180 0 0
T4 2018 1899 0 0
T5 1797 1662 0 0
T6 1547 1307 0 0
T27 909 878 0 0
T28 1453 1365 0 0
T29 1295 1285 0 0
T30 1548 1534 0 0
T31 1104 970 0 0
T32 1632 1449 0 0
T33 1586 1334 0 0

JitterEnableKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 38333870 35673180 0 0
T4 2018 1899 0 0
T5 1797 1662 0 0
T6 1547 1307 0 0
T27 909 878 0 0
T28 1453 1365 0 0
T29 1295 1285 0 0
T30 1548 1534 0 0
T31 1104 970 0 0
T32 1632 1449 0 0
T33 1586 1334 0 0

LcCtrlClkBypAckKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 38333870 35673180 0 0
T4 2018 1899 0 0
T5 1797 1662 0 0
T6 1547 1307 0 0
T27 909 878 0 0
T28 1453 1365 0 0
T29 1295 1285 0 0
T30 1548 1534 0 0
T31 1104 970 0 0
T32 1632 1449 0 0
T33 1586 1334 0 0

PwrMgrKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 38333870 35673180 0 0
T4 2018 1899 0 0
T5 1797 1662 0 0
T6 1547 1307 0 0
T27 909 878 0 0
T28 1453 1365 0 0
T29 1295 1285 0 0
T30 1548 1534 0 0
T31 1104 970 0 0
T32 1632 1449 0 0
T33 1586 1334 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 38333870 35673180 0 0
T4 2018 1899 0 0
T5 1797 1662 0 0
T6 1547 1307 0 0
T27 909 878 0 0
T28 1453 1365 0 0
T29 1295 1285 0 0
T30 1548 1534 0 0
T31 1104 970 0 0
T32 1632 1449 0 0
T33 1586 1334 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 38333870 35673180 0 0
T4 2018 1899 0 0
T5 1797 1662 0 0
T6 1547 1307 0 0
T27 909 878 0 0
T28 1453 1365 0 0
T29 1295 1285 0 0
T30 1548 1534 0 0
T31 1104 970 0 0
T32 1632 1449 0 0
T33 1586 1334 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%