Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	191669350	31257	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191669350	31257	0	0
T2	577925	404	0	0
T3	1149150	0	0	0
T9	0	105	0	0
T10	0	99	0	0
T12	0	189	0	0
T13	0	45	0	0
T14	0	231	0	0
T15	0	100	0	0
T16	0	133	0	0
T17	0	86	0	0
T18	0	55	0	0
T19	101485	0	0	0
T20	7435	0	0	0
T21	5490	0	0	0
T22	4505	0	0	0
T23	8215	0	0	0
T24	10305	0	0	0
T25	5740	0	0	0
T26	14390	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38333870	4771	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	4771	0	0
T2	115585	59	0	0
T3	229830	0	0	0
T9	0	18	0	0
T10	0	13	0	0
T12	0	28	0	0
T13	0	7	0	0
T14	0	37	0	0
T15	0	16	0	0
T16	0	21	0	0
T17	0	14	0	0
T18	0	9	0	0
T19	20297	0	0	0
T20	1487	0	0	0
T21	1098	0	0	0
T22	901	0	0	0
T23	1643	0	0	0
T24	2061	0	0	0
T25	1148	0	0	0
T26	2878	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38333870	4711	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	4711	0	0
T2	115585	58	0	0
T3	229830	0	0	0
T9	0	17	0	0
T10	0	12	0	0
T12	0	27	0	0
T13	0	7	0	0
T14	0	37	0	0
T15	0	16	0	0
T16	0	21	0	0
T17	0	14	0	0
T18	0	9	0	0
T19	20297	0	0	0
T20	1487	0	0	0
T21	1098	0	0	0
T22	901	0	0	0
T23	1643	0	0	0
T24	2061	0	0	0
T25	1148	0	0	0
T26	2878	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38333870	6288	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	6288	0	0
T2	115585	82	0	0
T3	229830	0	0	0
T9	0	21	0	0
T10	0	19	0	0
T12	0	37	0	0
T13	0	9	0	0
T14	0	47	0	0
T15	0	20	0	0
T16	0	27	0	0
T17	0	18	0	0
T18	0	11	0	0
T19	20297	0	0	0
T20	1487	0	0	0
T21	1098	0	0	0
T22	901	0	0	0
T23	1643	0	0	0
T24	2061	0	0	0
T25	1148	0	0	0
T26	2878	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38333870	6268	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	6268	0	0
T2	115585	81	0	0
T3	229830	0	0	0
T9	0	21	0	0
T10	0	19	0	0
T12	0	37	0	0
T13	0	10	0	0
T14	0	47	0	0
T15	0	20	0	0
T16	0	26	0	0
T17	0	17	0	0
T18	0	11	0	0
T19	20297	0	0	0
T20	1487	0	0	0
T21	1098	0	0	0
T22	901	0	0	0
T23	1643	0	0	0
T24	2061	0	0	0
T25	1148	0	0	0
T26	2878	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38333870	9219	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	9219	0	0
T2	115585	124	0	0
T3	229830	0	0	0
T9	0	28	0	0
T10	0	36	0	0
T12	0	60	0	0
T13	0	12	0	0
T14	0	63	0	0
T15	0	28	0	0
T16	0	38	0	0
T17	0	23	0	0
T18	0	15	0	0
T19	20297	0	0	0
T20	1487	0	0	0
T21	1098	0	0	0
T22	901	0	0	0
T23	1643	0	0	0
T24	2061	0	0	0
T25	1148	0	0	0
T26	2878	0	0	0