Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

22                      
23         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T46,T1,T19

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	38333870	35577505	0	0
AllClkBypReqTrue_A	38333870	93383	0	0
IoClkBypReqFalse_A	38333870	35518510	0	2409
IoClkBypReqTrue_A	38333870	147794	0	0
LcClkBypAckFalse_A	38333870	35584390	0	0
LcClkBypAckTrue_A	38333870	86498	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	35577505	0	0
T4	2018	1684	0	0
T5	1797	1661	0	0
T6	1547	1306	0	0
T27	909	877	0	0
T28	1453	1364	0	0
T29	1295	1284	0	0
T30	1548	1503	0	0
T31	1104	938	0	0
T32	1632	1370	0	0
T33	1586	1333	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	93383	0	0
T4	2018	214	0	0
T5	1797	0	0	0
T6	1547	0	0	0
T20	0	87	0	0
T27	909	0	0	0
T28	1453	0	0	0
T29	1295	0	0	0
T30	1548	30	0	0
T31	1104	31	0	0
T32	1632	78	0	0
T33	1586	0	0	0
T43	0	115	0	0
T57	0	21	0	0
T58	0	164	0	0
T61	0	100	0	0
T87	0	60	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	35518510	0	2409
T4	2018	1514	0	3
T5	1797	1659	0	3
T6	1547	1304	0	3
T27	909	875	0	3
T28	1453	1362	0	3
T29	1295	1282	0	3
T30	1548	1289	0	3
T31	1104	871	0	3
T32	1632	1446	0	3
T33	1586	1331	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	147794	0	0
T4	2018	382	0	0
T5	1797	0	0	0
T6	1547	0	0	0
T20	0	113	0	0
T24	0	122	0	0
T27	909	0	0	0
T28	1453	0	0	0
T29	1295	0	0	0
T30	1548	242	0	0
T31	1104	96	0	0
T32	1632	0	0	0
T33	1586	0	0	0
T43	0	278	0	0
T56	0	116	0	0
T58	0	321	0	0
T61	0	91	0	0
T87	0	112	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	35584390	0	0
T4	2018	1674	0	0
T5	1797	1661	0	0
T6	1547	1306	0	0
T27	909	877	0	0
T28	1453	1364	0	0
T29	1295	1284	0	0
T30	1548	1362	0	0
T31	1104	899	0	0
T32	1632	1448	0	0
T33	1586	1333	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	86498	0	0
T4	2018	224	0	0
T5	1797	0	0	0
T6	1547	0	0	0
T20	0	72	0	0
T24	0	75	0	0
T27	909	0	0	0
T28	1453	0	0	0
T29	1295	0	0	0
T30	1548	171	0	0
T31	1104	70	0	0
T32	1632	0	0	0
T33	1586	0	0	0
T43	0	125	0	0
T56	0	106	0	0
T58	0	256	0	0
T61	0	23	0	0
T87	0	63	0	0