Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	392640148	9388	0	0
TransStop_A	392640148	4961	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392640148	9388	0	0
T5	7492	4	0	0
T6	6192	0	0	0
T23	0	7	0	0
T27	14560	3	0	0
T28	11136	0	0	0
T29	25924	20	0	0
T30	77456	0	0	0
T31	7480	0	0	0
T32	6532	0	0	0
T33	6412	0	0	0
T44	0	4	0	0
T49	21064	4	0	0
T59	0	22	0	0
T60	0	31	0	0
T121	0	27	0	0
T122	0	4	0	0
T123	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392640148	4961	0	0
T5	7492	4	0	0
T6	6192	0	0	0
T23	0	7	0	0
T27	14560	3	0	0
T28	11136	0	0	0
T29	25924	14	0	0
T30	77456	0	0	0
T31	7480	0	0	0
T32	6532	0	0	0
T33	6412	0	0	0
T44	0	4	0	0
T49	21064	4	0	0
T59	0	10	0	0
T60	0	13	0	0
T121	0	16	0	0
T122	0	4	0	0
T123	0	4	0	0
T124	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	98160037	2341	0	0
TransStop_A	98160037	1241	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98160037	2341	0	0
T5	1873	1	0	0
T6	1548	0	0	0
T23	0	2	0	0
T27	3640	1	0	0
T28	2784	0	0	0
T29	6481	4	0	0
T30	19364	0	0	0
T31	1870	0	0	0
T32	1633	0	0	0
T33	1603	0	0	0
T44	0	1	0	0
T49	5266	1	0	0
T59	0	8	0	0
T60	0	7	0	0
T121	0	8	0	0
T122	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98160037	1241	0	0
T5	1873	1	0	0
T6	1548	0	0	0
T23	0	2	0	0
T27	3640	1	0	0
T28	2784	0	0	0
T29	6481	2	0	0
T30	19364	0	0	0
T31	1870	0	0	0
T32	1633	0	0	0
T33	1603	0	0	0
T44	0	1	0	0
T49	5266	1	0	0
T59	0	5	0	0
T60	0	3	0	0
T121	0	4	0	0
T122	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	98160037	2370	0	0
TransStop_A	98160037	1246	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98160037	2370	0	0
T5	1873	1	0	0
T6	1548	0	0	0
T23	0	3	0	0
T27	3640	1	0	0
T28	2784	0	0	0
T29	6481	5	0	0
T30	19364	0	0	0
T31	1870	0	0	0
T32	1633	0	0	0
T33	1603	0	0	0
T44	0	1	0	0
T49	5266	1	0	0
T59	0	8	0	0
T60	0	8	0	0
T121	0	2	0	0
T122	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98160037	1246	0	0
T5	1873	1	0	0
T6	1548	0	0	0
T23	0	3	0	0
T27	3640	1	0	0
T28	2784	0	0	0
T29	6481	4	0	0
T30	19364	0	0	0
T31	1870	0	0	0
T32	1633	0	0	0
T33	1603	0	0	0
T44	0	1	0	0
T49	5266	1	0	0
T59	0	3	0	0
T60	0	3	0	0
T121	0	2	0	0
T122	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	98160037	2334	0	0
TransStop_A	98160037	1224	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98160037	2334	0	0
T5	1873	1	0	0
T6	1548	0	0	0
T23	0	1	0	0
T27	3640	0	0	0
T28	2784	0	0	0
T29	6481	6	0	0
T30	19364	0	0	0
T31	1870	0	0	0
T32	1633	0	0	0
T33	1603	0	0	0
T44	0	1	0	0
T49	5266	1	0	0
T59	0	2	0	0
T60	0	7	0	0
T121	0	11	0	0
T122	0	1	0	0
T123	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98160037	1224	0	0
T5	1873	1	0	0
T6	1548	0	0	0
T23	0	1	0	0
T27	3640	0	0	0
T28	2784	0	0	0
T29	6481	4	0	0
T30	19364	0	0	0
T31	1870	0	0	0
T32	1633	0	0	0
T33	1603	0	0	0
T44	0	1	0	0
T49	5266	1	0	0
T60	0	4	0	0
T121	0	6	0	0
T122	0	1	0	0
T123	0	4	0	0
T124	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	98160037	2343	0	0
TransStop_A	98160037	1250	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98160037	2343	0	0
T5	1873	1	0	0
T6	1548	0	0	0
T23	0	1	0	0
T27	3640	1	0	0
T28	2784	0	0	0
T29	6481	5	0	0
T30	19364	0	0	0
T31	1870	0	0	0
T32	1633	0	0	0
T33	1603	0	0	0
T44	0	1	0	0
T49	5266	1	0	0
T59	0	4	0	0
T60	0	9	0	0
T121	0	6	0	0
T122	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98160037	1250	0	0
T5	1873	1	0	0
T6	1548	0	0	0
T23	0	1	0	0
T27	3640	1	0	0
T28	2784	0	0	0
T29	6481	4	0	0
T30	19364	0	0	0
T31	1870	0	0	0
T32	1633	0	0	0
T33	1603	0	0	0
T44	0	1	0	0
T49	5266	1	0	0
T59	0	2	0	0
T60	0	3	0	0
T121	0	4	0	0
T122	0	1	0	0