Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	38333870	2739171	0	53

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	2739171	0	53
T2	115585	35956	0	1
T3	229830	0	0	0
T9	0	6839	0	1
T10	0	11697	0	1
T12	0	18962	0	1
T13	0	3988	0	0
T14	0	15273	0	1
T15	0	7817	0	0
T17	0	0	0	1
T18	0	0	0	1
T19	20297	0	0	0
T20	1487	0	0	0
T21	1098	0	0	0
T22	901	0	0	0
T23	1643	0	0	0
T24	2061	0	0	0
T25	1148	0	0	0
T26	2878	0	0	0
T34	0	17	0	0
T35	0	0	0	1
T40	0	586	0	1
T41	0	589	0	0
T126	0	0	0	1