Unified Coverage Report :: Module :: clkmgr_extclk_sva_if

Module : clkmgr_extclk_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_extclk_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_extclk_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_extclk_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_extclk_sva_if

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	34	1	1	100.00
ALWAYS	49	1	1	100.00
ALWAYS	66	1	1	100.00

33                        logic lc_clk_byp_req;
34         1/1            always_comb lc_clk_byp_req = lc_clk_byp_req_i == On;
           Tests:       T4 T30 T31 
35                      
36                        `ASSERT(IoClkBypReqRise_A,
37                                $rose(
38                                    lc_clk_byp_req
39                                ) |=> ##[RiseCyclesMin:RiseCyclesMax] !lc_clk_byp_req || (io_clk_byp_req_o == MuBi4True),
40                                clk_i, !rst_ni || disable_sva)
41                        `ASSERT(IoClkBypReqFall_A,
42                                $fell(
43                                    lc_clk_byp_req
44                                ) |=> ##[FallCyclesMin:FallCyclesMax] lc_clk_byp_req || (io_clk_byp_req_o != MuBi4False),
45                                clk_i, !rst_ni || disable_sva)
46                      
47                        // Check extclk_ctrl triggers all_clk_byp_req_o and hi_speed_sel_o.
48                        logic extclk_sel_enabled;
49         1/1            always_comb extclk_sel_enabled = extclk_ctrl_sel == MuBi4True && lc_hw_debug_en_i == On;
           Tests:       T4 T30 T31 
50                      
51                        `ASSERT(AllClkBypReqRise_A,
52                                $rose(
53                                    extclk_sel_enabled
54                                ) |=> ##[RiseCyclesMin:RiseCyclesMax]
55                                    !extclk_sel_enabled || (all_clk_byp_req_o == MuBi4True),
56                                clk_i, !rst_ni || disable_sva)
57                        `ASSERT(AllClkBypReqFall_A,
58                                $fell(
59                                    extclk_sel_enabled
60                                ) |=> ##[FallCyclesMin:FallCyclesMax]
61                                    extclk_sel_enabled || (all_clk_byp_req_o != MuBi4True),
62                                clk_i, !rst_ni || disable_sva)
63                      
64                        logic hi_speed_enabled;
65                        always_comb begin
66         1/1              hi_speed_enabled = extclk_ctrl_sel == MuBi4True && extclk_ctrl_hi_speed_sel == MuBi4True &&
           Tests:       T4 T30 T31 

---

Cond Coverage for Module : clkmgr_extclk_sva_if

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (lc_clk_byp_req_i == On)
            ------------1-----------

-1-	Status	Tests
0	Covered	T4,T30,T31
1	Covered	T4,T30,T31

 LINE       49
 EXPRESSION ((extclk_ctrl_sel == MuBi4True) && (lc_hw_debug_en_i == On))
             ---------------1--------------    ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T30,T31
1	0	Covered	T4,T30,T31
1	1	Covered	T4,T30,T31

 LINE       49
 SUB-EXPRESSION (extclk_ctrl_sel == MuBi4True)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T4,T30,T31
1	Covered	T4,T30,T31

 LINE       49
 SUB-EXPRESSION (lc_hw_debug_en_i == On)
                ------------1-----------

-1-	Status	Tests
0	Covered	T4,T30,T31
1	Covered	T4,T30,T31

 LINE       66
 EXPRESSION ((extclk_ctrl_sel == MuBi4True) && (extclk_ctrl_hi_speed_sel == MuBi4True) && (lc_hw_debug_en_i == On))
             ---------------1--------------    -------------------2-------------------    ------------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T30,T31
1	0	1	Covered	T4,T30,T32
1	1	0	Covered	T4,T30,T31
1	1	1	Covered	T4,T31,T32

 LINE       66
 SUB-EXPRESSION (extclk_ctrl_sel == MuBi4True)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T4,T30,T31
1	Covered	T4,T30,T31

 LINE       66
 SUB-EXPRESSION (extclk_ctrl_hi_speed_sel == MuBi4True)
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T4,T30,T31
1	Covered	T4,T30,T31

 LINE       66
 SUB-EXPRESSION (lc_hw_debug_en_i == On)
                ------------1-----------

-1-	Status	Tests
0	Covered	T4,T30,T31
1	Covered	T4,T30,T31

---

Assert Coverage for Module : clkmgr_extclk_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFall_A	38333870	2890	0	0
AllClkBypReqRise_A	38333870	2890	0	0
HiSpeedSelFall_A	38333870	1699	0	0
HiSpeedSelRise_A	38333870	1699	0	0
IoClkBypReqFall_A	38333870	3612	0	0
IoClkBypReqRise_A	38333870	3608	0	0

AllClkBypReqFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	2890	0	0
T4	2018	6	0	0
T5	1797	0	0	0
T6	1547	0	0	0
T20	0	3	0	0
T27	909	0	0	0
T28	1453	0	0	0
T29	1295	0	0	0
T30	1548	1	0	0
T31	1104	1	0	0
T32	1632	4	0	0
T33	1586	0	0	0
T43	0	6	0	0
T57	0	1	0	0
T58	0	6	0	0
T61	0	6	0	0
T87	0	6	0	0

AllClkBypReqRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	2890	0	0
T4	2018	6	0	0
T5	1797	0	0	0
T6	1547	0	0	0
T20	0	3	0	0
T27	909	0	0	0
T28	1453	0	0	0
T29	1295	0	0	0
T30	1548	1	0	0
T31	1104	1	0	0
T32	1632	4	0	0
T33	1586	0	0	0
T43	0	6	0	0
T57	0	1	0	0
T58	0	6	0	0
T61	0	6	0	0
T87	0	6	0	0

HiSpeedSelFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	1699	0	0
T4	2018	2	0	0
T5	1797	0	0	0
T6	1547	0	0	0
T20	0	2	0	0
T24	0	7	0	0
T27	909	0	0	0
T28	1453	0	0	0
T29	1295	0	0	0
T30	1548	0	0	0
T31	1104	1	0	0
T32	1632	2	0	0
T33	1586	0	0	0
T43	0	1	0	0
T57	0	1	0	0
T58	0	5	0	0
T61	0	2	0	0
T87	0	6	0	0

HiSpeedSelRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	1699	0	0
T4	2018	2	0	0
T5	1797	0	0	0
T6	1547	0	0	0
T20	0	2	0	0
T24	0	7	0	0
T27	909	0	0	0
T28	1453	0	0	0
T29	1295	0	0	0
T30	1548	0	0	0
T31	1104	1	0	0
T32	1632	2	0	0
T33	1586	0	0	0
T43	0	1	0	0
T57	0	1	0	0
T58	0	5	0	0
T61	0	2	0	0
T87	0	6	0	0

IoClkBypReqFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	3612	0	0
T4	2018	10	0	0
T5	1797	0	0	0
T6	1547	0	0	0
T20	0	4	0	0
T24	0	3	0	0
T27	909	0	0	0
T28	1453	0	0	0
T29	1295	0	0	0
T30	1548	7	0	0
T31	1104	3	0	0
T32	1632	0	0	0
T33	1586	0	0	0
T43	0	9	0	0
T56	0	3	0	0
T58	0	8	0	0
T61	0	4	0	0
T87	0	4	0	0

IoClkBypReqRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	3608	0	0
T4	2018	10	0	0
T5	1797	0	0	0
T6	1547	0	0	0
T20	0	4	0	0
T24	0	3	0	0
T27	909	0	0	0
T28	1453	0	0	0
T29	1295	0	0	0
T30	1548	7	0	0
T31	1104	3	0	0
T32	1632	0	0	0
T33	1586	0	0	0
T43	0	9	0	0
T56	0	3	0	0
T58	0	8	0	0
T61	0	4	0	0
T87	0	4	0	0