Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	39205114	544817	0	0
clk_enables_rd_A	39205114	9237	0	0
clk_hints_rd_A	39205114	9047	0	0
extclk_ctrl_rd_A	39205114	14002	0	0
extclk_ctrl_regwen_rd_A	39205114	7436	0	0
jitter_enable_rd_A	39205114	17612	0	0
jitter_regwen_rd_A	39205114	7934	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39205114	544817	0	0
T15	0	3258	0	0
T16	0	3854	0	0
T34	108261	5605	0	0
T71	0	6957	0	0
T72	0	2380	0	0
T73	0	7658	0	0
T74	0	8714	0	0
T75	0	10734	0	0
T76	0	15562	0	0
T77	0	3129	0	0
T78	2024	0	0	0
T79	1373	0	0	0
T80	2248	0	0	0
T81	1048	0	0	0
T82	67988	0	0	0
T83	182020	0	0	0
T84	1892	0	0	0
T85	692	0	0	0
T86	871	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39205114	9237	0	0
T9	58729	0	0	0
T10	132568	0	0	0
T13	0	4	0	0
T15	0	81	0	0
T37	18425	0	0	0
T38	25975	0	0	0
T48	15946	0	0	0
T71	0	295	0	0
T72	0	151	0	0
T122	1882	1	0	0
T123	2792	0	0	0
T124	1602	0	0	0
T144	0	10	0	0
T145	0	6	0	0
T146	0	13	0	0
T147	0	5	0	0
T148	0	5	0	0
T149	1484	0	0	0
T150	1306	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39205114	9047	0	0
T9	58729	0	0	0
T10	132568	0	0	0
T13	0	8	0	0
T15	0	110	0	0
T37	18425	0	0	0
T38	25975	0	0	0
T48	15946	0	0	0
T71	0	312	0	0
T72	0	113	0	0
T122	1882	4	0	0
T123	2792	0	0	0
T124	1602	0	0	0
T145	0	6	0	0
T146	0	13	0	0
T147	0	5	0	0
T148	0	1	0	0
T149	1484	0	0	0
T150	1306	0	0	0
T151	0	2	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39205114	14002	0	0
T1	70021	0	0	0
T26	0	40	0	0
T42	998	0	0	0
T43	1640	0	0	0
T44	1729	0	0	0
T56	1450	18	0	0
T57	786	0	0	0
T58	1911	0	0	0
T59	1953	0	0	0
T60	2470	0	0	0
T61	1386	0	0	0
T152	0	34	0	0
T153	0	57	0	0
T154	0	16	0	0
T155	0	59	0	0
T156	0	59	0	0
T157	0	37	0	0
T158	0	9	0	0
T159	0	16	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39205114	7436	0	0
T15	95201	83	0	0
T16	69741	0	0	0
T71	0	247	0	0
T72	0	78	0	0
T74	0	372	0	0
T75	0	484	0	0
T160	0	26	0	0
T161	0	44	0	0
T162	0	18	0	0
T163	0	28	0	0
T164	0	24	0	0
T165	1807	0	0	0
T166	840	0	0	0
T167	1669	0	0	0
T168	1385	0	0	0
T169	1831	0	0	0
T170	11447	0	0	0
T171	2194	0	0	0
T172	2169	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39205114	17612	0	0
T9	58729	0	0	0
T10	132568	0	0	0
T13	0	110	0	0
T15	0	71	0	0
T37	18425	0	0	0
T38	25975	0	0	0
T48	15946	0	0	0
T71	0	517	0	0
T122	1882	114	0	0
T123	2792	0	0	0
T124	1602	0	0	0
T144	0	66	0	0
T145	0	116	0	0
T146	0	251	0	0
T147	0	117	0	0
T149	1484	0	0	0
T150	1306	0	0	0
T151	0	107	0	0
T173	0	68	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39205114	7934	0	0
T15	95201	129	0	0
T16	69741	0	0	0
T71	0	286	0	0
T72	0	96	0	0
T74	0	390	0	0
T75	0	532	0	0
T76	0	226	0	0
T165	1807	0	0	0
T166	840	0	0	0
T167	1669	0	0	0
T168	1385	0	0	0
T169	1831	0	0	0
T170	11447	0	0	0
T171	2194	0	0	0
T172	2169	0	0	0
T174	0	285	0	0
T175	0	476	0	0
T176	0	365	0	0
T177	0	271	0	0