Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

24                        logic step_down;
25         1/1            always_comb step_down = div_step_down_req_i && !scanmode;
           Tests:       T4 T5 T6 
26                      
27                        logic step_up;
28         1/1            always_comb step_up = !step_down;
           Tests:       T4 T30 T31 

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T30,T32
1	1	Covered	T4,T30,T31

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	88308290	3152	0	0
g_div2.Div2Whole_A	88308290	3678	0	0
g_div4.Div4Stepped_A	43310700	3094	0	0
g_div4.Div4Whole_A	43310700	3493	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88308290	3152	0	0
T4	2516	7	0	0
T5	1798	0	0	0
T6	1486	0	0	0
T27	3494	0	0	0
T28	2763	0	0	0
T29	6221	0	0	0
T30	18589	6	0	0
T31	1796	3	0	0
T32	1568	1	0	0
T33	1538	0	0	0
T43	0	9	0	0
T56	0	3	0	0
T57	0	1	0	0
T58	0	11	0	0
T61	0	3	0	0
T87	0	7	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88308290	3678	0	0
T4	2516	10	0	0
T5	1798	0	0	0
T6	1486	0	0	0
T27	3494	0	0	0
T28	2763	0	0	0
T29	6221	0	0	0
T30	18589	6	0	0
T31	1796	3	0	0
T32	1568	3	0	0
T33	1538	0	0	0
T43	0	9	0	0
T56	0	3	0	0
T57	0	1	0	0
T58	0	11	0	0
T61	0	2	0	0
T87	0	7	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43310700	3094	0	0
T4	1361	7	0	0
T5	887	0	0	0
T6	697	0	0	0
T27	1708	0	0	0
T28	1321	0	0	0
T29	3098	0	0	0
T30	10398	6	0	0
T31	910	3	0	0
T32	763	1	0	0
T33	716	0	0	0
T43	0	9	0	0
T56	0	3	0	0
T57	0	1	0	0
T58	0	11	0	0
T61	0	3	0	0
T87	0	7	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43310700	3493	0	0
T4	1361	10	0	0
T5	887	0	0	0
T6	697	0	0	0
T27	1708	0	0	0
T28	1321	0	0	0
T29	3098	0	0	0
T30	10398	6	0	0
T31	910	3	0	0
T32	763	2	0	0
T33	716	0	0	0
T43	0	8	0	0
T56	0	3	0	0
T57	0	1	0	0
T58	0	11	0	0
T61	0	2	0	0
T87	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

24                        logic step_down;
25         1/1            always_comb step_down = div_step_down_req_i && !scanmode;
           Tests:       T4 T5 T6 
26                      
27                        logic step_up;
28         1/1            always_comb step_up = !step_down;
           Tests:       T4 T30 T31 

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T30,T32
1	1	Covered	T4,T30,T31

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	88308290	3152	0	0
g_div2.Div2Whole_A	88308290	3678	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88308290	3152	0	0
T4	2516	7	0	0
T5	1798	0	0	0
T6	1486	0	0	0
T27	3494	0	0	0
T28	2763	0	0	0
T29	6221	0	0	0
T30	18589	6	0	0
T31	1796	3	0	0
T32	1568	1	0	0
T33	1538	0	0	0
T43	0	9	0	0
T56	0	3	0	0
T57	0	1	0	0
T58	0	11	0	0
T61	0	3	0	0
T87	0	7	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88308290	3678	0	0
T4	2516	10	0	0
T5	1798	0	0	0
T6	1486	0	0	0
T27	3494	0	0	0
T28	2763	0	0	0
T29	6221	0	0	0
T30	18589	6	0	0
T31	1796	3	0	0
T32	1568	3	0	0
T33	1538	0	0	0
T43	0	9	0	0
T56	0	3	0	0
T57	0	1	0	0
T58	0	11	0	0
T61	0	2	0	0
T87	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

24                        logic step_down;
25         1/1            always_comb step_down = div_step_down_req_i && !scanmode;
           Tests:       T4 T5 T6 
26                      
27                        logic step_up;
28         1/1            always_comb step_up = !step_down;
           Tests:       T4 T30 T31 

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T30,T32
1	1	Covered	T4,T30,T31

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	43310700	3094	0	0
g_div4.Div4Whole_A	43310700	3493	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43310700	3094	0	0
T4	1361	7	0	0
T5	887	0	0	0
T6	697	0	0	0
T27	1708	0	0	0
T28	1321	0	0	0
T29	3098	0	0	0
T30	10398	6	0	0
T31	910	3	0	0
T32	763	1	0	0
T33	716	0	0	0
T43	0	9	0	0
T56	0	3	0	0
T57	0	1	0	0
T58	0	11	0	0
T61	0	3	0	0
T87	0	7	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43310700	3493	0	0
T4	1361	10	0	0
T5	887	0	0	0
T6	697	0	0	0
T27	1708	0	0	0
T28	1321	0	0	0
T29	3098	0	0	0
T30	10398	6	0	0
T31	910	3	0	0
T32	763	2	0	0
T33	716	0	0	0
T43	0	8	0	0
T56	0	3	0	0
T57	0	1	0	0
T58	0	11	0	0
T61	0	2	0	0
T87	0	6	0	0