Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	115001610	407	0	0
StatusRise_A	115001610	407	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115001610	407	0	0
T21	0	15	0	0
T28	4359	13	0	0
T29	3885	0	0	0
T30	4644	0	0	0
T31	3312	0	0	0
T32	4896	0	0	0
T33	4758	0	0	0
T47	5055	11	0	0
T49	3789	0	0	0
T86	0	5	0	0
T87	4218	0	0	0
T105	2859	0	0	0
T149	0	6	0	0
T165	0	12	0	0
T178	0	12	0	0
T179	0	4	0	0
T180	0	7	0	0
T181	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115001610	407	0	0
T21	0	15	0	0
T28	4359	13	0	0
T29	3885	0	0	0
T30	4644	0	0	0
T31	3312	0	0	0
T32	4896	0	0	0
T33	4758	0	0	0
T47	5055	11	0	0
T49	3789	0	0	0
T86	0	5	0	0
T87	4218	0	0	0
T105	2859	0	0	0
T149	0	6	0	0
T165	0	12	0	0
T178	0	12	0	0
T179	0	4	0	0
T180	0	7	0	0
T181	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	38333870	139	0	0
StatusRise_A	38333870	139	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	139	0	0
T21	0	5	0	0
T28	1453	5	0	0
T29	1295	0	0	0
T30	1548	0	0	0
T31	1104	0	0	0
T32	1632	0	0	0
T33	1586	0	0	0
T47	1685	5	0	0
T49	1263	0	0	0
T86	0	2	0	0
T87	1406	0	0	0
T105	953	0	0	0
T149	0	3	0	0
T165	0	5	0	0
T178	0	4	0	0
T179	0	1	0	0
T180	0	2	0	0
T181	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	139	0	0
T21	0	5	0	0
T28	1453	5	0	0
T29	1295	0	0	0
T30	1548	0	0	0
T31	1104	0	0	0
T32	1632	0	0	0
T33	1586	0	0	0
T47	1685	5	0	0
T49	1263	0	0	0
T86	0	2	0	0
T87	1406	0	0	0
T105	953	0	0	0
T149	0	3	0	0
T165	0	5	0	0
T178	0	4	0	0
T179	0	1	0	0
T180	0	2	0	0
T181	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	38333870	142	0	0
StatusRise_A	38333870	142	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	142	0	0
T21	0	5	0	0
T28	1453	4	0	0
T29	1295	0	0	0
T30	1548	0	0	0
T31	1104	0	0	0
T32	1632	0	0	0
T33	1586	0	0	0
T47	1685	3	0	0
T49	1263	0	0	0
T86	0	2	0	0
T87	1406	0	0	0
T105	953	0	0	0
T149	0	2	0	0
T165	0	4	0	0
T178	0	4	0	0
T179	0	1	0	0
T180	0	2	0	0
T181	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	142	0	0
T21	0	5	0	0
T28	1453	4	0	0
T29	1295	0	0	0
T30	1548	0	0	0
T31	1104	0	0	0
T32	1632	0	0	0
T33	1586	0	0	0
T47	1685	3	0	0
T49	1263	0	0	0
T86	0	2	0	0
T87	1406	0	0	0
T105	953	0	0	0
T149	0	2	0	0
T165	0	4	0	0
T178	0	4	0	0
T179	0	1	0	0
T180	0	2	0	0
T181	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	38333870	126	0	0
StatusRise_A	38333870	126	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	126	0	0
T21	0	5	0	0
T28	1453	4	0	0
T29	1295	0	0	0
T30	1548	0	0	0
T31	1104	0	0	0
T32	1632	0	0	0
T33	1586	0	0	0
T47	1685	3	0	0
T49	1263	0	0	0
T86	0	1	0	0
T87	1406	0	0	0
T105	953	0	0	0
T149	0	1	0	0
T165	0	3	0	0
T178	0	4	0	0
T179	0	2	0	0
T180	0	3	0	0
T181	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38333870	126	0	0
T21	0	5	0	0
T28	1453	4	0	0
T29	1295	0	0	0
T30	1548	0	0	0
T31	1104	0	0	0
T32	1632	0	0	0
T33	1586	0	0	0
T47	1685	3	0	0
T49	1263	0	0	0
T86	0	1	0	0
T87	1406	0	0	0
T105	953	0	0	0
T149	0	1	0	0
T165	0	3	0	0
T178	0	4	0	0
T179	0	2	0	0
T180	0	3	0	0
T181	0	1	0	0