Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T47,T46
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	1032958578	33180	0	0
CgEnOn_A	1032958578	24018	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032958578	33180	0	0
T4	5813	3	0	0
T5	11513	6	0	0
T6	9462	20	0	0
T15	0	5	0	0
T21	0	30	0	0
T27	22358	4	0	0
T28	30140	40	0	0
T29	69934	7	0	0
T30	213536	3	0	0
T31	20236	3	0	0
T32	17546	3	0	0
T33	17090	3	0	0
T47	6652	20	0	0
T49	45406	1	0	0
T59	0	8	0	0
T86	0	10	0	0
T87	75757	0	0	0
T105	17591	0	0	0
T149	0	10	0	0
T178	0	20	0	0
T179	0	5	0	0
T180	0	10	0	0
T181	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1032958578	24018	0	0
T5	11070	3	0	0
T6	9462	17	0	0
T15	0	4	0	0
T21	0	45	0	0
T22	0	36	0	0
T27	22358	1	0	0
T28	30140	37	0	0
T29	69934	4	0	0
T30	213536	0	0	0
T31	20236	0	0	0
T32	17546	0	0	0
T33	17090	0	0	0
T44	0	4	0	0
T47	6652	29	0	0
T49	56728	4	0	0
T86	0	10	0	0
T87	80160	0	0	0
T105	17591	20	0	0
T122	0	1	0	0
T149	0	10	0	0
T165	0	4	0	0
T178	0	20	0	0
T179	0	5	0	0
T180	0	10	0	0
T181	0	10	0	0
T182	0	28	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T47,T46
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	43310283	160	0	0
CgEnOn_A	43310283	160	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43310283	160	0	0
T15	0	1	0	0
T21	0	5	0	0
T28	1321	4	0	0
T29	3098	0	0	0
T30	10398	0	0	0
T31	909	0	0	0
T32	763	0	0	0
T33	716	0	0	0
T47	646	3	0	0
T49	2494	0	0	0
T86	0	2	0	0
T87	8805	0	0	0
T105	1785	0	0	0
T149	0	2	0	0
T178	0	4	0	0
T179	0	1	0	0
T180	0	2	0	0
T181	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43310283	160	0	0
T15	0	1	0	0
T21	0	5	0	0
T28	1321	4	0	0
T29	3098	0	0	0
T30	10398	0	0	0
T31	909	0	0	0
T32	763	0	0	0
T33	716	0	0	0
T47	646	3	0	0
T49	2494	0	0	0
T86	0	2	0	0
T87	8805	0	0	0
T105	1785	0	0	0
T149	0	2	0	0
T178	0	4	0	0
T179	0	1	0	0
T180	0	2	0	0
T181	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T47,T46
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	21654700	160	0	0
CgEnOn_A	21654700	160	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21654700	160	0	0
T15	0	1	0	0
T21	0	5	0	0
T28	660	4	0	0
T29	1549	0	0	0
T30	5198	0	0	0
T31	453	0	0	0
T32	382	0	0	0
T33	358	0	0	0
T47	323	3	0	0
T49	1247	0	0	0
T86	0	2	0	0
T87	4403	0	0	0
T105	893	0	0	0
T149	0	2	0	0
T178	0	4	0	0
T179	0	1	0	0
T180	0	2	0	0
T181	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21654700	160	0	0
T15	0	1	0	0
T21	0	5	0	0
T28	660	4	0	0
T29	1549	0	0	0
T30	5198	0	0	0
T31	453	0	0	0
T32	382	0	0	0
T33	358	0	0	0
T47	323	3	0	0
T49	1247	0	0	0
T86	0	2	0	0
T87	4403	0	0	0
T105	893	0	0	0
T149	0	2	0	0
T178	0	4	0	0
T179	0	1	0	0
T180	0	2	0	0
T181	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T47,T46
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	21654700	160	0	0
CgEnOn_A	21654700	160	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21654700	160	0	0
T15	0	1	0	0
T21	0	5	0	0
T28	660	4	0	0
T29	1549	0	0	0
T30	5198	0	0	0
T31	453	0	0	0
T32	382	0	0	0
T33	358	0	0	0
T47	323	3	0	0
T49	1247	0	0	0
T86	0	2	0	0
T87	4403	0	0	0
T105	893	0	0	0
T149	0	2	0	0
T178	0	4	0	0
T179	0	1	0	0
T180	0	2	0	0
T181	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21654700	160	0	0
T15	0	1	0	0
T21	0	5	0	0
T28	660	4	0	0
T29	1549	0	0	0
T30	5198	0	0	0
T31	453	0	0	0
T32	382	0	0	0
T33	358	0	0	0
T47	323	3	0	0
T49	1247	0	0	0
T86	0	2	0	0
T87	4403	0	0	0
T105	893	0	0	0
T149	0	2	0	0
T178	0	4	0	0
T179	0	1	0	0
T180	0	2	0	0
T181	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T47,T46
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	21654700	160	0	0
CgEnOn_A	21654700	160	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21654700	160	0	0
T15	0	1	0	0
T21	0	5	0	0
T28	660	4	0	0
T29	1549	0	0	0
T30	5198	0	0	0
T31	453	0	0	0
T32	382	0	0	0
T33	358	0	0	0
T47	323	3	0	0
T49	1247	0	0	0
T86	0	2	0	0
T87	4403	0	0	0
T105	893	0	0	0
T149	0	2	0	0
T178	0	4	0	0
T179	0	1	0	0
T180	0	2	0	0
T181	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21654700	160	0	0
T15	0	1	0	0
T21	0	5	0	0
T28	660	4	0	0
T29	1549	0	0	0
T30	5198	0	0	0
T31	453	0	0	0
T32	382	0	0	0
T33	358	0	0	0
T47	323	3	0	0
T49	1247	0	0	0
T86	0	2	0	0
T87	4403	0	0	0
T105	893	0	0	0
T149	0	2	0	0
T178	0	4	0	0
T179	0	1	0	0
T180	0	2	0	0
T181	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T47,T46
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	88307846	160	0	0
CgEnOn_A	88307846	145	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88307846	160	0	0
T15	0	1	0	0
T21	0	5	0	0
T28	2762	4	0	0
T29	6220	0	0	0
T30	18588	0	0	0
T31	1796	0	0	0
T32	1567	0	0	0
T33	1538	0	0	0
T47	1399	3	0	0
T49	5054	0	0	0
T86	0	2	0	0
T87	14998	0	0	0
T105	3664	0	0	0
T149	0	2	0	0
T178	0	4	0	0
T179	0	1	0	0
T180	0	2	0	0
T181	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88307846	145	0	0
T21	0	5	0	0
T28	2762	4	0	0
T29	6220	0	0	0
T30	18588	0	0	0
T31	1796	0	0	0
T32	1567	0	0	0
T33	1538	0	0	0
T47	1399	3	0	0
T49	5054	0	0	0
T86	0	2	0	0
T87	14998	0	0	0
T105	3664	0	0	0
T149	0	2	0	0
T165	0	4	0	0
T178	0	4	0	0
T179	0	1	0	0
T180	0	2	0	0
T181	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T47,T46
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	98159591	142	0	0
CgEnOn_A	98159591	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98159591	142	0	0
T21	0	5	0	0
T28	2783	5	0	0
T29	6480	0	0	0
T30	19364	0	0	0
T31	1870	0	0	0
T32	1632	0	0	0
T33	1602	0	0	0
T47	1425	5	0	0
T49	5265	0	0	0
T86	0	2	0	0
T87	15623	0	0	0
T105	3816	0	0	0
T149	0	3	0	0
T165	0	5	0	0
T178	0	4	0	0
T179	0	1	0	0
T180	0	2	0	0
T181	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98159591	139	0	0
T21	0	5	0	0
T28	2783	5	0	0
T29	6480	0	0	0
T30	19364	0	0	0
T31	1870	0	0	0
T32	1632	0	0	0
T33	1602	0	0	0
T47	1425	5	0	0
T49	5265	0	0	0
T86	0	2	0	0
T87	15623	0	0	0
T105	3816	0	0	0
T149	0	3	0	0
T165	0	5	0	0
T178	0	4	0	0
T179	0	1	0	0
T180	0	2	0	0
T181	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T47,T46
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	98159591	142	0	0
CgEnOn_A	98159591	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98159591	142	0	0
T21	0	5	0	0
T28	2783	5	0	0
T29	6480	0	0	0
T30	19364	0	0	0
T31	1870	0	0	0
T32	1632	0	0	0
T33	1602	0	0	0
T47	1425	5	0	0
T49	5265	0	0	0
T86	0	2	0	0
T87	15623	0	0	0
T105	3816	0	0	0
T149	0	3	0	0
T165	0	5	0	0
T178	0	4	0	0
T179	0	1	0	0
T180	0	2	0	0
T181	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98159591	139	0	0
T21	0	5	0	0
T28	2783	5	0	0
T29	6480	0	0	0
T30	19364	0	0	0
T31	1870	0	0	0
T32	1632	0	0	0
T33	1602	0	0	0
T47	1425	5	0	0
T49	5265	0	0	0
T86	0	2	0	0
T87	15623	0	0	0
T105	3816	0	0	0
T149	0	3	0	0
T165	0	5	0	0
T178	0	4	0	0
T179	0	1	0	0
T180	0	2	0	0
T181	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T47,T46
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	47072987	130	0	0
CgEnOn_A	47072987	128	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47072987	130	0	0
T21	0	5	0	0
T28	1318	4	0	0
T29	3111	0	0	0
T30	9294	0	0	0
T31	897	0	0	0
T32	783	0	0	0
T33	769	0	0	0
T47	788	3	0	0
T49	2527	0	0	0
T86	0	1	0	0
T87	7499	0	0	0
T105	1831	0	0	0
T149	0	1	0	0
T165	0	3	0	0
T178	0	4	0	0
T179	0	2	0	0
T180	0	3	0	0
T181	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47072987	128	0	0
T21	0	5	0	0
T28	1318	4	0	0
T29	3111	0	0	0
T30	9294	0	0	0
T31	897	0	0	0
T32	783	0	0	0
T33	769	0	0	0
T47	788	3	0	0
T49	2527	0	0	0
T86	0	1	0	0
T87	7499	0	0	0
T105	1831	0	0	0
T149	0	1	0	0
T165	0	3	0	0
T178	0	4	0	0
T179	0	2	0	0
T180	0	3	0	0
T181	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T47,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	21654700	5474	0	0
CgEnOn_A	21654700	3200	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21654700	5474	0	0
T4	679	1	0	0
T5	443	1	0	0
T6	348	6	0	0
T27	854	1	0	0
T28	660	5	0	0
T29	1549	1	0	0
T30	5198	1	0	0
T31	453	1	0	0
T32	382	1	0	0
T33	358	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21654700	3200	0	0
T6	348	5	0	0
T21	0	5	0	0
T22	0	12	0	0
T27	854	0	0	0
T28	660	4	0	0
T29	1549	0	0	0
T30	5198	0	0	0
T31	453	0	0	0
T32	382	0	0	0
T33	358	0	0	0
T44	0	1	0	0
T47	0	3	0	0
T49	1247	1	0	0
T87	4403	0	0	0
T105	0	7	0	0
T122	0	1	0	0
T182	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T47,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	43310283	5506	0	0
CgEnOn_A	43310283	3232	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43310283	5506	0	0
T4	1360	1	0	0
T5	886	2	0	0
T6	697	7	0	0
T27	1707	1	0	0
T28	1321	5	0	0
T29	3098	1	0	0
T30	10398	1	0	0
T31	909	1	0	0
T32	763	1	0	0
T33	716	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43310283	3232	0	0
T5	886	1	0	0
T6	697	6	0	0
T21	0	5	0	0
T22	0	12	0	0
T27	1707	0	0	0
T28	1321	4	0	0
T29	3098	0	0	0
T30	10398	0	0	0
T31	909	0	0	0
T32	763	0	0	0
T33	716	0	0	0
T44	0	1	0	0
T47	0	3	0	0
T49	2494	1	0	0
T105	0	7	0	0
T182	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T47,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	88307846	5530	0	0
CgEnOn_A	88307846	3241	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88307846	5530	0	0
T4	2516	1	0	0
T5	1797	2	0	0
T6	1486	7	0	0
T27	3494	1	0	0
T28	2762	5	0	0
T29	6220	1	0	0
T30	18588	1	0	0
T31	1796	1	0	0
T32	1567	1	0	0
T33	1538	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	88307846	3241	0	0
T5	1797	1	0	0
T6	1486	6	0	0
T21	0	5	0	0
T22	0	12	0	0
T27	3494	0	0	0
T28	2762	4	0	0
T29	6220	0	0	0
T30	18588	0	0	0
T31	1796	0	0	0
T32	1567	0	0	0
T33	1538	0	0	0
T44	0	1	0	0
T47	0	3	0	0
T49	5054	1	0	0
T105	0	6	0	0
T182	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T47,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	47072987	5500	0	0
CgEnOn_A	47072987	3210	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47072987	5500	0	0
T4	1258	1	0	0
T5	899	2	0	0
T6	743	7	0	0
T27	1747	1	0	0
T28	1318	5	0	0
T29	3111	1	0	0
T30	9294	1	0	0
T31	897	1	0	0
T32	783	1	0	0
T33	769	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	47072987	3210	0	0
T5	899	1	0	0
T6	743	6	0	0
T21	0	5	0	0
T22	0	11	0	0
T27	1747	0	0	0
T28	1318	4	0	0
T29	3111	0	0	0
T30	9294	0	0	0
T31	897	0	0	0
T32	783	0	0	0
T33	769	0	0	0
T44	0	1	0	0
T47	0	3	0	0
T49	2527	1	0	0
T105	0	7	0	0
T182	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T47,T46
1	0	Covered	T5,T27,T29
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	98159591	2483	0	0
CgEnOn_A	98159591	2480	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98159591	2483	0	0
T5	1872	1	0	0
T6	1547	0	0	0
T21	0	5	0	0
T27	3639	1	0	0
T28	2783	5	0	0
T29	6480	4	0	0
T30	19364	0	0	0
T31	1870	0	0	0
T32	1632	0	0	0
T33	1602	0	0	0
T44	0	1	0	0
T47	0	5	0	0
T49	5265	1	0	0
T59	0	8	0	0
T60	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98159591	2480	0	0
T5	1872	1	0	0
T6	1547	0	0	0
T21	0	5	0	0
T27	3639	1	0	0
T28	2783	5	0	0
T29	6480	4	0	0
T30	19364	0	0	0
T31	1870	0	0	0
T32	1632	0	0	0
T33	1602	0	0	0
T44	0	1	0	0
T47	0	5	0	0
T49	5265	1	0	0
T59	0	8	0	0
T60	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T47,T46
1	0	Covered	T5,T27,T29
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	98159591	2512	0	0
CgEnOn_A	98159591	2509	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98159591	2512	0	0
T5	1872	1	0	0
T6	1547	0	0	0
T21	0	5	0	0
T27	3639	1	0	0
T28	2783	5	0	0
T29	6480	5	0	0
T30	19364	0	0	0
T31	1870	0	0	0
T32	1632	0	0	0
T33	1602	0	0	0
T44	0	1	0	0
T47	0	5	0	0
T49	5265	1	0	0
T59	0	8	0	0
T60	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98159591	2509	0	0
T5	1872	1	0	0
T6	1547	0	0	0
T21	0	5	0	0
T27	3639	1	0	0
T28	2783	5	0	0
T29	6480	5	0	0
T30	19364	0	0	0
T31	1870	0	0	0
T32	1632	0	0	0
T33	1602	0	0	0
T44	0	1	0	0
T47	0	5	0	0
T49	5265	1	0	0
T59	0	8	0	0
T60	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T47,T46
1	0	Covered	T5,T29,T49
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	98159591	2476	0	0
CgEnOn_A	98159591	2473	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98159591	2476	0	0
T5	1872	1	0	0
T6	1547	0	0	0
T21	0	5	0	0
T23	0	1	0	0
T27	3639	0	0	0
T28	2783	5	0	0
T29	6480	6	0	0
T30	19364	0	0	0
T31	1870	0	0	0
T32	1632	0	0	0
T33	1602	0	0	0
T44	0	1	0	0
T47	0	5	0	0
T49	5265	1	0	0
T59	0	2	0	0
T60	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98159591	2473	0	0
T5	1872	1	0	0
T6	1547	0	0	0
T21	0	5	0	0
T23	0	1	0	0
T27	3639	0	0	0
T28	2783	5	0	0
T29	6480	6	0	0
T30	19364	0	0	0
T31	1870	0	0	0
T32	1632	0	0	0
T33	1602	0	0	0
T44	0	1	0	0
T47	0	5	0	0
T49	5265	1	0	0
T59	0	2	0	0
T60	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T47,T46
1	0	Covered	T5,T27,T29
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	98159591	2485	0	0
CgEnOn_A	98159591	2482	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98159591	2485	0	0
T5	1872	1	0	0
T6	1547	0	0	0
T21	0	5	0	0
T27	3639	1	0	0
T28	2783	5	0	0
T29	6480	5	0	0
T30	19364	0	0	0
T31	1870	0	0	0
T32	1632	0	0	0
T33	1602	0	0	0
T44	0	1	0	0
T47	0	5	0	0
T49	5265	1	0	0
T59	0	4	0	0
T60	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98159591	2482	0	0
T5	1872	1	0	0
T6	1547	0	0	0
T21	0	5	0	0
T27	3639	1	0	0
T28	2783	5	0	0
T29	6480	5	0	0
T30	19364	0	0	0
T31	1870	0	0	0
T32	1632	0	0	0
T33	1602	0	0	0
T44	0	1	0	0
T47	0	5	0	0
T49	5265	1	0	0
T59	0	4	0	0
T60	0	9	0	0