Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	187608	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

430569

1

T4

3

T5

27

T27

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	185676	1			T4	4		T5	42		T28	18
values[0x0]	204683	1			T4	3		T5	23		T27	17
values[0x1]	227818	1			T4	6		T5	16		T27	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	130460	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

487717

1

T4

4

T5

32

T27

11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2002	1			T3	2		T129	1		T19	2
valid_sources[0x01]	2417	1			T74	2		T3	2		T128	2
valid_sources[0x02]	1993	1			T29	2		T177	1		T10	2
valid_sources[0x03]	2379	1			T5	2		T31	8		T40	2
valid_sources[0x04]	2001	1			T5	1		T33	1		T37	2
valid_sources[0x05]	2213	1			T32	6		T3	1		T10	5
valid_sources[0x06]	2375	1			T40	2		T3	1		T10	1
valid_sources[0x07]	2291	1			T10	2		T187	1		T11	2
valid_sources[0x08]	2538	1			T30	2		T37	2		T43	7
valid_sources[0x09]	2551	1			T5	1		T29	1		T40	1
valid_sources[0x0a]	2643	1			T29	4		T3	1		T184	1
valid_sources[0x0b]	2419	1			T4	1		T74	1		T10	4
valid_sources[0x0c]	2926	1			T30	5		T73	2		T10	2
valid_sources[0x0d]	2724	1			T31	2		T69	1		T127	1
valid_sources[0x0e]	2228	1			T31	5		T40	1		T73	2
valid_sources[0x0f]	2247	1			T5	1		T28	55		T29	2
valid_sources[0x10]	2103	1			T3	3		T10	1		T11	8
valid_sources[0x11]	2070	1			T10	4		T22	2		T11	5
valid_sources[0x12]	2572	1			T5	1		T129	1		T10	3
valid_sources[0x13]	2167	1			T73	3		T20	2		T187	2
valid_sources[0x14]	3534	1			T69	1		T3	1		T19	1
valid_sources[0x15]	2654	1			T5	1		T3	2		T10	2
valid_sources[0x16]	2182	1			T100	1		T19	1		T21	1
valid_sources[0x17]	2399	1			T31	11		T40	1		T43	1
valid_sources[0x18]	2138	1			T31	6		T1	7		T10	1
valid_sources[0x19]	2441	1			T31	3		T3	1		T116	1
valid_sources[0x1a]	2465	1			T69	1		T3	2		T100	1
valid_sources[0x1b]	2254	1			T73	1		T127	1		T100	2
valid_sources[0x1c]	2155	1			T49	1		T40	1		T100	2
valid_sources[0x1d]	2369	1			T5	3		T73	2		T3	1
valid_sources[0x1e]	2537	1			T5	1		T3	1		T10	3
valid_sources[0x1f]	2176	1			T29	4		T40	2		T69	2
valid_sources[0x20]	2324	1			T73	1		T3	1		T10	3
valid_sources[0x21]	2527	1			T5	2		T49	1		T37	2
valid_sources[0x22]	2364	1			T30	8		T49	2		T3	1
valid_sources[0x23]	1951	1			T5	1		T40	1		T116	1
valid_sources[0x24]	2146	1			T29	2		T40	1		T3	2
valid_sources[0x25]	2321	1			T27	7		T40	1		T184	2
valid_sources[0x26]	4043	1			T40	1		T3	1		T116	1
valid_sources[0x27]	2146	1			T4	1		T73	8		T184	2
valid_sources[0x28]	2367	1			T3	1		T10	7		T11	1
valid_sources[0x29]	2342	1			T1	7		T37	1		T3	1
valid_sources[0x2a]	2059	1			T5	4		T3	1		T177	1
valid_sources[0x2b]	2760	1			T3	1		T10	6		T21	2
valid_sources[0x2c]	1975	1			T2	2		T3	1		T100	8
valid_sources[0x2d]	2575	1			T1	6		T37	1		T40	1
valid_sources[0x2e]	2899	1			T29	5		T40	1		T3	1
valid_sources[0x2f]	2266	1			T3	1		T129	1		T10	7
valid_sources[0x30]	2601	1			T73	2		T3	1		T127	3
valid_sources[0x31]	2349	1			T40	1		T184	1		T10	7
valid_sources[0x32]	1909	1			T5	2		T3	2		T100	4
valid_sources[0x33]	2023	1			T37	1		T184	1		T10	3
valid_sources[0x34]	2373	1			T33	1		T3	2		T184	1
valid_sources[0x35]	2284	1			T69	1		T3	1		T184	1
valid_sources[0x36]	2190	1			T29	2		T69	1		T3	1
valid_sources[0x37]	1909	1			T70	7		T74	2		T3	2
valid_sources[0x38]	2709	1			T69	2		T3	1		T10	5
valid_sources[0x39]	2001	1			T40	1		T129	1		T10	2
valid_sources[0x3a]	2276	1			T10	4		T21	1		T11	3
valid_sources[0x3b]	2731	1			T37	3		T3	1		T19	1
valid_sources[0x3c]	2336	1			T40	1		T3	1		T127	1
valid_sources[0x3d]	2361	1			T37	1		T40	1		T3	4
valid_sources[0x3e]	2459	1			T29	1		T73	2		T3	1
valid_sources[0x3f]	2179	1			T3	1		T184	1		T10	3
valid_sources[0x40]	2470	1			T40	2		T177	1		T116	1
valid_sources[0x41]	2214	1			T29	1		T3	3		T100	2
valid_sources[0x42]	2457	1			T5	1		T184	1		T10	2
valid_sources[0x43]	2682	1			T32	4		T3	2		T177	1
valid_sources[0x44]	2759	1			T5	2		T29	3		T3	1
valid_sources[0x45]	2414	1			T3	1		T10	2		T187	2
valid_sources[0x46]	2355	1			T29	1		T40	1		T3	2
valid_sources[0x47]	2869	1			T40	3		T10	1		T11	2
valid_sources[0x48]	2470	1			T29	1		T30	1		T3	1
valid_sources[0x49]	2167	1			T5	1		T3	3		T184	1
valid_sources[0x4a]	2153	1			T37	3		T2	6		T69	1
valid_sources[0x4b]	2231	1			T5	1		T40	1		T3	1
valid_sources[0x4c]	2685	1			T73	4		T129	1		T10	1
valid_sources[0x4d]	2680	1			T31	2		T3	2		T116	1
valid_sources[0x4e]	2493	1			T49	1		T3	1		T19	1
valid_sources[0x4f]	2427	1			T5	2		T33	1		T116	1
valid_sources[0x50]	2213	1			T73	1		T3	2		T19	1
valid_sources[0x51]	2556	1			T27	8		T3	1		T100	2
valid_sources[0x52]	2957	1			T5	2		T3	2		T10	2
valid_sources[0x53]	2255	1			T27	11		T10	2		T187	1
valid_sources[0x54]	1996	1			T43	1		T3	1		T116	1
valid_sources[0x55]	1923	1			T5	1		T40	3		T73	2
valid_sources[0x56]	2949	1			T33	1		T40	1		T100	1
valid_sources[0x57]	2168	1			T5	2		T73	2		T19	2
valid_sources[0x58]	2576	1			T40	1		T3	2		T127	2
valid_sources[0x59]	2863	1			T31	2		T1	6		T37	1
valid_sources[0x5a]	2419	1			T49	1		T10	3		T26	2
valid_sources[0x5b]	2225	1			T37	1		T73	1		T3	1
valid_sources[0x5c]	2317	1			T37	1		T73	2		T116	1
valid_sources[0x5d]	2286	1			T3	4		T177	1		T19	1
valid_sources[0x5e]	1933	1			T31	2		T73	1		T3	3
valid_sources[0x5f]	2194	1			T29	6		T32	2		T73	2
valid_sources[0x60]	2427	1			T3	1		T10	3		T185	3
valid_sources[0x61]	2257	1			T74	2		T116	1		T19	1
valid_sources[0x62]	2057	1			T29	1		T3	1		T10	3
valid_sources[0x63]	2425	1			T3	1		T100	3		T129	1
valid_sources[0x64]	2015	1			T70	2		T73	4		T3	2
valid_sources[0x65]	1929	1			T40	1		T184	1		T100	6
valid_sources[0x66]	3089	1			T31	7		T2	1		T3	1
valid_sources[0x67]	1948	1			T43	2		T3	1		T10	5
valid_sources[0x68]	2257	1			T3	1		T10	1		T25	2
valid_sources[0x69]	2655	1			T29	1		T100	3		T19	1
valid_sources[0x6a]	2067	1			T2	2		T184	1		T10	3
valid_sources[0x6b]	2278	1			T5	5		T32	3		T3	1
valid_sources[0x6c]	1857	1			T5	1		T73	1		T3	1
valid_sources[0x6d]	2668	1			T29	1		T40	1		T3	2
valid_sources[0x6e]	2434	1			T73	8		T3	1		T10	5
valid_sources[0x6f]	2262	1			T127	3		T19	1		T187	1
valid_sources[0x70]	2096	1			T72	1		T10	1		T130	1
valid_sources[0x71]	2487	1			T29	2		T127	1		T10	3
valid_sources[0x72]	2307	1			T10	1		T24	3		T130	2
valid_sources[0x73]	2664	1			T37	2		T40	1		T2	5
valid_sources[0x74]	2672	1			T31	1		T72	1		T73	1
valid_sources[0x75]	2839	1			T3	1		T10	3		T20	1
valid_sources[0x76]	2062	1			T32	1		T40	2		T116	1
valid_sources[0x77]	2755	1			T37	1		T184	1		T10	4
valid_sources[0x78]	1948	1			T73	1		T127	7		T10	2
valid_sources[0x79]	2344	1			T40	3		T41	61		T3	2
valid_sources[0x7a]	2207	1			T3	6		T184	1		T129	1
valid_sources[0x7b]	2096	1			T73	2		T3	2		T10	2
valid_sources[0x7c]	2202	1			T185	1		T11	3		T156	1
valid_sources[0x7d]	3122	1			T3	2		T128	2		T10	4
valid_sources[0x7e]	2961	1			T3	1		T127	3		T10	1
valid_sources[0x7f]	2715	1			T3	1		T100	3		T10	4
valid_sources[0x80]	2748	1			T73	3		T3	1		T10	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

122745

1

T4

2

T5

17

T28

8

values[0x0]

all_enables

biggest_size

164543

1

T4

1

T5

7

T27

5

values[0x1]

all_enables

biggest_size

143281

1

T5

3

T27

3

T28

1