Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T27
0	1	Covered	T27,T177,T25
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T37
1	0	Covered	T6,T38,T44
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	141583410	7496	0	0
GateOpen_A	141583410	13552	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141583410	7496	0	0
T5	13825	4	0	0
T6	3407	4	0	0
T27	6022	40	0	0
T28	10721	0	0	0
T29	7488	0	0	0
T30	11186	0	0	0
T31	42985	0	0	0
T32	28828	0	0	0
T33	9494	0	0	0
T38	0	15	0	0
T39	0	4	0	0
T40	0	4	0	0
T44	0	3	0	0
T49	3139	0	0	0
T98	0	17	0	0
T100	0	1	0	0
T177	0	16	0	0
T178	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	141583410	13552	0	0
T1	0	4	0	0
T4	17627	4	0	0
T5	13825	4	0	0
T6	3407	8	0	0
T27	6022	44	0	0
T28	10721	0	0	0
T29	7488	0	0	0
T30	11186	0	0	0
T31	42985	4	0	0
T32	28828	4	0	0
T33	9494	0	0	0
T37	0	204	0	0
T38	0	19	0	0
T39	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T27
0	1	Covered	T27,T177,T25
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T37
1	0	Covered	T6,T38,T44
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	15213117	1803	0	0
GateOpen_A	15213117	3315	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15213117	1803	0	0
T5	1528	1	0	0
T6	365	1	0	0
T27	663	8	0	0
T28	1238	0	0	0
T29	824	0	0	0
T30	1359	0	0	0
T31	4765	0	0	0
T32	3359	0	0	0
T33	1088	0	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T49	329	0	0	0
T98	0	4	0	0
T177	0	3	0	0
T178	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15213117	3315	0	0
T1	0	1	0	0
T4	2013	1	0	0
T5	1528	1	0	0
T6	365	2	0	0
T27	663	9	0	0
T28	1238	0	0	0
T29	824	0	0	0
T30	1359	0	0	0
T31	4765	1	0	0
T32	3359	1	0	0
T33	1088	0	0	0
T37	0	51	0	0
T38	0	4	0	0
T39	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T27
0	1	Covered	T27,T177,T25
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T37
1	0	Covered	T6,T38,T44
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	30426603	1898	0	0
GateOpen_A	30426603	3410	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30426603	1898	0	0
T5	3055	1	0	0
T6	729	1	0	0
T27	1325	9	0	0
T28	2476	0	0	0
T29	1647	0	0	0
T30	2720	0	0	0
T31	9530	0	0	0
T32	6717	0	0	0
T33	2176	0	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T49	658	0	0	0
T98	0	4	0	0
T177	0	4	0	0
T178	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30426603	3410	0	0
T1	0	1	0	0
T4	4026	1	0	0
T5	3055	1	0	0
T6	729	2	0	0
T27	1325	10	0	0
T28	2476	0	0	0
T29	1647	0	0	0
T30	2720	0	0	0
T31	9530	1	0	0
T32	6717	1	0	0
T33	2176	0	0	0
T37	0	51	0	0
T38	0	4	0	0
T39	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T27
0	1	Covered	T27,T177,T25
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T37
1	0	Covered	T6,T38,T44
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	62669510	1892	0	0
GateOpen_A	62669510	3408	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62669510	1892	0	0
T5	6161	1	0	0
T6	1551	1	0	0
T27	2689	12	0	0
T28	4671	0	0	0
T29	3344	0	0	0
T30	4738	0	0	0
T31	19126	0	0	0
T32	12501	0	0	0
T33	4153	0	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T49	1435	0	0	0
T98	0	4	0	0
T177	0	4	0	0
T178	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62669510	3408	0	0
T1	0	1	0	0
T4	7725	1	0	0
T5	6161	1	0	0
T6	1551	2	0	0
T27	2689	13	0	0
T28	4671	0	0	0
T29	3344	0	0	0
T30	4738	0	0	0
T31	19126	1	0	0
T32	12501	1	0	0
T33	4153	0	0	0
T37	0	51	0	0
T38	0	4	0	0
T39	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T27
0	1	Covered	T27,T177,T25
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T37
1	0	Covered	T6,T38,T98
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	33274180	1903	0	0
GateOpen_A	33274180	3419	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33274180	1903	0	0
T5	3081	1	0	0
T6	762	1	0	0
T27	1345	11	0	0
T28	2336	0	0	0
T29	1673	0	0	0
T30	2369	0	0	0
T31	9564	0	0	0
T32	6251	0	0	0
T33	2077	0	0	0
T38	0	6	0	0
T39	0	1	0	0
T40	0	1	0	0
T49	717	0	0	0
T98	0	5	0	0
T100	0	1	0	0
T177	0	5	0	0
T178	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33274180	3419	0	0
T1	0	1	0	0
T4	3863	1	0	0
T5	3081	1	0	0
T6	762	2	0	0
T27	1345	12	0	0
T28	2336	0	0	0
T29	1673	0	0	0
T30	2369	0	0	0
T31	9564	1	0	0
T32	6251	1	0	0
T33	2077	0	0	0
T37	0	51	0	0
T38	0	7	0	0
T39	0	2	0	0