Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	158412190	24508	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	158412190	24508	0	0
T7	248725	86	0	0
T8	0	50	0	0
T9	0	131	0	0
T10	312295	0	0	0
T12	0	288	0	0
T13	0	44	0	0
T14	0	147	0	0
T15	0	90	0	0
T16	0	282	0	0
T17	0	452	0	0
T18	0	86	0	0
T19	47730	0	0	0
T20	9045	0	0	0
T21	7645	0	0	0
T22	4435	0	0	0
T23	26550	0	0	0
T24	12580	0	0	0
T25	5885	0	0	0
T26	8260	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	31682438	3632	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31682438	3632	0	0
T7	49745	14	0	0
T8	0	8	0	0
T9	0	20	0	0
T10	62459	0	0	0
T12	0	37	0	0
T13	0	7	0	0
T14	0	24	0	0
T15	0	12	0	0
T16	0	41	0	0
T17	0	60	0	0
T18	0	14	0	0
T19	9546	0	0	0
T20	1809	0	0	0
T21	1529	0	0	0
T22	887	0	0	0
T23	5310	0	0	0
T24	2516	0	0	0
T25	1177	0	0	0
T26	1652	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	31682438	3556	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31682438	3556	0	0
T7	49745	13	0	0
T8	0	8	0	0
T9	0	21	0	0
T10	62459	0	0	0
T12	0	37	0	0
T13	0	7	0	0
T14	0	23	0	0
T15	0	12	0	0
T16	0	41	0	0
T17	0	59	0	0
T18	0	14	0	0
T19	9546	0	0	0
T20	1809	0	0	0
T21	1529	0	0	0
T22	887	0	0	0
T23	5310	0	0	0
T24	2516	0	0	0
T25	1177	0	0	0
T26	1652	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	31682438	4939	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31682438	4939	0	0
T7	49745	17	0	0
T8	0	10	0	0
T9	0	27	0	0
T10	62459	0	0	0
T12	0	59	0	0
T13	0	9	0	0
T14	0	30	0	0
T15	0	17	0	0
T16	0	58	0	0
T17	0	92	0	0
T18	0	17	0	0
T19	9546	0	0	0
T20	1809	0	0	0
T21	1529	0	0	0
T22	887	0	0	0
T23	5310	0	0	0
T24	2516	0	0	0
T25	1177	0	0	0
T26	1652	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	31682438	4928	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31682438	4928	0	0
T7	49745	18	0	0
T8	0	10	0	0
T9	0	27	0	0
T10	62459	0	0	0
T12	0	60	0	0
T13	0	9	0	0
T14	0	30	0	0
T15	0	18	0	0
T16	0	56	0	0
T17	0	91	0	0
T18	0	19	0	0
T19	9546	0	0	0
T20	1809	0	0	0
T21	1529	0	0	0
T22	887	0	0	0
T23	5310	0	0	0
T24	2516	0	0	0
T25	1177	0	0	0
T26	1652	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	31682438	7453	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31682438	7453	0	0
T7	49745	24	0	0
T8	0	14	0	0
T9	0	36	0	0
T10	62459	0	0	0
T12	0	95	0	0
T13	0	12	0	0
T14	0	40	0	0
T15	0	31	0	0
T16	0	86	0	0
T17	0	150	0	0
T18	0	22	0	0
T19	9546	0	0	0
T20	1809	0	0	0
T21	1529	0	0	0
T22	887	0	0	0
T23	5310	0	0	0
T24	2516	0	0	0
T25	1177	0	0	0
T26	1652	0	0	0