Line Coverage for Module :
prim_generic_clock_div ( parameter Divisor=2,ResetValue=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 5 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| ALWAYS | 55 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
26 logic step_down_req;
27 1/1 assign step_down_req = test_en_i ? '0 : step_down_req_i;
Tests: T4 T5 T27
28
29 logic clk_int;
30 logic clk_muxed;
31
32 if (Divisor == 2) begin : gen_div2
33 logic q_p, q_n;
34
35 prim_flop # (
36 .Width(1),
37 .ResetValue(ResetValue)
38 ) u_div2 (
39 .clk_i,
40 .rst_ni,
41 .d_i(q_n),
42 .q_o(q_p)
43 );
44
45 prim_clock_inv # (
46 .HasScanMode(1'b0)
47 ) u_inv (
48 .clk_i(q_p),
49 .scanmode_i('0),
50 .clk_no(q_n)
51 );
52
53 logic step_down_nq;
54 always_ff @(negedge clk_i or negedge rst_ni) begin
55 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
56 1/1 step_down_nq <= 1'b0;
Tests: T4 T5 T6
57 end else begin
58 1/1 step_down_nq <= step_down_req;
Tests: T4 T5 T6
59 end
60 end
61
62 // make sure selection point is away from both edges
63 prim_clock_mux2 #(
64 .NoFpgaBufG(1'b1)
65 ) u_step_down_mux (
66 .clk0_i(q_p),
67 .clk1_i(clk_i),
68 .sel_i(step_down_nq),
69 .clk_o(clk_int)
70 );
71
72 1/1 assign step_down_ack_o = step_down_nq;
Tests: T4 T28 T30
Line Coverage for Module :
prim_generic_clock_div ( parameter Divisor=4,ResetValue=0,gen_div.ToggleCnt=2,gen_div.CntWidth=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 12 | 12 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| ALWAYS | 85 | 7 | 7 | 100.00 |
| ALWAYS | 97 | 3 | 3 | 100.00 |
26 logic step_down_req;
27 1/1 assign step_down_req = test_en_i ? '0 : step_down_req_i;
Tests: T4 T5 T27
28
29 logic clk_int;
30 logic clk_muxed;
31
32 if (Divisor == 2) begin : gen_div2
33 logic q_p, q_n;
34
35 prim_flop # (
36 .Width(1),
37 .ResetValue(ResetValue)
38 ) u_div2 (
39 .clk_i,
40 .rst_ni,
41 .d_i(q_n),
42 .q_o(q_p)
43 );
44
45 prim_clock_inv # (
46 .HasScanMode(1'b0)
47 ) u_inv (
48 .clk_i(q_p),
49 .scanmode_i('0),
50 .clk_no(q_n)
51 );
52
53 logic step_down_nq;
54 always_ff @(negedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 step_down_nq <= 1'b0;
57 end else begin
58 step_down_nq <= step_down_req;
59 end
60 end
61
62 // make sure selection point is away from both edges
63 prim_clock_mux2 #(
64 .NoFpgaBufG(1'b1)
65 ) u_step_down_mux (
66 .clk0_i(q_p),
67 .clk1_i(clk_i),
68 .sel_i(step_down_nq),
69 .clk_o(clk_int)
70 );
71
72 assign step_down_ack_o = step_down_nq;
73
74 end else begin : gen_div
75
76 localparam int unsigned ToggleCnt = Divisor / 2;
77 localparam int unsigned CntWidth = $clog2(ToggleCnt);
78 logic [CntWidth-1:0] cnt;
79 logic [CntWidth-1:0] limit;
80
81 1/1 assign limit = !step_down_req ? CntWidth'(ToggleCnt - 1) :
Tests: T4 T28 T30
82 (ToggleCnt / 2) == 2 ? '0 : CntWidth'((ToggleCnt / 2) - 1);
83
84 always_ff @(posedge clk_i or negedge rst_ni) begin
85 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
86 1/1 cnt <= '0;
Tests: T4 T5 T6
87 1/1 clk_int <= ResetValue;
Tests: T4 T5 T6
88 1/1 end else if (cnt >= limit) begin
Tests: T4 T5 T6
89 1/1 cnt <= '0;
Tests: T4 T5 T6
90 1/1 clk_int <= ~clk_muxed;
Tests: T4 T5 T6
91 end else begin
92 1/1 cnt <= cnt + 1'b1;
Tests: T4 T5 T6
93 end
94 end
95
96 always_ff @(posedge clk_i or negedge rst_ni) begin
97 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
98 1/1 step_down_ack_o <= 1'b0;
Tests: T4 T5 T6
99 end else begin
100 1/1 step_down_ack_o <= step_down_req;
Tests: T4 T5 T6
Cond Coverage for Module :
prim_generic_clock_div ( parameter Divisor=2,ResetValue=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 27
EXPRESSION (test_en_i ? '0 : step_down_req_i)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T27 |
Cond Coverage for Module :
prim_generic_clock_div ( parameter Divisor=4,ResetValue=0,gen_div.ToggleCnt=2,gen_div.CntWidth=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 27
EXPRESSION (test_en_i ? '0 : step_down_req_i)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T27 |
LINE 81
EXPRESSION (((!step_down_req)) ? (1'((gen_div.ToggleCnt - 1))) : ((((gen_div.ToggleCnt / 2) == 2) ? '0 : 1'(((gen_div.ToggleCnt / 2) - 1)))))
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T28,T30 |
| 1 | Covered | T4,T5,T6 |
Branch Coverage for Module :
prim_generic_clock_div ( parameter Divisor=2,ResetValue=0 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| TERNARY |
27 |
2 |
2 |
100.00 |
| IF |
55 |
2 |
2 |
100.00 |
27 assign step_down_req = test_en_i ? '0 : step_down_req_i;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T27 |
| 0 |
Covered |
T4,T5,T6 |
55 if (!rst_ni) begin
-1-
56 step_down_nq <= 1'b0;
==>
57 end else begin
58 step_down_nq <= step_down_req;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Branch Coverage for Module :
prim_generic_clock_div ( parameter Divisor=4,ResetValue=0,gen_div.ToggleCnt=2,gen_div.CntWidth=1 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
9 |
9 |
100.00 |
| TERNARY |
27 |
2 |
2 |
100.00 |
| TERNARY |
81 |
2 |
2 |
100.00 |
| IF |
85 |
3 |
3 |
100.00 |
| IF |
97 |
2 |
2 |
100.00 |
27 assign step_down_req = test_en_i ? '0 : step_down_req_i;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T27 |
| 0 |
Covered |
T4,T5,T6 |
81 assign limit = !step_down_req ? CntWidth'(ToggleCnt - 1) :
82 (ToggleCnt / 2) == 2 ? '0 : CntWidth'((ToggleCnt / 2) - 1);
ID LINE
-1- 81 (!step_down_req)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T28,T30 |
85 if (!rst_ni) begin
-1-
86 cnt <= '0;
==>
87 clk_int <= ResetValue;
88 end else if (cnt >= limit) begin
-2-
89 cnt <= '0;
==>
90 clk_int <= ~clk_muxed;
91 end else begin
92 cnt <= cnt + 1'b1;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T4,T5,T6 |
| 0 |
0 |
Covered |
T4,T5,T6 |
97 if (!rst_ni) begin
-1-
98 step_down_ack_o <= 1'b0;
==>
99 end else begin
100 step_down_ack_o <= step_down_req;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Module :
prim_generic_clock_div
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
DivEven_A |
1596 |
1596 |
0 |
0 |
DivEven_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1596 |
1596 |
0 |
0 |
| T4 |
2 |
2 |
0 |
0 |
| T5 |
2 |
2 |
0 |
0 |
| T6 |
2 |
2 |
0 |
0 |
| T27 |
2 |
2 |
0 |
0 |
| T28 |
2 |
2 |
0 |
0 |
| T29 |
2 |
2 |
0 |
0 |
| T30 |
2 |
2 |
0 |
0 |
| T31 |
2 |
2 |
0 |
0 |
| T32 |
2 |
2 |
0 |
0 |
| T33 |
2 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 5 | 5 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| ALWAYS | 55 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
26 logic step_down_req;
27 1/1 assign step_down_req = test_en_i ? '0 : step_down_req_i;
Tests: T4 T5 T27
28
29 logic clk_int;
30 logic clk_muxed;
31
32 if (Divisor == 2) begin : gen_div2
33 logic q_p, q_n;
34
35 prim_flop # (
36 .Width(1),
37 .ResetValue(ResetValue)
38 ) u_div2 (
39 .clk_i,
40 .rst_ni,
41 .d_i(q_n),
42 .q_o(q_p)
43 );
44
45 prim_clock_inv # (
46 .HasScanMode(1'b0)
47 ) u_inv (
48 .clk_i(q_p),
49 .scanmode_i('0),
50 .clk_no(q_n)
51 );
52
53 logic step_down_nq;
54 always_ff @(negedge clk_i or negedge rst_ni) begin
55 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
56 1/1 step_down_nq <= 1'b0;
Tests: T4 T5 T6
57 end else begin
58 1/1 step_down_nq <= step_down_req;
Tests: T4 T5 T6
59 end
60 end
61
62 // make sure selection point is away from both edges
63 prim_clock_mux2 #(
64 .NoFpgaBufG(1'b1)
65 ) u_step_down_mux (
66 .clk0_i(q_p),
67 .clk1_i(clk_i),
68 .sel_i(step_down_nq),
69 .clk_o(clk_int)
70 );
71
72 1/1 assign step_down_ack_o = step_down_nq;
Tests: T4 T28 T30
Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 27
EXPRESSION (test_en_i ? '0 : step_down_req_i)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T27 |
Branch Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
4 |
4 |
100.00 |
| TERNARY |
27 |
2 |
2 |
100.00 |
| IF |
55 |
2 |
2 |
100.00 |
27 assign step_down_req = test_en_i ? '0 : step_down_req_i;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T27 |
| 0 |
Covered |
T4,T5,T6 |
55 if (!rst_ni) begin
-1-
56 step_down_nq <= 1'b0;
==>
57 end else begin
58 step_down_nq <= step_down_req;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
DivEven_A |
798 |
798 |
0 |
0 |
DivEven_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
798 |
798 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T27 |
1 |
1 |
0 |
0 |
| T28 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T31 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 12 | 12 | 100.00 |
| CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
| ALWAYS | 85 | 7 | 7 | 100.00 |
| ALWAYS | 97 | 3 | 3 | 100.00 |
26 logic step_down_req;
27 1/1 assign step_down_req = test_en_i ? '0 : step_down_req_i;
Tests: T4 T5 T27
28
29 logic clk_int;
30 logic clk_muxed;
31
32 if (Divisor == 2) begin : gen_div2
33 logic q_p, q_n;
34
35 prim_flop # (
36 .Width(1),
37 .ResetValue(ResetValue)
38 ) u_div2 (
39 .clk_i,
40 .rst_ni,
41 .d_i(q_n),
42 .q_o(q_p)
43 );
44
45 prim_clock_inv # (
46 .HasScanMode(1'b0)
47 ) u_inv (
48 .clk_i(q_p),
49 .scanmode_i('0),
50 .clk_no(q_n)
51 );
52
53 logic step_down_nq;
54 always_ff @(negedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 step_down_nq <= 1'b0;
57 end else begin
58 step_down_nq <= step_down_req;
59 end
60 end
61
62 // make sure selection point is away from both edges
63 prim_clock_mux2 #(
64 .NoFpgaBufG(1'b1)
65 ) u_step_down_mux (
66 .clk0_i(q_p),
67 .clk1_i(clk_i),
68 .sel_i(step_down_nq),
69 .clk_o(clk_int)
70 );
71
72 assign step_down_ack_o = step_down_nq;
73
74 end else begin : gen_div
75
76 localparam int unsigned ToggleCnt = Divisor / 2;
77 localparam int unsigned CntWidth = $clog2(ToggleCnt);
78 logic [CntWidth-1:0] cnt;
79 logic [CntWidth-1:0] limit;
80
81 1/1 assign limit = !step_down_req ? CntWidth'(ToggleCnt - 1) :
Tests: T4 T28 T30
82 (ToggleCnt / 2) == 2 ? '0 : CntWidth'((ToggleCnt / 2) - 1);
83
84 always_ff @(posedge clk_i or negedge rst_ni) begin
85 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
86 1/1 cnt <= '0;
Tests: T4 T5 T6
87 1/1 clk_int <= ResetValue;
Tests: T4 T5 T6
88 1/1 end else if (cnt >= limit) begin
Tests: T4 T5 T6
89 1/1 cnt <= '0;
Tests: T4 T5 T6
90 1/1 clk_int <= ~clk_muxed;
Tests: T4 T5 T6
91 end else begin
92 1/1 cnt <= cnt + 1'b1;
Tests: T4 T5 T6
93 end
94 end
95
96 always_ff @(posedge clk_i or negedge rst_ni) begin
97 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
98 1/1 step_down_ack_o <= 1'b0;
Tests: T4 T5 T6
99 end else begin
100 1/1 step_down_ack_o <= step_down_req;
Tests: T4 T5 T6
Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic
| Total | Covered | Percent |
|---|
| Conditions | 4 | 4 | 100.00 |
| Logical | 4 | 4 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 27
EXPRESSION (test_en_i ? '0 : step_down_req_i)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T27 |
LINE 81
EXPRESSION (((!step_down_req)) ? (1'((gen_div.ToggleCnt - 1))) : ((((gen_div.ToggleCnt / 2) == 2) ? '0 : 1'(((gen_div.ToggleCnt / 2) - 1)))))
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T28,T30 |
| 1 | Covered | T4,T5,T6 |
Branch Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
| Branches |
|
9 |
9 |
100.00 |
| TERNARY |
27 |
2 |
2 |
100.00 |
| TERNARY |
81 |
2 |
2 |
100.00 |
| IF |
85 |
3 |
3 |
100.00 |
| IF |
97 |
2 |
2 |
100.00 |
27 assign step_down_req = test_en_i ? '0 : step_down_req_i;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T27 |
| 0 |
Covered |
T4,T5,T6 |
81 assign limit = !step_down_req ? CntWidth'(ToggleCnt - 1) :
82 (ToggleCnt / 2) == 2 ? '0 : CntWidth'((ToggleCnt / 2) - 1);
ID LINE
-1- 81 (!step_down_req)
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T28,T30 |
85 if (!rst_ni) begin
-1-
86 cnt <= '0;
==>
87 clk_int <= ResetValue;
88 end else if (cnt >= limit) begin
-2-
89 cnt <= '0;
==>
90 clk_int <= ~clk_muxed;
91 end else begin
92 cnt <= cnt + 1'b1;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T4,T5,T6 |
| 0 |
0 |
Covered |
T4,T5,T6 |
97 if (!rst_ni) begin
-1-
98 step_down_ack_o <= 1'b0;
==>
99 end else begin
100 step_down_ack_o <= step_down_req;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
DivEven_A |
798 |
798 |
0 |
0 |
DivEven_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
798 |
798 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T27 |
1 |
1 |
0 |
0 |
| T28 |
1 |
1 |
0 |
0 |
| T29 |
1 |
1 |
0 |
0 |
| T30 |
1 |
1 |
0 |
0 |
| T31 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |