Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

22                      
23         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T37,T73,T19

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	31682438	28975189	0	0
AllClkBypReqTrue_A	31682438	88730	0	0
IoClkBypReqFalse_A	31682438	28915473	0	2394
IoClkBypReqTrue_A	31682438	144076	0	0
LcClkBypAckFalse_A	31682438	28981151	0	0
LcClkBypAckTrue_A	31682438	82768	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31682438	28975189	0	0
T4	1287	1196	0	0
T5	1797	1765	0	0
T6	1623	1424	0	0
T27	1400	1343	0	0
T28	2286	1992	0	0
T29	3310	3162	0	0
T30	2072	1737	0	0
T31	2391	2379	0	0
T32	1563	1491	0	0
T33	1037	898	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31682438	88730	0	0
T4	1287	72	0	0
T5	1797	0	0	0
T6	1623	0	0	0
T27	1400	0	0	0
T28	2286	213	0	0
T29	3310	0	0	0
T30	2072	293	0	0
T31	2391	0	0	0
T32	1563	53	0	0
T33	1037	98	0	0
T41	0	226	0	0
T43	0	150	0	0
T69	0	105	0	0
T70	0	20	0	0
T73	0	323	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31682438	28915473	0	2394
T4	1287	1144	0	3
T5	1797	1763	0	3
T6	1623	1422	0	3
T27	1400	1341	0	3
T28	2286	2203	0	3
T29	3310	3160	0	3
T30	2072	1560	0	3
T31	2391	2377	0	3
T32	1563	1241	0	3
T33	1037	889	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31682438	144076	0	0
T4	1287	122	0	0
T5	1797	0	0	0
T6	1623	0	0	0
T27	1400	0	0	0
T28	2286	0	0	0
T29	3310	0	0	0
T30	2072	468	0	0
T31	2391	0	0	0
T32	1563	301	0	0
T33	1037	105	0	0
T41	0	400	0	0
T43	0	165	0	0
T68	0	252	0	0
T70	0	36	0	0
T73	0	589	0	0
T74	0	44	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31682438	28981151	0	0
T4	1287	1211	0	0
T5	1797	1765	0	0
T6	1623	1424	0	0
T27	1400	1343	0	0
T28	2286	2205	0	0
T29	3310	3162	0	0
T30	2072	1805	0	0
T31	2391	2379	0	0
T32	1563	1423	0	0
T33	1037	938	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31682438	82768	0	0
T4	1287	57	0	0
T5	1797	0	0	0
T6	1623	0	0	0
T27	1400	0	0	0
T28	2286	0	0	0
T29	3310	0	0	0
T30	2072	225	0	0
T31	2391	0	0	0
T32	1563	121	0	0
T33	1037	58	0	0
T41	0	182	0	0
T43	0	72	0	0
T68	0	109	0	0
T70	0	29	0	0
T73	0	362	0	0
T127	0	212	0	0