Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	277100712	9443	0	0
TransStop_A	277100712	4802	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	277100712	9443	0	0
T5	25672	4	0	0
T6	6372	0	0	0
T27	11204	0	0	0
T28	19460	0	0	0
T29	13936	30	0	0
T30	19744	0	0	0
T31	79692	23	0	0
T32	52088	0	0	0
T33	17304	0	0	0
T40	0	4	0	0
T42	0	12	0	0
T49	5980	0	0	0
T71	0	13	0	0
T73	0	21	0	0
T100	0	4	0	0
T128	0	8	0	0
T129	0	11	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	277100712	4802	0	0
T5	25672	4	0	0
T6	6372	0	0	0
T21	0	4	0	0
T27	11204	0	0	0
T28	19460	0	0	0
T29	13936	20	0	0
T30	19744	0	0	0
T31	79692	18	0	0
T32	52088	0	0	0
T33	17304	0	0	0
T40	0	4	0	0
T42	0	8	0	0
T49	5980	0	0	0
T71	0	4	0	0
T73	0	16	0	0
T100	0	4	0	0
T128	0	2	0	0
T129	0	7	0	0
T130	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	69275178	2396	0	0
TransStop_A	69275178	1226	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69275178	2396	0	0
T5	6418	1	0	0
T6	1593	0	0	0
T27	2801	0	0	0
T28	4865	0	0	0
T29	3484	6	0	0
T30	4936	0	0	0
T31	19923	5	0	0
T32	13022	0	0	0
T33	4326	0	0	0
T40	0	1	0	0
T42	0	4	0	0
T49	1495	0	0	0
T71	0	2	0	0
T73	0	3	0	0
T100	0	1	0	0
T128	0	4	0	0
T129	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69275178	1226	0	0
T5	6418	1	0	0
T6	1593	0	0	0
T21	0	1	0	0
T27	2801	0	0	0
T28	4865	0	0	0
T29	3484	4	0	0
T30	4936	0	0	0
T31	19923	4	0	0
T32	13022	0	0	0
T33	4326	0	0	0
T40	0	1	0	0
T42	0	3	0	0
T49	1495	0	0	0
T73	0	3	0	0
T100	0	1	0	0
T128	0	1	0	0
T130	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	69275178	2321	0	0
TransStop_A	69275178	1195	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69275178	2321	0	0
T5	6418	1	0	0
T6	1593	0	0	0
T27	2801	0	0	0
T28	4865	0	0	0
T29	3484	8	0	0
T30	4936	0	0	0
T31	19923	5	0	0
T32	13022	0	0	0
T33	4326	0	0	0
T40	0	1	0	0
T42	0	3	0	0
T49	1495	0	0	0
T71	0	4	0	0
T73	0	5	0	0
T100	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69275178	1195	0	0
T5	6418	1	0	0
T6	1593	0	0	0
T21	0	1	0	0
T27	2801	0	0	0
T28	4865	0	0	0
T29	3484	7	0	0
T30	4936	0	0	0
T31	19923	5	0	0
T32	13022	0	0	0
T33	4326	0	0	0
T40	0	1	0	0
T42	0	3	0	0
T49	1495	0	0	0
T71	0	2	0	0
T73	0	3	0	0
T100	0	1	0	0
T130	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	69275178	2391	0	0
TransStop_A	69275178	1227	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69275178	2391	0	0
T5	6418	1	0	0
T6	1593	0	0	0
T27	2801	0	0	0
T28	4865	0	0	0
T29	3484	8	0	0
T30	4936	0	0	0
T31	19923	9	0	0
T32	13022	0	0	0
T33	4326	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T49	1495	0	0	0
T71	0	4	0	0
T73	0	7	0	0
T100	0	1	0	0
T128	0	2	0	0
T129	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69275178	1227	0	0
T5	6418	1	0	0
T6	1593	0	0	0
T21	0	1	0	0
T27	2801	0	0	0
T28	4865	0	0	0
T29	3484	6	0	0
T30	4936	0	0	0
T31	19923	6	0	0
T32	13022	0	0	0
T33	4326	0	0	0
T40	0	1	0	0
T49	1495	0	0	0
T71	0	1	0	0
T73	0	5	0	0
T100	0	1	0	0
T128	0	1	0	0
T129	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	69275178	2335	0	0
TransStop_A	69275178	1154	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69275178	2335	0	0
T5	6418	1	0	0
T6	1593	0	0	0
T27	2801	0	0	0
T28	4865	0	0	0
T29	3484	8	0	0
T30	4936	0	0	0
T31	19923	4	0	0
T32	13022	0	0	0
T33	4326	0	0	0
T40	0	1	0	0
T42	0	3	0	0
T49	1495	0	0	0
T71	0	3	0	0
T73	0	6	0	0
T100	0	1	0	0
T128	0	1	0	0
T129	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69275178	1154	0	0
T5	6418	1	0	0
T6	1593	0	0	0
T21	0	1	0	0
T27	2801	0	0	0
T28	4865	0	0	0
T29	3484	3	0	0
T30	4936	0	0	0
T31	19923	3	0	0
T32	13022	0	0	0
T33	4326	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T49	1495	0	0	0
T71	0	1	0	0
T73	0	5	0	0
T100	0	1	0	0
T129	0	4	0	0