Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	32585367	459288	0	0
clk_enables_rd_A	32585367	8916	0	0
clk_hints_rd_A	32585367	8507	0	0
extclk_ctrl_rd_A	32585367	13664	0	0
extclk_ctrl_regwen_rd_A	32585367	7756	0	0
jitter_enable_rd_A	32585367	19310	0	0
jitter_regwen_rd_A	32585367	7811	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32585367	459288	0	0
T36	146380	4508	0	0
T50	0	7252	0	0
T51	0	3389	0	0
T52	0	4329	0	0
T53	0	5146	0	0
T54	0	6276	0	0
T55	0	6408	0	0
T56	0	11992	0	0
T57	0	5772	0	0
T58	0	23518	0	0
T59	3119	0	0	0
T60	1189	0	0	0
T61	2106	0	0	0
T62	2657	0	0	0
T63	3567	0	0	0
T64	2038	0	0	0
T65	1051	0	0	0
T66	968	0	0	0
T67	111129	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32585367	8916	0	0
T5	1797	4	0	0
T6	1623	0	0	0
T16	0	11	0	0
T27	1400	0	0	0
T28	2286	0	0	0
T29	3310	0	0	0
T30	2072	0	0	0
T31	2391	0	0	0
T32	1563	0	0	0
T33	1037	0	0	0
T36	0	144	0	0
T49	1494	0	0	0
T52	0	223	0	0
T77	0	8	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	3	0	0
T153	0	1	0	0
T154	0	4	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32585367	8507	0	0
T5	1797	7	0	0
T6	1623	0	0	0
T16	0	13	0	0
T27	1400	0	0	0
T28	2286	0	0	0
T29	3310	0	0	0
T30	2072	0	0	0
T31	2391	0	0	0
T32	1563	0	0	0
T33	1037	0	0	0
T36	0	189	0	0
T49	1494	0	0	0
T52	0	170	0	0
T77	0	15	0	0
T150	0	1	0	0
T151	0	5	0	0
T152	0	3	0	0
T153	0	2	0	0
T155	0	2	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32585367	13664	0	0
T4	1287	10	0	0
T5	1797	0	0	0
T6	1623	0	0	0
T10	0	101	0	0
T11	0	123	0	0
T27	1400	0	0	0
T28	2286	27	0	0
T29	3310	0	0	0
T30	2072	0	0	0
T31	2391	0	0	0
T32	1563	27	0	0
T33	1037	0	0	0
T68	0	20	0	0
T69	0	38	0	0
T70	0	4	0	0
T74	0	5	0	0
T156	0	23	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32585367	7756	0	0
T10	62459	43	0	0
T11	0	58	0	0
T20	1809	0	0	0
T21	1529	0	0	0
T22	887	0	0	0
T23	5310	0	0	0
T24	2516	0	0	0
T25	1177	0	0	0
T26	1652	0	0	0
T36	0	143	0	0
T75	0	77	0	0
T78	0	30	0	0
T130	1121	0	0	0
T157	0	28	0	0
T158	0	4	0	0
T159	0	11	0	0
T160	0	70	0	0
T161	0	7	0	0
T162	2057	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32585367	19310	0	0
T5	1797	99	0	0
T6	1623	0	0	0
T16	0	155	0	0
T27	1400	0	0	0
T28	2286	0	0	0
T29	3310	0	0	0
T30	2072	0	0	0
T31	2391	0	0	0
T32	1563	0	0	0
T33	1037	0	0	0
T36	0	368	0	0
T49	1494	0	0	0
T77	0	220	0	0
T100	0	100	0	0
T150	0	103	0	0
T151	0	52	0	0
T152	0	107	0	0
T155	0	125	0	0
T163	0	98	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32585367	7811	0	0
T36	146380	193	0	0
T52	0	158	0	0
T54	0	248	0	0
T55	0	388	0	0
T57	0	105	0	0
T59	3119	0	0	0
T60	1189	0	0	0
T61	2106	0	0	0
T62	2657	0	0	0
T63	3567	0	0	0
T64	2038	0	0	0
T65	1051	0	0	0
T66	968	0	0	0
T67	111129	0	0	0
T164	0	282	0	0
T165	0	185	0	0
T166	0	550	0	0
T167	0	62	0	0
T168	0	93	0	0