Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

24                        logic step_down;
25         1/1            always_comb step_down = div_step_down_req_i && !scanmode;
           Tests:       T4 T5 T27 
26                      
27                        logic step_up;
28         1/1            always_comb step_up = !step_down;
           Tests:       T4 T28 T30 

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T27
1	0	Covered	T4,T30,T32
1	1	Covered	T4,T28,T30

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	62669510	3035	0	0
g_div2.Div2Whole_A	62669510	3580	0	0
g_div4.Div4Stepped_A	30426603	2985	0	0
g_div4.Div4Whole_A	30426603	3425	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62669510	3035	0	0
T4	7725	2	0	0
T5	6161	0	0	0
T6	1551	0	0	0
T27	2689	0	0	0
T28	4671	10	0	0
T29	3344	0	0	0
T30	4738	10	0	0
T31	19126	0	0	0
T32	12501	4	0	0
T33	4153	2	0	0
T41	0	6	0	0
T43	0	2	0	0
T68	0	2	0	0
T69	0	3	0	0
T70	0	1	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62669510	3580	0	0
T4	7725	2	0	0
T5	6161	0	0	0
T6	1551	0	0	0
T27	2689	0	0	0
T28	4671	13	0	0
T29	3344	0	0	0
T30	4738	13	0	0
T31	19126	0	0	0
T32	12501	4	0	0
T33	4153	2	0	0
T41	0	13	0	0
T43	0	6	0	0
T68	0	4	0	0
T69	0	3	0	0
T70	0	1	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30426603	2985	0	0
T4	4026	2	0	0
T5	3055	0	0	0
T6	729	0	0	0
T27	1325	0	0	0
T28	2476	10	0	0
T29	1647	0	0	0
T30	2720	10	0	0
T31	9530	0	0	0
T32	6717	4	0	0
T33	2176	2	0	0
T41	0	6	0	0
T43	0	1	0	0
T68	0	2	0	0
T69	0	3	0	0
T70	0	1	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30426603	3425	0	0
T4	4026	2	0	0
T5	3055	0	0	0
T6	729	0	0	0
T27	1325	0	0	0
T28	2476	13	0	0
T29	1647	0	0	0
T30	2720	13	0	0
T31	9530	0	0	0
T32	6717	4	0	0
T33	2176	2	0	0
T41	0	10	0	0
T43	0	6	0	0
T68	0	4	0	0
T69	0	3	0	0
T70	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

24                        logic step_down;
25         1/1            always_comb step_down = div_step_down_req_i && !scanmode;
           Tests:       T4 T5 T27 
26                      
27                        logic step_up;
28         1/1            always_comb step_up = !step_down;
           Tests:       T4 T28 T30 

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T27
1	0	Covered	T4,T30,T32
1	1	Covered	T4,T28,T30

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	62669510	3035	0	0
g_div2.Div2Whole_A	62669510	3580	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62669510	3035	0	0
T4	7725	2	0	0
T5	6161	0	0	0
T6	1551	0	0	0
T27	2689	0	0	0
T28	4671	10	0	0
T29	3344	0	0	0
T30	4738	10	0	0
T31	19126	0	0	0
T32	12501	4	0	0
T33	4153	2	0	0
T41	0	6	0	0
T43	0	2	0	0
T68	0	2	0	0
T69	0	3	0	0
T70	0	1	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62669510	3580	0	0
T4	7725	2	0	0
T5	6161	0	0	0
T6	1551	0	0	0
T27	2689	0	0	0
T28	4671	13	0	0
T29	3344	0	0	0
T30	4738	13	0	0
T31	19126	0	0	0
T32	12501	4	0	0
T33	4153	2	0	0
T41	0	13	0	0
T43	0	6	0	0
T68	0	4	0	0
T69	0	3	0	0
T70	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

24                        logic step_down;
25         1/1            always_comb step_down = div_step_down_req_i && !scanmode;
           Tests:       T4 T5 T27 
26                      
27                        logic step_up;
28         1/1            always_comb step_up = !step_down;
           Tests:       T4 T28 T30 

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T27
1	0	Covered	T4,T30,T32
1	1	Covered	T4,T28,T30

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	30426603	2985	0	0
g_div4.Div4Whole_A	30426603	3425	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30426603	2985	0	0
T4	4026	2	0	0
T5	3055	0	0	0
T6	729	0	0	0
T27	1325	0	0	0
T28	2476	10	0	0
T29	1647	0	0	0
T30	2720	10	0	0
T31	9530	0	0	0
T32	6717	4	0	0
T33	2176	2	0	0
T41	0	6	0	0
T43	0	1	0	0
T68	0	2	0	0
T69	0	3	0	0
T70	0	1	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30426603	3425	0	0
T4	4026	2	0	0
T5	3055	0	0	0
T6	729	0	0	0
T27	1325	0	0	0
T28	2476	13	0	0
T29	1647	0	0	0
T30	2720	13	0	0
T31	9530	0	0	0
T32	6717	4	0	0
T33	2176	2	0	0
T41	0	10	0	0
T43	0	6	0	0
T68	0	4	0	0
T69	0	3	0	0
T70	0	1	0	0