Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	95047314	441	0	0
StatusRise_A	95047314	441	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95047314	441	0	0
T1	25857	0	0	0
T6	4869	4	0	0
T27	4200	0	0	0
T28	6858	0	0	0
T29	9930	0	0	0
T30	6216	0	0	0
T31	7173	0	0	0
T32	4689	0	0	0
T33	3111	0	0	0
T38	0	12	0	0
T44	0	1	0	0
T49	4482	0	0	0
T98	0	14	0	0
T169	0	3	0	0
T170	0	1	0	0
T171	0	9	0	0
T172	0	13	0	0
T173	0	15	0	0
T174	0	7	0	0
T175	0	10	0	0
T176	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95047314	441	0	0
T1	25857	0	0	0
T6	4869	4	0	0
T27	4200	0	0	0
T28	6858	0	0	0
T29	9930	0	0	0
T30	6216	0	0	0
T31	7173	0	0	0
T32	4689	0	0	0
T33	3111	0	0	0
T38	0	12	0	0
T44	0	1	0	0
T49	4482	0	0	0
T98	0	14	0	0
T169	0	3	0	0
T170	0	1	0	0
T171	0	9	0	0
T172	0	13	0	0
T173	0	15	0	0
T174	0	7	0	0
T175	0	10	0	0
T176	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	31682438	140	0	0
StatusRise_A	31682438	140	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31682438	140	0	0
T1	8619	0	0	0
T6	1623	2	0	0
T27	1400	0	0	0
T28	2286	0	0	0
T29	3310	0	0	0
T30	2072	0	0	0
T31	2391	0	0	0
T32	1563	0	0	0
T33	1037	0	0	0
T38	0	3	0	0
T49	1494	0	0	0
T98	0	5	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	3	0	0
T172	0	3	0	0
T173	0	4	0	0
T174	0	3	0	0
T175	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31682438	140	0	0
T1	8619	0	0	0
T6	1623	2	0	0
T27	1400	0	0	0
T28	2286	0	0	0
T29	3310	0	0	0
T30	2072	0	0	0
T31	2391	0	0	0
T32	1563	0	0	0
T33	1037	0	0	0
T38	0	3	0	0
T49	1494	0	0	0
T98	0	5	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	3	0	0
T172	0	3	0	0
T173	0	4	0	0
T174	0	3	0	0
T175	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	31682438	148	0	0
StatusRise_A	31682438	148	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31682438	148	0	0
T1	8619	0	0	0
T6	1623	1	0	0
T27	1400	0	0	0
T28	2286	0	0	0
T29	3310	0	0	0
T30	2072	0	0	0
T31	2391	0	0	0
T32	1563	0	0	0
T33	1037	0	0	0
T38	0	3	0	0
T44	0	1	0	0
T49	1494	0	0	0
T98	0	4	0	0
T169	0	1	0	0
T171	0	4	0	0
T172	0	5	0	0
T173	0	7	0	0
T174	0	2	0	0
T175	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31682438	148	0	0
T1	8619	0	0	0
T6	1623	1	0	0
T27	1400	0	0	0
T28	2286	0	0	0
T29	3310	0	0	0
T30	2072	0	0	0
T31	2391	0	0	0
T32	1563	0	0	0
T33	1037	0	0	0
T38	0	3	0	0
T44	0	1	0	0
T49	1494	0	0	0
T98	0	4	0	0
T169	0	1	0	0
T171	0	4	0	0
T172	0	5	0	0
T173	0	7	0	0
T174	0	2	0	0
T175	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	31682438	153	0	0
StatusRise_A	31682438	153	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31682438	153	0	0
T1	8619	0	0	0
T6	1623	1	0	0
T27	1400	0	0	0
T28	2286	0	0	0
T29	3310	0	0	0
T30	2072	0	0	0
T31	2391	0	0	0
T32	1563	0	0	0
T33	1037	0	0	0
T38	0	6	0	0
T49	1494	0	0	0
T98	0	5	0	0
T169	0	1	0	0
T171	0	2	0	0
T172	0	5	0	0
T173	0	4	0	0
T174	0	2	0	0
T175	0	4	0	0
T176	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31682438	153	0	0
T1	8619	0	0	0
T6	1623	1	0	0
T27	1400	0	0	0
T28	2286	0	0	0
T29	3310	0	0	0
T30	2072	0	0	0
T31	2391	0	0	0
T32	1563	0	0	0
T33	1037	0	0	0
T38	0	6	0	0
T49	1494	0	0	0
T98	0	5	0	0
T169	0	1	0	0
T171	0	2	0	0
T172	0	5	0	0
T173	0	4	0	0
T174	0	2	0	0
T175	0	4	0	0
T176	0	4	0	0