Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T37,T38
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	729237420	31283	0	0
CgEnOn_A	729237420	22521	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729237420	31283	0	0
T1	166615	0	0	0
T4	17626	3	0	0
T5	39495	7	0	0
T6	17088	13	0	0
T27	30168	48	0	0
T28	53104	3	0	0
T29	37514	9	0	0
T30	54700	3	0	0
T31	215034	8	0	0
T32	142492	3	0	0
T33	47110	3	0	0
T38	0	18	0	0
T40	0	1	0	0
T42	0	4	0	0
T44	0	5	0	0
T49	12760	0	0	0
T98	0	25	0	0
T169	0	5	0	0
T171	0	20	0	0
T172	0	25	0	0
T173	0	35	0	0
T174	0	10	0	0
T175	0	20	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	729237420	22521	0	0
T1	166615	0	0	0
T5	39495	4	0	0
T6	17088	10	0	0
T27	30168	45	0	0
T28	53104	0	0	0
T29	37514	6	0	0
T30	54700	0	0	0
T31	215034	5	0	0
T32	142492	0	0	0
T33	47110	0	0	0
T38	0	27	0	0
T39	0	3	0	0
T40	0	4	0	0
T42	0	4	0	0
T44	0	8	0	0
T49	15898	0	0	0
T71	0	2	0	0
T73	0	3	0	0
T98	0	37	0	0
T169	0	5	0	0
T171	0	20	0	0
T172	0	25	0	0
T173	0	35	0	0
T174	0	10	0	0
T175	0	20	0	0
T177	0	22	0	0
T178	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T37,T38
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	30426199	161	0	0
CgEnOn_A	30426199	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30426199	161	0	0
T1	17227	0	0	0
T6	728	1	0	0
T27	1325	0	0	0
T28	2476	0	0	0
T29	1646	0	0	0
T30	2720	0	0	0
T31	9530	0	0	0
T32	6717	0	0	0
T33	2176	0	0	0
T38	0	3	0	0
T44	0	1	0	0
T49	657	0	0	0
T98	0	4	0	0
T169	0	1	0	0
T171	0	4	0	0
T172	0	5	0	0
T173	0	7	0	0
T174	0	2	0	0
T175	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30426199	161	0	0
T1	17227	0	0	0
T6	728	1	0	0
T27	1325	0	0	0
T28	2476	0	0	0
T29	1646	0	0	0
T30	2720	0	0	0
T31	9530	0	0	0
T32	6717	0	0	0
T33	2176	0	0	0
T38	0	3	0	0
T44	0	1	0	0
T49	657	0	0	0
T98	0	4	0	0
T169	0	1	0	0
T171	0	4	0	0
T172	0	5	0	0
T173	0	7	0	0
T174	0	2	0	0
T175	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T37,T38
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	15212714	161	0	0
CgEnOn_A	15212714	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15212714	161	0	0
T1	8613	0	0	0
T6	364	1	0	0
T27	662	0	0	0
T28	1238	0	0	0
T29	823	0	0	0
T30	1359	0	0	0
T31	4765	0	0	0
T32	3358	0	0	0
T33	1088	0	0	0
T38	0	3	0	0
T44	0	1	0	0
T49	329	0	0	0
T98	0	4	0	0
T169	0	1	0	0
T171	0	4	0	0
T172	0	5	0	0
T173	0	7	0	0
T174	0	2	0	0
T175	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15212714	161	0	0
T1	8613	0	0	0
T6	364	1	0	0
T27	662	0	0	0
T28	1238	0	0	0
T29	823	0	0	0
T30	1359	0	0	0
T31	4765	0	0	0
T32	3358	0	0	0
T33	1088	0	0	0
T38	0	3	0	0
T44	0	1	0	0
T49	329	0	0	0
T98	0	4	0	0
T169	0	1	0	0
T171	0	4	0	0
T172	0	5	0	0
T173	0	7	0	0
T174	0	2	0	0
T175	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T37,T38
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	15212714	161	0	0
CgEnOn_A	15212714	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15212714	161	0	0
T1	8613	0	0	0
T6	364	1	0	0
T27	662	0	0	0
T28	1238	0	0	0
T29	823	0	0	0
T30	1359	0	0	0
T31	4765	0	0	0
T32	3358	0	0	0
T33	1088	0	0	0
T38	0	3	0	0
T44	0	1	0	0
T49	329	0	0	0
T98	0	4	0	0
T169	0	1	0	0
T171	0	4	0	0
T172	0	5	0	0
T173	0	7	0	0
T174	0	2	0	0
T175	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15212714	161	0	0
T1	8613	0	0	0
T6	364	1	0	0
T27	662	0	0	0
T28	1238	0	0	0
T29	823	0	0	0
T30	1359	0	0	0
T31	4765	0	0	0
T32	3358	0	0	0
T33	1088	0	0	0
T38	0	3	0	0
T44	0	1	0	0
T49	329	0	0	0
T98	0	4	0	0
T169	0	1	0	0
T171	0	4	0	0
T172	0	5	0	0
T173	0	7	0	0
T174	0	2	0	0
T175	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T37,T38
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	15212714	161	0	0
CgEnOn_A	15212714	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15212714	161	0	0
T1	8613	0	0	0
T6	364	1	0	0
T27	662	0	0	0
T28	1238	0	0	0
T29	823	0	0	0
T30	1359	0	0	0
T31	4765	0	0	0
T32	3358	0	0	0
T33	1088	0	0	0
T38	0	3	0	0
T44	0	1	0	0
T49	329	0	0	0
T98	0	4	0	0
T169	0	1	0	0
T171	0	4	0	0
T172	0	5	0	0
T173	0	7	0	0
T174	0	2	0	0
T175	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15212714	161	0	0
T1	8613	0	0	0
T6	364	1	0	0
T27	662	0	0	0
T28	1238	0	0	0
T29	823	0	0	0
T30	1359	0	0	0
T31	4765	0	0	0
T32	3358	0	0	0
T33	1088	0	0	0
T38	0	3	0	0
T44	0	1	0	0
T49	329	0	0	0
T98	0	4	0	0
T169	0	1	0	0
T171	0	4	0	0
T172	0	5	0	0
T173	0	7	0	0
T174	0	2	0	0
T175	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T37,T38
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	62669092	161	0	0
CgEnOn_A	62669092	150	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62669092	161	0	0
T1	34478	0	0	0
T6	1550	1	0	0
T27	2688	0	0	0
T28	4670	0	0	0
T29	3344	0	0	0
T30	4738	0	0	0
T31	19125	0	0	0
T32	12500	0	0	0
T33	4152	0	0	0
T38	0	3	0	0
T44	0	1	0	0
T49	1435	0	0	0
T98	0	4	0	0
T169	0	1	0	0
T171	0	4	0	0
T172	0	5	0	0
T173	0	7	0	0
T174	0	2	0	0
T175	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62669092	150	0	0
T1	34478	0	0	0
T6	1550	1	0	0
T27	2688	0	0	0
T28	4670	0	0	0
T29	3344	0	0	0
T30	4738	0	0	0
T31	19125	0	0	0
T32	12500	0	0	0
T33	4152	0	0	0
T38	0	3	0	0
T44	0	1	0	0
T49	1435	0	0	0
T98	0	4	0	0
T169	0	1	0	0
T171	0	4	0	0
T172	0	5	0	0
T173	0	7	0	0
T174	0	2	0	0
T175	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T37,T38
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	69274743	148	0	0
CgEnOn_A	69274743	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69274743	148	0	0
T1	35916	0	0	0
T6	1592	2	0	0
T27	2801	0	0	0
T28	4865	0	0	0
T29	3483	0	0	0
T30	4935	0	0	0
T31	19923	0	0	0
T32	13021	0	0	0
T33	4325	0	0	0
T38	0	3	0	0
T49	1494	0	0	0
T98	0	5	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	3	0	0
T172	0	3	0	0
T173	0	4	0	0
T174	0	3	0	0
T175	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69274743	142	0	0
T1	35916	0	0	0
T6	1592	2	0	0
T27	2801	0	0	0
T28	4865	0	0	0
T29	3483	0	0	0
T30	4935	0	0	0
T31	19923	0	0	0
T32	13021	0	0	0
T33	4325	0	0	0
T38	0	3	0	0
T49	1494	0	0	0
T98	0	5	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	3	0	0
T172	0	3	0	0
T173	0	4	0	0
T174	0	3	0	0
T175	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T37,T38
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	69274743	148	0	0
CgEnOn_A	69274743	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69274743	148	0	0
T1	35916	0	0	0
T6	1592	2	0	0
T27	2801	0	0	0
T28	4865	0	0	0
T29	3483	0	0	0
T30	4935	0	0	0
T31	19923	0	0	0
T32	13021	0	0	0
T33	4325	0	0	0
T38	0	3	0	0
T49	1494	0	0	0
T98	0	5	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	3	0	0
T172	0	3	0	0
T173	0	4	0	0
T174	0	3	0	0
T175	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69274743	142	0	0
T1	35916	0	0	0
T6	1592	2	0	0
T27	2801	0	0	0
T28	4865	0	0	0
T29	3483	0	0	0
T30	4935	0	0	0
T31	19923	0	0	0
T32	13021	0	0	0
T33	4325	0	0	0
T38	0	3	0	0
T49	1494	0	0	0
T98	0	5	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	3	0	0
T172	0	3	0	0
T173	0	4	0	0
T174	0	3	0	0
T175	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T37,T38
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	33273762	158	0	0
CgEnOn_A	33273762	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33273762	158	0	0
T1	17239	0	0	0
T6	762	1	0	0
T27	1344	0	0	0
T28	2335	0	0	0
T29	1672	0	0	0
T30	2369	0	0	0
T31	9563	0	0	0
T32	6250	0	0	0
T33	2076	0	0	0
T38	0	6	0	0
T49	717	0	0	0
T98	0	5	0	0
T169	0	1	0	0
T171	0	2	0	0
T172	0	5	0	0
T173	0	4	0	0
T174	0	2	0	0
T175	0	4	0	0
T176	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33273762	154	0	0
T1	17239	0	0	0
T6	762	1	0	0
T27	1344	0	0	0
T28	2335	0	0	0
T29	1672	0	0	0
T30	2369	0	0	0
T31	9563	0	0	0
T32	6250	0	0	0
T33	2076	0	0	0
T38	0	6	0	0
T49	717	0	0	0
T98	0	5	0	0
T169	0	1	0	0
T171	0	2	0	0
T172	0	5	0	0
T173	0	4	0	0
T174	0	2	0	0
T175	0	4	0	0
T176	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T38,T44
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	15212714	4987	0	0
CgEnOn_A	15212714	2815	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15212714	4987	0	0
T4	2013	1	0	0
T5	1527	2	0	0
T6	364	2	0	0
T27	662	16	0	0
T28	1238	1	0	0
T29	823	1	0	0
T30	1359	1	0	0
T31	4765	1	0	0
T32	3358	1	0	0
T33	1088	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	15212714	2815	0	0
T5	1527	1	0	0
T6	364	1	0	0
T27	662	15	0	0
T28	1238	0	0	0
T29	823	0	0	0
T30	1359	0	0	0
T31	4765	0	0	0
T32	3358	0	0	0
T33	1088	0	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T49	329	0	0	0
T98	0	4	0	0
T177	0	6	0	0
T178	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T38,T44
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	30426199	4990	0	0
CgEnOn_A	30426199	2818	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30426199	4990	0	0
T4	4026	1	0	0
T5	3055	2	0	0
T6	728	2	0	0
T27	1325	15	0	0
T28	2476	1	0	0
T29	1646	1	0	0
T30	2720	1	0	0
T31	9530	1	0	0
T32	6717	1	0	0
T33	2176	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	30426199	2818	0	0
T5	3055	1	0	0
T6	728	1	0	0
T27	1325	14	0	0
T28	2476	0	0	0
T29	1646	0	0	0
T30	2720	0	0	0
T31	9530	0	0	0
T32	6717	0	0	0
T33	2176	0	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T49	657	0	0	0
T98	0	4	0	0
T177	0	8	0	0
T178	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T38,T44
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	62669092	5012	0	0
CgEnOn_A	62669092	2829	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62669092	5012	0	0
T4	7725	1	0	0
T5	6161	2	0	0
T6	1550	2	0	0
T27	2688	17	0	0
T28	4670	1	0	0
T29	3344	1	0	0
T30	4738	1	0	0
T31	19125	1	0	0
T32	12500	1	0	0
T33	4152	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62669092	2829	0	0
T5	6161	1	0	0
T6	1550	1	0	0
T27	2688	16	0	0
T28	4670	0	0	0
T29	3344	0	0	0
T30	4738	0	0	0
T31	19125	0	0	0
T32	12500	0	0	0
T33	4152	0	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	0	1	0	0
T44	0	1	0	0
T49	1435	0	0	0
T98	0	4	0	0
T177	0	8	0	0
T178	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T38,T98
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	33273762	5000	0	0
CgEnOn_A	33273762	2816	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33273762	5000	0	0
T4	3862	1	0	0
T5	3080	2	0	0
T6	762	2	0	0
T27	1344	15	0	0
T28	2335	1	0	0
T29	1672	1	0	0
T30	2369	1	0	0
T31	9563	1	0	0
T32	6250	1	0	0
T33	2076	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33273762	2816	0	0
T5	3080	1	0	0
T6	762	1	0	0
T27	1344	14	0	0
T28	2335	0	0	0
T29	1672	0	0	0
T30	2369	0	0	0
T31	9563	0	0	0
T32	6250	0	0	0
T33	2076	0	0	0
T38	0	6	0	0
T39	0	1	0	0
T40	0	1	0	0
T49	717	0	0	0
T98	0	5	0	0
T100	0	1	0	0
T177	0	8	0	0
T178	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T37,T38
1	0	Covered	T5,T29,T31
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	69274743	2544	0	0
CgEnOn_A	69274743	2538	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69274743	2544	0	0
T5	6418	1	0	0
T6	1592	2	0	0
T27	2801	0	0	0
T28	4865	0	0	0
T29	3483	6	0	0
T30	4935	0	0	0
T31	19923	5	0	0
T32	13021	0	0	0
T33	4325	0	0	0
T38	0	3	0	0
T40	0	1	0	0
T42	0	4	0	0
T49	1494	0	0	0
T71	0	2	0	0
T73	0	3	0	0
T98	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69274743	2538	0	0
T5	6418	1	0	0
T6	1592	2	0	0
T27	2801	0	0	0
T28	4865	0	0	0
T29	3483	6	0	0
T30	4935	0	0	0
T31	19923	5	0	0
T32	13021	0	0	0
T33	4325	0	0	0
T38	0	3	0	0
T40	0	1	0	0
T42	0	4	0	0
T49	1494	0	0	0
T71	0	2	0	0
T73	0	3	0	0
T98	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T37,T38
1	0	Covered	T5,T29,T31
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	69274743	2469	0	0
CgEnOn_A	69274743	2463	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69274743	2469	0	0
T5	6418	1	0	0
T6	1592	2	0	0
T27	2801	0	0	0
T28	4865	0	0	0
T29	3483	8	0	0
T30	4935	0	0	0
T31	19923	5	0	0
T32	13021	0	0	0
T33	4325	0	0	0
T38	0	3	0	0
T40	0	1	0	0
T42	0	3	0	0
T49	1494	0	0	0
T71	0	4	0	0
T73	0	5	0	0
T98	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69274743	2463	0	0
T5	6418	1	0	0
T6	1592	2	0	0
T27	2801	0	0	0
T28	4865	0	0	0
T29	3483	8	0	0
T30	4935	0	0	0
T31	19923	5	0	0
T32	13021	0	0	0
T33	4325	0	0	0
T38	0	3	0	0
T40	0	1	0	0
T42	0	3	0	0
T49	1494	0	0	0
T71	0	4	0	0
T73	0	5	0	0
T98	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T37,T38
1	0	Covered	T5,T29,T31
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	69274743	2539	0	0
CgEnOn_A	69274743	2533	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69274743	2539	0	0
T5	6418	1	0	0
T6	1592	2	0	0
T27	2801	0	0	0
T28	4865	0	0	0
T29	3483	8	0	0
T30	4935	0	0	0
T31	19923	9	0	0
T32	13021	0	0	0
T33	4325	0	0	0
T38	0	3	0	0
T40	0	1	0	0
T42	0	2	0	0
T49	1494	0	0	0
T71	0	4	0	0
T73	0	7	0	0
T98	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69274743	2533	0	0
T5	6418	1	0	0
T6	1592	2	0	0
T27	2801	0	0	0
T28	4865	0	0	0
T29	3483	8	0	0
T30	4935	0	0	0
T31	19923	9	0	0
T32	13021	0	0	0
T33	4325	0	0	0
T38	0	3	0	0
T40	0	1	0	0
T42	0	2	0	0
T49	1494	0	0	0
T71	0	4	0	0
T73	0	7	0	0
T98	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T37,T38
1	0	Covered	T5,T29,T31
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	69274743	2483	0	0
CgEnOn_A	69274743	2477	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69274743	2483	0	0
T5	6418	1	0	0
T6	1592	2	0	0
T27	2801	0	0	0
T28	4865	0	0	0
T29	3483	8	0	0
T30	4935	0	0	0
T31	19923	4	0	0
T32	13021	0	0	0
T33	4325	0	0	0
T38	0	3	0	0
T40	0	1	0	0
T42	0	3	0	0
T49	1494	0	0	0
T71	0	3	0	0
T73	0	6	0	0
T98	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69274743	2477	0	0
T5	6418	1	0	0
T6	1592	2	0	0
T27	2801	0	0	0
T28	4865	0	0	0
T29	3483	8	0	0
T30	4935	0	0	0
T31	19923	4	0	0
T32	13021	0	0	0
T33	4325	0	0	0
T38	0	3	0	0
T40	0	1	0	0
T42	0	3	0	0
T49	1494	0	0	0
T71	0	3	0	0
T73	0	6	0	0
T98	0	5	0	0