Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	208991	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

507134

1

T4

27

T5

19

T6

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	207411	1			T4	42		T5	18		T28	48
values[0x0]	241435	1			T4	20		T5	18		T6	22
values[0x1]	267279	1			T4	19		T5	19		T6	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	144367	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

571758

1

T4

35

T5

26

T6

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2859	1			T5	1		T33	3		T50	1
valid_sources[0x01]	4996	1			T2	1		T17	4		T22	1
valid_sources[0x02]	2812	1			T29	3		T25	1		T93	1
valid_sources[0x03]	2800	1			T2	9		T3	5		T20	1
valid_sources[0x04]	2549	1			T29	2		T21	1		T34	1
valid_sources[0x05]	2713	1			T1	1		T18	1		T20	1
valid_sources[0x06]	2323	1			T22	1		T24	3		T34	2
valid_sources[0x07]	2485	1			T29	1		T2	1		T93	1
valid_sources[0x08]	2863	1			T29	1		T50	1		T44	1
valid_sources[0x09]	3952	1			T5	1		T6	2		T20	1
valid_sources[0x0a]	2702	1			T29	2		T1	1		T20	1
valid_sources[0x0b]	3198	1			T33	2		T23	1		T93	2
valid_sources[0x0c]	2486	1			T6	1		T50	1		T20	1
valid_sources[0x0d]	2658	1			T5	1		T6	4		T29	1
valid_sources[0x0e]	2519	1			T50	2		T22	1		T25	1
valid_sources[0x0f]	3002	1			T5	1		T29	2		T2	4
valid_sources[0x10]	3132	1			T50	1		T9	4		T26	5
valid_sources[0x11]	4008	1			T5	1		T31	4		T45	1
valid_sources[0x12]	2726	1			T45	6		T26	2		T188	2
valid_sources[0x13]	2528	1			T20	1		T34	1		T26	4
valid_sources[0x14]	3403	1			T29	1		T20	1		T93	2
valid_sources[0x15]	5585	1			T29	1		T45	5		T26	3
valid_sources[0x16]	4135	1			T3	26		T22	1		T93	1
valid_sources[0x17]	2697	1			T29	1		T32	1		T22	2
valid_sources[0x18]	2916	1			T50	1		T2	10		T20	1
valid_sources[0x19]	2950	1			T50	2		T2	7		T93	1
valid_sources[0x1a]	2764	1			T5	1		T29	1		T2	3
valid_sources[0x1b]	2329	1			T5	1		T29	1		T1	9
valid_sources[0x1c]	3288	1			T99	1		T34	1		T39	1
valid_sources[0x1d]	2483	1			T17	1		T20	1		T34	1
valid_sources[0x1e]	2115	1			T26	3		T123	2		T194	1
valid_sources[0x1f]	3649	1			T20	1		T71	1		T26	4
valid_sources[0x20]	2598	1			T1	2		T20	1		T93	3
valid_sources[0x21]	2529	1			T33	2		T49	12		T2	23
valid_sources[0x22]	3015	1			T6	1		T26	4		T123	2
valid_sources[0x23]	2994	1			T32	2		T45	4		T26	3
valid_sources[0x24]	2543	1			T22	1		T45	1		T26	3
valid_sources[0x25]	3103	1			T32	1		T22	1		T24	2
valid_sources[0x26]	2627	1			T5	1		T29	1		T33	1
valid_sources[0x27]	2190	1			T29	1		T20	1		T21	2
valid_sources[0x28]	2545	1			T5	1		T50	1		T3	1
valid_sources[0x29]	2794	1			T29	1		T32	1		T33	2
valid_sources[0x2a]	2154	1			T50	1		T94	2		T42	1
valid_sources[0x2b]	2445	1			T93	2		T42	1		T45	1
valid_sources[0x2c]	2518	1			T2	2		T24	1		T34	1
valid_sources[0x2d]	2806	1			T5	1		T29	1		T34	2
valid_sources[0x2e]	3361	1			T5	1		T32	1		T26	3
valid_sources[0x2f]	2248	1			T4	1		T2	2		T26	2
valid_sources[0x30]	2755	1			T50	2		T34	1		T42	1
valid_sources[0x31]	2814	1			T5	1		T32	1		T17	1
valid_sources[0x32]	2764	1			T6	1		T29	2		T50	1
valid_sources[0x33]	2932	1			T32	1		T21	1		T45	2
valid_sources[0x34]	3106	1			T7	1		T47	1		T195	1
valid_sources[0x35]	2900	1			T5	1		T6	3		T94	1
valid_sources[0x36]	2603	1			T99	1		T93	1		T26	1
valid_sources[0x37]	3315	1			T5	1		T41	21		T71	1
valid_sources[0x38]	3424	1			T50	2		T18	1		T25	1
valid_sources[0x39]	2674	1			T45	3		T9	3		T26	2
valid_sources[0x3a]	2958	1			T6	6		T29	1		T17	1
valid_sources[0x3b]	3274	1			T5	1		T29	1		T20	1
valid_sources[0x3c]	2343	1			T29	1		T50	1		T21	1
valid_sources[0x3d]	3280	1			T31	1		T32	1		T50	1
valid_sources[0x3e]	2324	1			T5	1		T29	1		T50	2
valid_sources[0x3f]	2670	1			T29	1		T50	1		T20	2
valid_sources[0x40]	2475	1			T20	2		T93	1		T45	1
valid_sources[0x41]	2439	1			T30	46		T50	1		T20	1
valid_sources[0x42]	3105	1			T4	15		T50	1		T22	1
valid_sources[0x43]	2643	1			T5	1		T29	2		T23	1
valid_sources[0x44]	2422	1			T50	1		T2	3		T99	2
valid_sources[0x45]	2314	1			T3	44		T20	1		T124	1
valid_sources[0x46]	3098	1			T5	1		T93	1		T26	2
valid_sources[0x47]	2465	1			T4	2		T3	50		T100	1
valid_sources[0x48]	2336	1			T22	1		T34	1		T45	2
valid_sources[0x49]	2670	1			T20	1		T93	1		T34	2
valid_sources[0x4a]	2943	1			T29	1		T93	1		T42	1
valid_sources[0x4b]	2202	1			T4	2		T23	2		T34	1
valid_sources[0x4c]	2599	1			T29	3		T50	1		T2	6
valid_sources[0x4d]	2664	1			T6	2		T28	84		T1	11
valid_sources[0x4e]	2793	1			T6	3		T50	1		T26	5
valid_sources[0x4f]	2671	1			T29	1		T20	1		T23	4
valid_sources[0x50]	3624	1			T5	1		T34	1		T45	5
valid_sources[0x51]	2360	1			T29	1		T31	1		T93	1
valid_sources[0x52]	2862	1			T6	1		T29	2		T9	10
valid_sources[0x53]	2513	1			T29	1		T1	3		T2	2
valid_sources[0x54]	2461	1			T50	1		T45	1		T26	5
valid_sources[0x55]	2205	1			T50	1		T99	2		T26	2
valid_sources[0x56]	2514	1			T2	3		T99	1		T45	10
valid_sources[0x57]	3129	1			T32	1		T49	1		T23	2
valid_sources[0x58]	2882	1			T5	3		T34	1		T42	1
valid_sources[0x59]	3073	1			T29	1		T17	2		T99	2
valid_sources[0x5a]	2310	1			T29	1		T2	1		T34	1
valid_sources[0x5b]	3226	1			T6	2		T29	1		T18	1
valid_sources[0x5c]	2697	1			T50	1		T3	1		T44	13
valid_sources[0x5d]	2889	1			T32	2		T34	1		T45	3
valid_sources[0x5e]	2361	1			T5	1		T6	3		T43	1
valid_sources[0x5f]	2935	1			T50	1		T20	1		T93	2
valid_sources[0x60]	2241	1			T29	2		T32	1		T20	1
valid_sources[0x61]	2208	1			T32	1		T50	1		T2	5
valid_sources[0x62]	2512	1			T50	2		T2	1		T3	8
valid_sources[0x63]	2577	1			T1	5		T2	3		T20	1
valid_sources[0x64]	2147	1			T4	1		T29	3		T22	1
valid_sources[0x65]	2113	1			T29	1		T23	7		T93	2
valid_sources[0x66]	2397	1			T50	1		T23	1		T100	2
valid_sources[0x67]	3006	1			T32	1		T34	1		T45	3
valid_sources[0x68]	2944	1			T5	1		T42	1		T26	4
valid_sources[0x69]	3462	1			T22	1		T25	1		T26	3
valid_sources[0x6a]	2386	1			T6	2		T50	1		T22	1
valid_sources[0x6b]	2924	1			T2	7		T22	2		T123	1
valid_sources[0x6c]	3415	1			T29	1		T17	2		T34	1
valid_sources[0x6d]	2552	1			T50	1		T2	7		T93	1
valid_sources[0x6e]	2267	1			T29	1		T23	1		T42	1
valid_sources[0x6f]	3311	1			T2	4		T34	1		T42	1
valid_sources[0x70]	2693	1			T33	2		T34	1		T71	2
valid_sources[0x71]	2579	1			T50	1		T23	3		T100	1
valid_sources[0x72]	2825	1			T29	1		T2	8		T20	2
valid_sources[0x73]	2561	1			T93	1		T34	1		T45	2
valid_sources[0x74]	4843	1			T6	1		T20	1		T26	7
valid_sources[0x75]	2789	1			T50	1		T99	1		T34	1
valid_sources[0x76]	2700	1			T5	1		T2	5		T26	3
valid_sources[0x77]	2338	1			T50	1		T20	2		T93	1
valid_sources[0x78]	2759	1			T5	1		T45	1		T26	1
valid_sources[0x79]	2745	1			T50	2		T2	3		T94	1
valid_sources[0x7a]	2714	1			T29	1		T1	5		T71	1
valid_sources[0x7b]	2118	1			T32	2		T22	1		T45	1
valid_sources[0x7c]	2410	1			T29	1		T20	2		T22	1
valid_sources[0x7d]	2976	1			T5	1		T29	2		T9	4
valid_sources[0x7e]	2014	1			T50	1		T20	1		T23	2
valid_sources[0x7f]	2559	1			T50	1		T22	1		T25	1
valid_sources[0x80]	2194	1			T5	1		T33	1		T20	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

140672

1

T4

17

T5

7

T28

22

values[0x0]

all_enables

biggest_size

196304

1

T4

7

T5

8

T6

8

values[0x1]

all_enables

biggest_size

170158

1

T4

3

T5

4

T6

1