Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	627952	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3794433

1

T4

1

T5

6

T6

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1074803	1			T4	13		T5	6		T29	28
values[0x0]	1536555	1			T4	7		T5	3		T6	3
values[0x1]	1811027	1			T4	2		T5	10		T6	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	334309	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4088076

1

T4

4

T5

9

T6

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17141	1			T20	1		T203	2		T10	3
valid_sources[0x01]	17158	1			T33	1		T68	1		T1	2
valid_sources[0x02]	17319	1			T50	1		T10	4		T47	1
valid_sources[0x03]	18135	1			T34	1		T20	1		T9	1
valid_sources[0x04]	17576	1			T31	1		T1	2		T9	1
valid_sources[0x05]	16533	1			T3	4		T10	2		T47	2
valid_sources[0x06]	17146	1			T1	1		T55	3		T9	1
valid_sources[0x07]	17268	1			T198	5		T39	1		T10	5
valid_sources[0x08]	16969	1			T4	1		T1	2		T20	1
valid_sources[0x09]	17298	1			T1	3		T40	2		T60	1
valid_sources[0x0a]	16205	1			T33	1		T9	1		T60	3
valid_sources[0x0b]	16794	1			T4	3		T1	4		T59	1
valid_sources[0x0c]	17296	1			T29	2		T9	2		T50	1
valid_sources[0x0d]	16684	1			T1	6		T40	1		T60	2
valid_sources[0x0e]	16410	1			T1	2		T40	2		T50	1
valid_sources[0x0f]	17956	1			T33	1		T1	1		T3	2
valid_sources[0x10]	16982	1			T1	1		T60	1		T50	4
valid_sources[0x11]	16242	1			T1	3		T3	5		T20	1
valid_sources[0x12]	16794	1			T1	2		T60	3		T50	5
valid_sources[0x13]	16931	1			T29	1		T1	2		T9	1
valid_sources[0x14]	18035	1			T30	28		T1	2		T3	1
valid_sources[0x15]	16729	1			T19	2		T9	1		T50	3
valid_sources[0x16]	16995	1			T33	1		T1	1		T67	4
valid_sources[0x17]	18110	1			T68	1		T1	1		T25	1
valid_sources[0x18]	16010	1			T3	3		T10	1		T167	1
valid_sources[0x19]	16742	1			T68	2		T1	1		T56	1
valid_sources[0x1a]	17709	1			T5	19		T1	5		T3	1
valid_sources[0x1b]	16189	1			T29	1		T3	2		T9	1
valid_sources[0x1c]	16513	1			T1	3		T51	1		T20	1
valid_sources[0x1d]	17612	1			T1	4		T55	6		T19	4
valid_sources[0x1e]	17486	1			T60	1		T50	3		T13	9
valid_sources[0x1f]	18445	1			T1	1		T20	1		T9	1
valid_sources[0x20]	17421	1			T33	1		T20	2		T9	1
valid_sources[0x21]	17737	1			T1	1		T20	1		T40	1
valid_sources[0x22]	18035	1			T29	1		T33	1		T1	1
valid_sources[0x23]	15849	1			T20	1		T50	2		T10	5
valid_sources[0x24]	16033	1			T4	1		T31	1		T34	2
valid_sources[0x25]	16020	1			T4	1		T20	1		T40	1
valid_sources[0x26]	16342	1			T1	1		T51	1		T50	3
valid_sources[0x27]	16765	1			T34	2		T1	1		T50	1
valid_sources[0x28]	17933	1			T69	2		T3	2		T19	4
valid_sources[0x29]	16393	1			T1	1		T9	1		T59	1
valid_sources[0x2a]	17079	1			T33	3		T9	1		T50	2
valid_sources[0x2b]	16853	1			T33	1		T1	2		T10	4
valid_sources[0x2c]	17163	1			T33	4		T1	4		T3	8
valid_sources[0x2d]	16646	1			T33	3		T1	1		T51	1
valid_sources[0x2e]	17695	1			T3	2		T60	1		T50	2
valid_sources[0x2f]	16277	1			T4	2		T1	3		T55	1
valid_sources[0x30]	17319	1			T33	4		T1	2		T9	1
valid_sources[0x31]	17812	1			T51	2		T3	2		T9	4
valid_sources[0x32]	17407	1			T1	1		T50	3		T39	1
valid_sources[0x33]	18015	1			T9	2		T60	2		T50	2
valid_sources[0x34]	17695	1			T29	1		T33	1		T104	1
valid_sources[0x35]	16142	1			T69	1		T51	1		T50	1
valid_sources[0x36]	17642	1			T6	5		T1	1		T60	5
valid_sources[0x37]	16783	1			T1	2		T40	1		T60	1
valid_sources[0x38]	17542	1			T29	2		T68	1		T1	1
valid_sources[0x39]	17737	1			T1	1		T51	3		T56	1
valid_sources[0x3a]	16415	1			T33	2		T3	1		T20	1
valid_sources[0x3b]	17510	1			T29	1		T60	1		T50	3
valid_sources[0x3c]	17113	1			T104	1		T1	2		T20	1
valid_sources[0x3d]	17775	1			T1	1		T3	3		T60	1
valid_sources[0x3e]	17710	1			T104	1		T1	1		T52	56
valid_sources[0x3f]	16488	1			T33	2		T34	5		T1	2
valid_sources[0x40]	16462	1			T34	1		T1	1		T64	19
valid_sources[0x41]	18710	1			T1	1		T51	2		T40	1
valid_sources[0x42]	17108	1			T1	3		T3	1		T25	2
valid_sources[0x43]	15815	1			T68	1		T55	6		T9	1
valid_sources[0x44]	15861	1			T33	1		T34	2		T1	1
valid_sources[0x45]	17020	1			T31	1		T1	2		T56	1
valid_sources[0x46]	17772	1			T50	1		T62	2		T10	2
valid_sources[0x47]	16862	1			T1	1		T19	1		T60	1
valid_sources[0x48]	16489	1			T33	1		T68	1		T1	1
valid_sources[0x49]	17116	1			T104	1		T1	4		T50	3
valid_sources[0x4a]	18333	1			T1	1		T3	2		T25	1
valid_sources[0x4b]	18127	1			T1	1		T10	1		T167	2
valid_sources[0x4c]	16408	1			T55	12		T60	1		T50	1
valid_sources[0x4d]	17142	1			T4	1		T29	2		T104	1
valid_sources[0x4e]	17468	1			T1	2		T55	2		T19	1
valid_sources[0x4f]	16966	1			T40	1		T50	2		T167	2
valid_sources[0x50]	17798	1			T29	1		T51	2		T60	2
valid_sources[0x51]	16858	1			T1	2		T3	8		T9	1
valid_sources[0x52]	17379	1			T1	2		T3	4		T19	3
valid_sources[0x53]	16975	1			T51	1		T3	2		T9	4
valid_sources[0x54]	17282	1			T20	2		T9	2		T50	4
valid_sources[0x55]	17573	1			T29	1		T3	1		T50	1
valid_sources[0x56]	16538	1			T33	1		T40	1		T50	4
valid_sources[0x57]	18073	1			T1	1		T3	4		T20	1
valid_sources[0x58]	18119	1			T29	1		T68	3		T1	1
valid_sources[0x59]	17088	1			T1	1		T59	1		T60	1
valid_sources[0x5a]	18103	1			T50	3		T10	1		T205	1
valid_sources[0x5b]	16819	1			T1	2		T3	4		T25	4
valid_sources[0x5c]	16468	1			T1	2		T59	2		T50	2
valid_sources[0x5d]	17272	1			T9	1		T59	1		T50	3
valid_sources[0x5e]	16951	1			T29	1		T104	1		T1	1
valid_sources[0x5f]	16674	1			T33	4		T1	2		T20	2
valid_sources[0x60]	18087	1			T68	1		T1	2		T3	3
valid_sources[0x61]	18549	1			T3	5		T9	1		T50	2
valid_sources[0x62]	17633	1			T1	1		T25	2		T50	2
valid_sources[0x63]	17157	1			T1	2		T3	1		T50	5
valid_sources[0x64]	17269	1			T1	3		T60	1		T61	7
valid_sources[0x65]	17009	1			T29	1		T1	3		T50	2
valid_sources[0x66]	17051	1			T40	1		T50	2		T10	4
valid_sources[0x67]	17209	1			T55	1		T3	5		T50	1
valid_sources[0x68]	17975	1			T56	1		T50	3		T10	3
valid_sources[0x69]	19488	1			T32	21		T1	1		T58	3
valid_sources[0x6a]	16058	1			T1	1		T25	1		T50	2
valid_sources[0x6b]	18063	1			T1	1		T55	8		T20	1
valid_sources[0x6c]	17094	1			T9	2		T50	3		T39	2
valid_sources[0x6d]	18429	1			T3	4		T9	1		T59	2
valid_sources[0x6e]	16347	1			T1	2		T60	1		T50	2
valid_sources[0x6f]	16065	1			T104	1		T1	2		T51	3
valid_sources[0x70]	17832	1			T33	2		T56	1		T60	3
valid_sources[0x71]	18040	1			T51	2		T59	1		T60	1
valid_sources[0x72]	17918	1			T4	1		T1	1		T56	1
valid_sources[0x73]	18130	1			T1	1		T51	2		T60	3
valid_sources[0x74]	15624	1			T1	1		T25	1		T40	1
valid_sources[0x75]	17715	1			T29	1		T9	2		T50	3
valid_sources[0x76]	17206	1			T29	1		T33	1		T34	1
valid_sources[0x77]	17800	1			T50	3		T10	1		T167	3
valid_sources[0x78]	18262	1			T33	1		T1	2		T40	1
valid_sources[0x79]	17030	1			T9	3		T60	3		T50	1
valid_sources[0x7a]	18077	1			T1	2		T59	3		T50	2
valid_sources[0x7b]	17285	1			T29	2		T33	1		T1	1
valid_sources[0x7c]	17378	1			T3	28		T20	1		T40	2
valid_sources[0x7d]	17039	1			T29	2		T51	1		T50	2
valid_sources[0x7e]	18158	1			T34	1		T68	1		T1	1
valid_sources[0x7f]	17482	1			T50	2		T39	2		T10	3
valid_sources[0x80]	17214	1			T1	1		T9	3		T40	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

951711

1

T4

1

T5

4

T29

15

values[0x0]

all_enables

biggest_size

1446076

1

T5

1

T6

2

T30

3

values[0x1]

all_enables

biggest_size

1396646

1

T5

1

T29

5

T30

3