Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T28,T68
0	1	Covered	T6,T51,T25
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T68
1	0	Covered	T28,T53,T26
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1072648324	14522	0	0
GateOpen_A	1072648324	20676	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1072648324	14522	0	0
T4	3681	4	0	0
T5	22080	0	0	0
T6	3126	0	0	0
T21	0	4	0	0
T25	0	27	0	0
T26	0	12	0	0
T28	2757	14	0	0
T29	13471	0	0	0
T30	6562	0	0	0
T31	2827	0	0	0
T32	4789	0	0	0
T33	15275	0	0	0
T34	4699	0	0	0
T44	0	5	0	0
T51	0	45	0	0
T53	0	3	0	0
T65	0	4	0	0
T68	0	4	0	0
T198	0	39	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1072648324	20676	0	0
T1	0	28	0	0
T4	3681	4	0	0
T5	22080	4	0	0
T6	3126	4	0	0
T28	2757	18	0	0
T29	13471	0	0	0
T30	6562	4	0	0
T31	2827	0	0	0
T32	4789	0	0	0
T33	15275	4	0	0
T34	4699	0	0	0
T51	0	45	0	0
T52	0	4	0	0
T68	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T28,T68
0	1	Covered	T6,T51,T25
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T68
1	0	Covered	T28,T53,T26
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	118354868	3423	0	0
GateOpen_A	118354868	4960	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118354868	3423	0	0
T4	405	1	0	0
T5	3422	0	0	0
T6	341	0	0	0
T21	0	1	0	0
T25	0	5	0	0
T26	0	3	0	0
T28	297	4	0	0
T29	1486	0	0	0
T30	734	0	0	0
T31	299	0	0	0
T32	519	0	0	0
T33	1718	0	0	0
T34	543	0	0	0
T51	0	9	0	0
T53	0	1	0	0
T65	0	1	0	0
T68	0	1	0	0
T198	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118354868	4960	0	0
T1	0	7	0	0
T4	405	1	0	0
T5	3422	1	0	0
T6	341	1	0	0
T28	297	5	0	0
T29	1486	0	0	0
T30	734	1	0	0
T31	299	0	0	0
T32	519	0	0	0
T33	1718	1	0	0
T34	543	0	0	0
T51	0	9	0	0
T52	0	1	0	0
T68	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T28,T68
0	1	Covered	T6,T51,T25
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T68
1	0	Covered	T28,T53,T26
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	236710613	3712	0	0
GateOpen_A	236710613	5249	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236710613	3712	0	0
T4	810	1	0	0
T5	6845	0	0	0
T6	682	0	0	0
T21	0	1	0	0
T25	0	7	0	0
T26	0	3	0	0
T28	593	4	0	0
T29	2972	0	0	0
T30	1467	0	0	0
T31	598	0	0	0
T32	1038	0	0	0
T33	3436	0	0	0
T34	1089	0	0	0
T51	0	12	0	0
T53	0	1	0	0
T65	0	1	0	0
T68	0	1	0	0
T198	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236710613	5249	0	0
T1	0	7	0	0
T4	810	1	0	0
T5	6845	1	0	0
T6	682	1	0	0
T28	593	5	0	0
T29	2972	0	0	0
T30	1467	1	0	0
T31	598	0	0	0
T32	1038	0	0	0
T33	3436	1	0	0
T34	1089	0	0	0
T51	0	12	0	0
T52	0	1	0	0
T68	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T28,T68
0	1	Covered	T6,T51,T25
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T68
1	0	Covered	T28,T53,T26
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	474935020	3717	0	0
GateOpen_A	474935020	5257	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474935020	3717	0	0
T4	1644	1	0	0
T5	7875	0	0	0
T6	1402	0	0	0
T21	0	1	0	0
T25	0	7	0	0
T26	0	3	0	0
T28	1238	4	0	0
T29	6008	0	0	0
T30	2907	0	0	0
T31	1286	0	0	0
T32	2154	0	0	0
T33	6747	0	0	0
T34	2044	0	0	0
T51	0	11	0	0
T53	0	1	0	0
T65	0	1	0	0
T68	0	1	0	0
T198	0	12	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474935020	5257	0	0
T1	0	7	0	0
T4	1644	1	0	0
T5	7875	1	0	0
T6	1402	1	0	0
T28	1238	5	0	0
T29	6008	0	0	0
T30	2907	1	0	0
T31	1286	0	0	0
T32	2154	0	0	0
T33	6747	1	0	0
T34	2044	0	0	0
T51	0	11	0	0
T52	0	1	0	0
T68	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T28,T68
0	1	Covered	T6,T51,T25
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T68
1	0	Covered	T28,T26,T44
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	242647823	3670	0	0
GateOpen_A	242647823	5210	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242647823	3670	0	0
T4	822	1	0	0
T5	3938	0	0	0
T6	701	0	0	0
T21	0	1	0	0
T25	0	8	0	0
T26	0	3	0	0
T28	629	2	0	0
T29	3005	0	0	0
T30	1454	0	0	0
T31	644	0	0	0
T32	1078	0	0	0
T33	3374	0	0	0
T34	1023	0	0	0
T44	0	5	0	0
T51	0	13	0	0
T65	0	1	0	0
T68	0	1	0	0
T198	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242647823	5210	0	0
T1	0	7	0	0
T4	822	1	0	0
T5	3938	1	0	0
T6	701	1	0	0
T28	629	3	0	0
T29	3005	0	0	0
T30	1454	1	0	0
T31	644	0	0	0
T32	1078	0	0	0
T33	3374	1	0	0
T34	1023	0	0	0
T51	0	13	0	0
T52	0	1	0	0
T68	0	1	0	0