Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	855380335	81320	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	855380335	81320	0	0
T2	184135	223	0	0
T3	47250	0	0	0
T9	0	47	0	0
T10	0	260	0	0
T12	0	176	0	0
T13	0	335	0	0
T14	0	91	0	0
T15	0	97	0	0
T16	0	72	0	0
T17	0	40	0	0
T18	0	465	0	0
T19	14975	0	0	0
T20	76635	0	0	0
T21	3365	0	0	0
T22	4105	0	0	0
T23	4450	0	0	0
T24	7285	0	0	0
T25	10255	0	0	0
T26	6935	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	171076067	11869	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171076067	11869	0	0
T2	36827	35	0	0
T3	9450	0	0	0
T9	0	8	0	0
T10	0	34	0	0
T12	0	28	0	0
T13	0	53	0	0
T14	0	15	0	0
T15	0	13	0	0
T16	0	10	0	0
T17	0	7	0	0
T18	0	75	0	0
T19	2995	0	0	0
T20	15327	0	0	0
T21	673	0	0	0
T22	821	0	0	0
T23	890	0	0	0
T24	1457	0	0	0
T25	2051	0	0	0
T26	1387	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	171076067	11701	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171076067	11701	0	0
T2	36827	35	0	0
T3	9450	0	0	0
T9	0	8	0	0
T10	0	34	0	0
T12	0	28	0	0
T13	0	55	0	0
T14	0	15	0	0
T15	0	14	0	0
T16	0	10	0	0
T17	0	7	0	0
T18	0	72	0	0
T19	2995	0	0	0
T20	15327	0	0	0
T21	673	0	0	0
T22	821	0	0	0
T23	890	0	0	0
T24	1457	0	0	0
T25	2051	0	0	0
T26	1387	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	171076067	16368	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171076067	16368	0	0
T2	36827	45	0	0
T3	9450	0	0	0
T9	0	10	0	0
T10	0	52	0	0
T12	0	36	0	0
T13	0	68	0	0
T14	0	19	0	0
T15	0	19	0	0
T16	0	16	0	0
T17	0	8	0	0
T18	0	94	0	0
T19	2995	0	0	0
T20	15327	0	0	0
T21	673	0	0	0
T22	821	0	0	0
T23	890	0	0	0
T24	1457	0	0	0
T25	2051	0	0	0
T26	1387	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	171076067	16294	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171076067	16294	0	0
T2	36827	45	0	0
T3	9450	0	0	0
T9	0	10	0	0
T10	0	53	0	0
T12	0	36	0	0
T13	0	68	0	0
T14	0	19	0	0
T15	0	20	0	0
T16	0	14	0	0
T17	0	8	0	0
T18	0	95	0	0
T19	2995	0	0	0
T20	15327	0	0	0
T21	673	0	0	0
T22	821	0	0	0
T23	890	0	0	0
T24	1457	0	0	0
T25	2051	0	0	0
T26	1387	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	171076067	25088	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171076067	25088	0	0
T2	36827	63	0	0
T3	9450	0	0	0
T9	0	11	0	0
T10	0	87	0	0
T12	0	48	0	0
T13	0	91	0	0
T14	0	23	0	0
T15	0	31	0	0
T16	0	22	0	0
T17	0	10	0	0
T18	0	129	0	0
T19	2995	0	0	0
T20	15327	0	0	0
T21	673	0	0	0
T22	821	0	0	0
T23	890	0	0	0
T24	1457	0	0	0
T25	2051	0	0	0
T26	1387	0	0	0