Go
back
81 always_ff @(posedge clk_i or negedge rst_ni) begin
82 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
83 1/1 err_q <= '0;
Tests: T4 T5 T6
84 1/1 end else if (intg_err || reg_we_err) begin
Tests: T4 T5 T6
85 1/1 err_q <= 1'b1;
Tests: T55 T20 T67
86 end
MISSING_ELSE
87 end
88
89 // integrity error output is permanent and should be used for alert generation
90 // register errors are transactional
91 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T4 T5 T6
92
93 // outgoing integrity generation
94 tlul_pkg::tl_d2h_t tl_o_pre;
95 tlul_rsp_intg_gen #(
96 .EnableRspIntgGen(1),
97 .EnableDataIntgGen(1)
98 ) u_rsp_intg_gen (
99 .tl_i(tl_o_pre),
100 .tl_o(tl_o)
101 );
102
103 1/1 assign tl_reg_h2d = tl_i;
Tests: T4 T5 T6
104 1/1 assign tl_o_pre = tl_reg_d2h;
Tests: T4 T5 T6
105
106 tlul_adapter_reg #(
107 .RegAw(AW),
108 .RegDw(DW),
109 .EnableDataIntgGen(0)
110 ) u_reg_if (
111 .clk_i (clk_i),
112 .rst_ni (rst_ni),
113
114 .tl_i (tl_reg_h2d),
115 .tl_o (tl_reg_d2h),
116
117 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
118 .intg_error_o(),
119
120 .we_o (reg_we),
121 .re_o (reg_re),
122 .addr_o (reg_addr),
123 .wdata_o (reg_wdata),
124 .be_o (reg_be),
125 .busy_i (reg_busy),
126 .rdata_i (reg_rdata),
127 .error_i (reg_error)
128 );
129
130 // cdc oversampling signals
131
132 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T4 T5 T6
133 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T4 T29 T30
134
135 // Define SW related signals
136 // Format: <reg>_<field>_{wd|we|qs}
137 // or <reg>_{wd|we|qs} if field == 1 or 0
138 logic alert_test_we;
139 logic alert_test_recov_fault_wd;
140 logic alert_test_fatal_fault_wd;
141 logic extclk_ctrl_regwen_we;
142 logic extclk_ctrl_regwen_qs;
143 logic extclk_ctrl_regwen_wd;
144 logic extclk_ctrl_we;
145 logic [3:0] extclk_ctrl_sel_qs;
146 logic [3:0] extclk_ctrl_sel_wd;
147 logic [3:0] extclk_ctrl_hi_speed_sel_qs;
148 logic [3:0] extclk_ctrl_hi_speed_sel_wd;
149 logic extclk_status_re;
150 logic [3:0] extclk_status_qs;
151 logic jitter_regwen_we;
152 logic jitter_regwen_qs;
153 logic jitter_regwen_wd;
154 logic jitter_enable_we;
155 logic [3:0] jitter_enable_qs;
156 logic [3:0] jitter_enable_wd;
157 logic clk_enables_we;
158 logic clk_enables_clk_io_div4_peri_en_qs;
159 logic clk_enables_clk_io_div4_peri_en_wd;
160 logic clk_enables_clk_io_div2_peri_en_qs;
161 logic clk_enables_clk_io_div2_peri_en_wd;
162 logic clk_enables_clk_io_peri_en_qs;
163 logic clk_enables_clk_io_peri_en_wd;
164 logic clk_enables_clk_usb_peri_en_qs;
165 logic clk_enables_clk_usb_peri_en_wd;
166 logic clk_hints_we;
167 logic clk_hints_clk_main_aes_hint_qs;
168 logic clk_hints_clk_main_aes_hint_wd;
169 logic clk_hints_clk_main_hmac_hint_qs;
170 logic clk_hints_clk_main_hmac_hint_wd;
171 logic clk_hints_clk_main_kmac_hint_qs;
172 logic clk_hints_clk_main_kmac_hint_wd;
173 logic clk_hints_clk_main_otbn_hint_qs;
174 logic clk_hints_clk_main_otbn_hint_wd;
175 logic clk_hints_status_clk_main_aes_val_qs;
176 logic clk_hints_status_clk_main_hmac_val_qs;
177 logic clk_hints_status_clk_main_kmac_val_qs;
178 logic clk_hints_status_clk_main_otbn_val_qs;
179 logic measure_ctrl_regwen_we;
180 logic measure_ctrl_regwen_qs;
181 logic measure_ctrl_regwen_wd;
182 logic io_meas_ctrl_en_we;
183 logic [3:0] io_meas_ctrl_en_qs;
184 logic io_meas_ctrl_en_busy;
185 logic io_meas_ctrl_shadowed_re;
186 logic io_meas_ctrl_shadowed_we;
187 logic [19:0] io_meas_ctrl_shadowed_qs;
188 logic io_meas_ctrl_shadowed_busy;
189 logic io_meas_ctrl_shadowed_hi_storage_err;
190 logic io_meas_ctrl_shadowed_hi_update_err;
191 logic io_meas_ctrl_shadowed_lo_storage_err;
192 logic io_meas_ctrl_shadowed_lo_update_err;
193 logic io_div2_meas_ctrl_en_we;
194 logic [3:0] io_div2_meas_ctrl_en_qs;
195 logic io_div2_meas_ctrl_en_busy;
196 logic io_div2_meas_ctrl_shadowed_re;
197 logic io_div2_meas_ctrl_shadowed_we;
198 logic [17:0] io_div2_meas_ctrl_shadowed_qs;
199 logic io_div2_meas_ctrl_shadowed_busy;
200 logic io_div2_meas_ctrl_shadowed_hi_storage_err;
201 logic io_div2_meas_ctrl_shadowed_hi_update_err;
202 logic io_div2_meas_ctrl_shadowed_lo_storage_err;
203 logic io_div2_meas_ctrl_shadowed_lo_update_err;
204 logic io_div4_meas_ctrl_en_we;
205 logic [3:0] io_div4_meas_ctrl_en_qs;
206 logic io_div4_meas_ctrl_en_busy;
207 logic io_div4_meas_ctrl_shadowed_re;
208 logic io_div4_meas_ctrl_shadowed_we;
209 logic [15:0] io_div4_meas_ctrl_shadowed_qs;
210 logic io_div4_meas_ctrl_shadowed_busy;
211 logic io_div4_meas_ctrl_shadowed_hi_storage_err;
212 logic io_div4_meas_ctrl_shadowed_hi_update_err;
213 logic io_div4_meas_ctrl_shadowed_lo_storage_err;
214 logic io_div4_meas_ctrl_shadowed_lo_update_err;
215 logic main_meas_ctrl_en_we;
216 logic [3:0] main_meas_ctrl_en_qs;
217 logic main_meas_ctrl_en_busy;
218 logic main_meas_ctrl_shadowed_re;
219 logic main_meas_ctrl_shadowed_we;
220 logic [19:0] main_meas_ctrl_shadowed_qs;
221 logic main_meas_ctrl_shadowed_busy;
222 logic main_meas_ctrl_shadowed_hi_storage_err;
223 logic main_meas_ctrl_shadowed_hi_update_err;
224 logic main_meas_ctrl_shadowed_lo_storage_err;
225 logic main_meas_ctrl_shadowed_lo_update_err;
226 logic usb_meas_ctrl_en_we;
227 logic [3:0] usb_meas_ctrl_en_qs;
228 logic usb_meas_ctrl_en_busy;
229 logic usb_meas_ctrl_shadowed_re;
230 logic usb_meas_ctrl_shadowed_we;
231 logic [17:0] usb_meas_ctrl_shadowed_qs;
232 logic usb_meas_ctrl_shadowed_busy;
233 logic usb_meas_ctrl_shadowed_hi_storage_err;
234 logic usb_meas_ctrl_shadowed_hi_update_err;
235 logic usb_meas_ctrl_shadowed_lo_storage_err;
236 logic usb_meas_ctrl_shadowed_lo_update_err;
237 logic recov_err_code_we;
238 logic recov_err_code_shadow_update_err_qs;
239 logic recov_err_code_shadow_update_err_wd;
240 logic recov_err_code_io_measure_err_qs;
241 logic recov_err_code_io_measure_err_wd;
242 logic recov_err_code_io_div2_measure_err_qs;
243 logic recov_err_code_io_div2_measure_err_wd;
244 logic recov_err_code_io_div4_measure_err_qs;
245 logic recov_err_code_io_div4_measure_err_wd;
246 logic recov_err_code_main_measure_err_qs;
247 logic recov_err_code_main_measure_err_wd;
248 logic recov_err_code_usb_measure_err_qs;
249 logic recov_err_code_usb_measure_err_wd;
250 logic recov_err_code_io_timeout_err_qs;
251 logic recov_err_code_io_timeout_err_wd;
252 logic recov_err_code_io_div2_timeout_err_qs;
253 logic recov_err_code_io_div2_timeout_err_wd;
254 logic recov_err_code_io_div4_timeout_err_qs;
255 logic recov_err_code_io_div4_timeout_err_wd;
256 logic recov_err_code_main_timeout_err_qs;
257 logic recov_err_code_main_timeout_err_wd;
258 logic recov_err_code_usb_timeout_err_qs;
259 logic recov_err_code_usb_timeout_err_wd;
260 logic fatal_err_code_reg_intg_qs;
261 logic fatal_err_code_idle_cnt_qs;
262 logic fatal_err_code_shadow_storage_err_qs;
263 // Define register CDC handling.
264 // CDC handling is done on a per-reg instead of per-field boundary.
265
266 logic [3:0] io_io_meas_ctrl_en_ds_int;
267 logic [3:0] io_io_meas_ctrl_en_qs_int;
268 logic [3:0] io_io_meas_ctrl_en_ds;
269 logic io_io_meas_ctrl_en_qe;
270 logic [3:0] io_io_meas_ctrl_en_qs;
271 logic [3:0] io_io_meas_ctrl_en_wdata;
272 logic io_io_meas_ctrl_en_we;
273 logic unused_io_io_meas_ctrl_en_wdata;
274 logic io_io_meas_ctrl_en_regwen;
275
276 always_comb begin
277 1/1 io_io_meas_ctrl_en_qs = 4'h9;
Tests: T1 T2 T3
278 1/1 io_io_meas_ctrl_en_ds = 4'h9;
Tests: T1 T2 T3
279 1/1 io_io_meas_ctrl_en_ds = io_io_meas_ctrl_en_ds_int;
Tests: T1 T2 T3
280 1/1 io_io_meas_ctrl_en_qs = io_io_meas_ctrl_en_qs_int;
Tests: T1 T2 T3
281 end
282
283 prim_reg_cdc #(
284 .DataWidth(4),
285 .ResetVal(4'h9),
286 .BitMask(4'hf),
287 .DstWrReq(1)
288 ) u_io_meas_ctrl_en_cdc (
289 .clk_src_i (clk_i),
290 .rst_src_ni (rst_ni),
291 .clk_dst_i (clk_io_i),
292 .rst_dst_ni (rst_io_ni),
293 .src_regwen_i (measure_ctrl_regwen_qs),
294 .src_we_i (io_meas_ctrl_en_we),
295 .src_re_i ('0),
296 .src_wd_i (reg_wdata[3:0]),
297 .src_busy_o (io_meas_ctrl_en_busy),
298 .src_qs_o (io_meas_ctrl_en_qs), // for software read back
299 .dst_update_i (io_io_meas_ctrl_en_qe),
300 .dst_ds_i (io_io_meas_ctrl_en_ds),
301 .dst_qs_i (io_io_meas_ctrl_en_qs),
302 .dst_we_o (io_io_meas_ctrl_en_we),
303 .dst_re_o (),
304 .dst_regwen_o (io_io_meas_ctrl_en_regwen),
305 .dst_wd_o (io_io_meas_ctrl_en_wdata)
306 );
307 1/1 assign unused_io_io_meas_ctrl_en_wdata =
Tests: T1 T2 T3
308 ^io_io_meas_ctrl_en_wdata;
309
310 logic [9:0] io_io_meas_ctrl_shadowed_hi_qs_int;
311 logic [9:0] io_io_meas_ctrl_shadowed_lo_qs_int;
312 logic [19:0] io_io_meas_ctrl_shadowed_qs;
313 logic [19:0] io_io_meas_ctrl_shadowed_wdata;
314 logic io_io_meas_ctrl_shadowed_we;
315 logic unused_io_io_meas_ctrl_shadowed_wdata;
316 logic io_io_meas_ctrl_shadowed_re;
317 logic io_io_meas_ctrl_shadowed_regwen;
318
319 always_comb begin
320 1/1 io_io_meas_ctrl_shadowed_qs = 20'h759ea;
Tests: T1 T2 T3
321 1/1 io_io_meas_ctrl_shadowed_qs[9:0] = io_io_meas_ctrl_shadowed_hi_qs_int;
Tests: T1 T2 T3
322 1/1 io_io_meas_ctrl_shadowed_qs[19:10] = io_io_meas_ctrl_shadowed_lo_qs_int;
Tests: T1 T2 T3
323 end
324
325 prim_reg_cdc #(
326 .DataWidth(20),
327 .ResetVal(20'h759ea),
328 .BitMask(20'hfffff),
329 .DstWrReq(0)
330 ) u_io_meas_ctrl_shadowed_cdc (
331 .clk_src_i (clk_i),
332 .rst_src_ni (rst_ni),
333 .clk_dst_i (clk_io_i),
334 .rst_dst_ni (rst_io_ni),
335 .src_regwen_i (measure_ctrl_regwen_qs),
336 .src_we_i (io_meas_ctrl_shadowed_we),
337 .src_re_i (io_meas_ctrl_shadowed_re),
338 .src_wd_i (reg_wdata[19:0]),
339 .src_busy_o (io_meas_ctrl_shadowed_busy),
340 .src_qs_o (io_meas_ctrl_shadowed_qs), // for software read back
341 .dst_update_i ('0),
342 .dst_ds_i ('0),
343 .dst_qs_i (io_io_meas_ctrl_shadowed_qs),
344 .dst_we_o (io_io_meas_ctrl_shadowed_we),
345 .dst_re_o (io_io_meas_ctrl_shadowed_re),
346 .dst_regwen_o (io_io_meas_ctrl_shadowed_regwen),
347 .dst_wd_o (io_io_meas_ctrl_shadowed_wdata)
348 );
349 1/1 assign unused_io_io_meas_ctrl_shadowed_wdata =
Tests: T1 T2 T3
350 ^io_io_meas_ctrl_shadowed_wdata;
351
352 logic [3:0] io_div2_io_div2_meas_ctrl_en_ds_int;
353 logic [3:0] io_div2_io_div2_meas_ctrl_en_qs_int;
354 logic [3:0] io_div2_io_div2_meas_ctrl_en_ds;
355 logic io_div2_io_div2_meas_ctrl_en_qe;
356 logic [3:0] io_div2_io_div2_meas_ctrl_en_qs;
357 logic [3:0] io_div2_io_div2_meas_ctrl_en_wdata;
358 logic io_div2_io_div2_meas_ctrl_en_we;
359 logic unused_io_div2_io_div2_meas_ctrl_en_wdata;
360 logic io_div2_io_div2_meas_ctrl_en_regwen;
361
362 always_comb begin
363 1/1 io_div2_io_div2_meas_ctrl_en_qs = 4'h9;
Tests: T1 T2 T3
364 1/1 io_div2_io_div2_meas_ctrl_en_ds = 4'h9;
Tests: T1 T2 T3
365 1/1 io_div2_io_div2_meas_ctrl_en_ds = io_div2_io_div2_meas_ctrl_en_ds_int;
Tests: T1 T2 T3
366 1/1 io_div2_io_div2_meas_ctrl_en_qs = io_div2_io_div2_meas_ctrl_en_qs_int;
Tests: T1 T2 T3
367 end
368
369 prim_reg_cdc #(
370 .DataWidth(4),
371 .ResetVal(4'h9),
372 .BitMask(4'hf),
373 .DstWrReq(1)
374 ) u_io_div2_meas_ctrl_en_cdc (
375 .clk_src_i (clk_i),
376 .rst_src_ni (rst_ni),
377 .clk_dst_i (clk_io_div2_i),
378 .rst_dst_ni (rst_io_div2_ni),
379 .src_regwen_i (measure_ctrl_regwen_qs),
380 .src_we_i (io_div2_meas_ctrl_en_we),
381 .src_re_i ('0),
382 .src_wd_i (reg_wdata[3:0]),
383 .src_busy_o (io_div2_meas_ctrl_en_busy),
384 .src_qs_o (io_div2_meas_ctrl_en_qs), // for software read back
385 .dst_update_i (io_div2_io_div2_meas_ctrl_en_qe),
386 .dst_ds_i (io_div2_io_div2_meas_ctrl_en_ds),
387 .dst_qs_i (io_div2_io_div2_meas_ctrl_en_qs),
388 .dst_we_o (io_div2_io_div2_meas_ctrl_en_we),
389 .dst_re_o (),
390 .dst_regwen_o (io_div2_io_div2_meas_ctrl_en_regwen),
391 .dst_wd_o (io_div2_io_div2_meas_ctrl_en_wdata)
392 );
393 1/1 assign unused_io_div2_io_div2_meas_ctrl_en_wdata =
Tests: T1 T2 T3
394 ^io_div2_io_div2_meas_ctrl_en_wdata;
395
396 logic [8:0] io_div2_io_div2_meas_ctrl_shadowed_hi_qs_int;
397 logic [8:0] io_div2_io_div2_meas_ctrl_shadowed_lo_qs_int;
398 logic [17:0] io_div2_io_div2_meas_ctrl_shadowed_qs;
399 logic [17:0] io_div2_io_div2_meas_ctrl_shadowed_wdata;
400 logic io_div2_io_div2_meas_ctrl_shadowed_we;
401 logic unused_io_div2_io_div2_meas_ctrl_shadowed_wdata;
402 logic io_div2_io_div2_meas_ctrl_shadowed_re;
403 logic io_div2_io_div2_meas_ctrl_shadowed_regwen;
404
405 always_comb begin
406 1/1 io_div2_io_div2_meas_ctrl_shadowed_qs = 18'h1ccfa;
Tests: T1 T2 T3
407 1/1 io_div2_io_div2_meas_ctrl_shadowed_qs[8:0] = io_div2_io_div2_meas_ctrl_shadowed_hi_qs_int;
Tests: T1 T2 T3
408 1/1 io_div2_io_div2_meas_ctrl_shadowed_qs[17:9] = io_div2_io_div2_meas_ctrl_shadowed_lo_qs_int;
Tests: T1 T2 T3
409 end
410
411 prim_reg_cdc #(
412 .DataWidth(18),
413 .ResetVal(18'h1ccfa),
414 .BitMask(18'h3ffff),
415 .DstWrReq(0)
416 ) u_io_div2_meas_ctrl_shadowed_cdc (
417 .clk_src_i (clk_i),
418 .rst_src_ni (rst_ni),
419 .clk_dst_i (clk_io_div2_i),
420 .rst_dst_ni (rst_io_div2_ni),
421 .src_regwen_i (measure_ctrl_regwen_qs),
422 .src_we_i (io_div2_meas_ctrl_shadowed_we),
423 .src_re_i (io_div2_meas_ctrl_shadowed_re),
424 .src_wd_i (reg_wdata[17:0]),
425 .src_busy_o (io_div2_meas_ctrl_shadowed_busy),
426 .src_qs_o (io_div2_meas_ctrl_shadowed_qs), // for software read back
427 .dst_update_i ('0),
428 .dst_ds_i ('0),
429 .dst_qs_i (io_div2_io_div2_meas_ctrl_shadowed_qs),
430 .dst_we_o (io_div2_io_div2_meas_ctrl_shadowed_we),
431 .dst_re_o (io_div2_io_div2_meas_ctrl_shadowed_re),
432 .dst_regwen_o (io_div2_io_div2_meas_ctrl_shadowed_regwen),
433 .dst_wd_o (io_div2_io_div2_meas_ctrl_shadowed_wdata)
434 );
435 1/1 assign unused_io_div2_io_div2_meas_ctrl_shadowed_wdata =
Tests: T1 T2 T3
436 ^io_div2_io_div2_meas_ctrl_shadowed_wdata;
437
438 logic [3:0] io_div4_io_div4_meas_ctrl_en_ds_int;
439 logic [3:0] io_div4_io_div4_meas_ctrl_en_qs_int;
440 logic [3:0] io_div4_io_div4_meas_ctrl_en_ds;
441 logic io_div4_io_div4_meas_ctrl_en_qe;
442 logic [3:0] io_div4_io_div4_meas_ctrl_en_qs;
443 logic [3:0] io_div4_io_div4_meas_ctrl_en_wdata;
444 logic io_div4_io_div4_meas_ctrl_en_we;
445 logic unused_io_div4_io_div4_meas_ctrl_en_wdata;
446 logic io_div4_io_div4_meas_ctrl_en_regwen;
447
448 always_comb begin
449 1/1 io_div4_io_div4_meas_ctrl_en_qs = 4'h9;
Tests: T1 T2 T3
450 1/1 io_div4_io_div4_meas_ctrl_en_ds = 4'h9;
Tests: T1 T2 T3
451 1/1 io_div4_io_div4_meas_ctrl_en_ds = io_div4_io_div4_meas_ctrl_en_ds_int;
Tests: T1 T2 T3
452 1/1 io_div4_io_div4_meas_ctrl_en_qs = io_div4_io_div4_meas_ctrl_en_qs_int;
Tests: T1 T2 T3
453 end
454
455 prim_reg_cdc #(
456 .DataWidth(4),
457 .ResetVal(4'h9),
458 .BitMask(4'hf),
459 .DstWrReq(1)
460 ) u_io_div4_meas_ctrl_en_cdc (
461 .clk_src_i (clk_i),
462 .rst_src_ni (rst_ni),
463 .clk_dst_i (clk_io_div4_i),
464 .rst_dst_ni (rst_io_div4_ni),
465 .src_regwen_i (measure_ctrl_regwen_qs),
466 .src_we_i (io_div4_meas_ctrl_en_we),
467 .src_re_i ('0),
468 .src_wd_i (reg_wdata[3:0]),
469 .src_busy_o (io_div4_meas_ctrl_en_busy),
470 .src_qs_o (io_div4_meas_ctrl_en_qs), // for software read back
471 .dst_update_i (io_div4_io_div4_meas_ctrl_en_qe),
472 .dst_ds_i (io_div4_io_div4_meas_ctrl_en_ds),
473 .dst_qs_i (io_div4_io_div4_meas_ctrl_en_qs),
474 .dst_we_o (io_div4_io_div4_meas_ctrl_en_we),
475 .dst_re_o (),
476 .dst_regwen_o (io_div4_io_div4_meas_ctrl_en_regwen),
477 .dst_wd_o (io_div4_io_div4_meas_ctrl_en_wdata)
478 );
479 1/1 assign unused_io_div4_io_div4_meas_ctrl_en_wdata =
Tests: T1 T2 T3
480 ^io_div4_io_div4_meas_ctrl_en_wdata;
481
482 logic [7:0] io_div4_io_div4_meas_ctrl_shadowed_hi_qs_int;
483 logic [7:0] io_div4_io_div4_meas_ctrl_shadowed_lo_qs_int;
484 logic [15:0] io_div4_io_div4_meas_ctrl_shadowed_qs;
485 logic [15:0] io_div4_io_div4_meas_ctrl_shadowed_wdata;
486 logic io_div4_io_div4_meas_ctrl_shadowed_we;
487 logic unused_io_div4_io_div4_meas_ctrl_shadowed_wdata;
488 logic io_div4_io_div4_meas_ctrl_shadowed_re;
489 logic io_div4_io_div4_meas_ctrl_shadowed_regwen;
490
491 always_comb begin
492 1/1 io_div4_io_div4_meas_ctrl_shadowed_qs = 16'h6e82;
Tests: T1 T2 T3
493 1/1 io_div4_io_div4_meas_ctrl_shadowed_qs[7:0] = io_div4_io_div4_meas_ctrl_shadowed_hi_qs_int;
Tests: T1 T2 T3
494 1/1 io_div4_io_div4_meas_ctrl_shadowed_qs[15:8] = io_div4_io_div4_meas_ctrl_shadowed_lo_qs_int;
Tests: T1 T2 T3
495 end
496
497 prim_reg_cdc #(
498 .DataWidth(16),
499 .ResetVal(16'h6e82),
500 .BitMask(16'hffff),
501 .DstWrReq(0)
502 ) u_io_div4_meas_ctrl_shadowed_cdc (
503 .clk_src_i (clk_i),
504 .rst_src_ni (rst_ni),
505 .clk_dst_i (clk_io_div4_i),
506 .rst_dst_ni (rst_io_div4_ni),
507 .src_regwen_i (measure_ctrl_regwen_qs),
508 .src_we_i (io_div4_meas_ctrl_shadowed_we),
509 .src_re_i (io_div4_meas_ctrl_shadowed_re),
510 .src_wd_i (reg_wdata[15:0]),
511 .src_busy_o (io_div4_meas_ctrl_shadowed_busy),
512 .src_qs_o (io_div4_meas_ctrl_shadowed_qs), // for software read back
513 .dst_update_i ('0),
514 .dst_ds_i ('0),
515 .dst_qs_i (io_div4_io_div4_meas_ctrl_shadowed_qs),
516 .dst_we_o (io_div4_io_div4_meas_ctrl_shadowed_we),
517 .dst_re_o (io_div4_io_div4_meas_ctrl_shadowed_re),
518 .dst_regwen_o (io_div4_io_div4_meas_ctrl_shadowed_regwen),
519 .dst_wd_o (io_div4_io_div4_meas_ctrl_shadowed_wdata)
520 );
521 1/1 assign unused_io_div4_io_div4_meas_ctrl_shadowed_wdata =
Tests: T1 T2 T3
522 ^io_div4_io_div4_meas_ctrl_shadowed_wdata;
523
524 logic [3:0] main_main_meas_ctrl_en_ds_int;
525 logic [3:0] main_main_meas_ctrl_en_qs_int;
526 logic [3:0] main_main_meas_ctrl_en_ds;
527 logic main_main_meas_ctrl_en_qe;
528 logic [3:0] main_main_meas_ctrl_en_qs;
529 logic [3:0] main_main_meas_ctrl_en_wdata;
530 logic main_main_meas_ctrl_en_we;
531 logic unused_main_main_meas_ctrl_en_wdata;
532 logic main_main_meas_ctrl_en_regwen;
533
534 always_comb begin
535 1/1 main_main_meas_ctrl_en_qs = 4'h9;
Tests: T1 T2 T3
536 1/1 main_main_meas_ctrl_en_ds = 4'h9;
Tests: T1 T2 T3
537 1/1 main_main_meas_ctrl_en_ds = main_main_meas_ctrl_en_ds_int;
Tests: T1 T2 T3
538 1/1 main_main_meas_ctrl_en_qs = main_main_meas_ctrl_en_qs_int;
Tests: T1 T2 T3
539 end
540
541 prim_reg_cdc #(
542 .DataWidth(4),
543 .ResetVal(4'h9),
544 .BitMask(4'hf),
545 .DstWrReq(1)
546 ) u_main_meas_ctrl_en_cdc (
547 .clk_src_i (clk_i),
548 .rst_src_ni (rst_ni),
549 .clk_dst_i (clk_main_i),
550 .rst_dst_ni (rst_main_ni),
551 .src_regwen_i (measure_ctrl_regwen_qs),
552 .src_we_i (main_meas_ctrl_en_we),
553 .src_re_i ('0),
554 .src_wd_i (reg_wdata[3:0]),
555 .src_busy_o (main_meas_ctrl_en_busy),
556 .src_qs_o (main_meas_ctrl_en_qs), // for software read back
557 .dst_update_i (main_main_meas_ctrl_en_qe),
558 .dst_ds_i (main_main_meas_ctrl_en_ds),
559 .dst_qs_i (main_main_meas_ctrl_en_qs),
560 .dst_we_o (main_main_meas_ctrl_en_we),
561 .dst_re_o (),
562 .dst_regwen_o (main_main_meas_ctrl_en_regwen),
563 .dst_wd_o (main_main_meas_ctrl_en_wdata)
564 );
565 1/1 assign unused_main_main_meas_ctrl_en_wdata =
Tests: T1 T2 T3
566 ^main_main_meas_ctrl_en_wdata;
567
568 logic [9:0] main_main_meas_ctrl_shadowed_hi_qs_int;
569 logic [9:0] main_main_meas_ctrl_shadowed_lo_qs_int;
570 logic [19:0] main_main_meas_ctrl_shadowed_qs;
571 logic [19:0] main_main_meas_ctrl_shadowed_wdata;
572 logic main_main_meas_ctrl_shadowed_we;
573 logic unused_main_main_meas_ctrl_shadowed_wdata;
574 logic main_main_meas_ctrl_shadowed_re;
575 logic main_main_meas_ctrl_shadowed_regwen;
576
577 always_comb begin
578 1/1 main_main_meas_ctrl_shadowed_qs = 20'h7a9fe;
Tests: T1 T2 T3
579 1/1 main_main_meas_ctrl_shadowed_qs[9:0] = main_main_meas_ctrl_shadowed_hi_qs_int;
Tests: T1 T2 T3
580 1/1 main_main_meas_ctrl_shadowed_qs[19:10] = main_main_meas_ctrl_shadowed_lo_qs_int;
Tests: T1 T2 T3
581 end
582
583 prim_reg_cdc #(
584 .DataWidth(20),
585 .ResetVal(20'h7a9fe),
586 .BitMask(20'hfffff),
587 .DstWrReq(0)
588 ) u_main_meas_ctrl_shadowed_cdc (
589 .clk_src_i (clk_i),
590 .rst_src_ni (rst_ni),
591 .clk_dst_i (clk_main_i),
592 .rst_dst_ni (rst_main_ni),
593 .src_regwen_i (measure_ctrl_regwen_qs),
594 .src_we_i (main_meas_ctrl_shadowed_we),
595 .src_re_i (main_meas_ctrl_shadowed_re),
596 .src_wd_i (reg_wdata[19:0]),
597 .src_busy_o (main_meas_ctrl_shadowed_busy),
598 .src_qs_o (main_meas_ctrl_shadowed_qs), // for software read back
599 .dst_update_i ('0),
600 .dst_ds_i ('0),
601 .dst_qs_i (main_main_meas_ctrl_shadowed_qs),
602 .dst_we_o (main_main_meas_ctrl_shadowed_we),
603 .dst_re_o (main_main_meas_ctrl_shadowed_re),
604 .dst_regwen_o (main_main_meas_ctrl_shadowed_regwen),
605 .dst_wd_o (main_main_meas_ctrl_shadowed_wdata)
606 );
607 1/1 assign unused_main_main_meas_ctrl_shadowed_wdata =
Tests: T1 T2 T3
608 ^main_main_meas_ctrl_shadowed_wdata;
609
610 logic [3:0] usb_usb_meas_ctrl_en_ds_int;
611 logic [3:0] usb_usb_meas_ctrl_en_qs_int;
612 logic [3:0] usb_usb_meas_ctrl_en_ds;
613 logic usb_usb_meas_ctrl_en_qe;
614 logic [3:0] usb_usb_meas_ctrl_en_qs;
615 logic [3:0] usb_usb_meas_ctrl_en_wdata;
616 logic usb_usb_meas_ctrl_en_we;
617 logic unused_usb_usb_meas_ctrl_en_wdata;
618 logic usb_usb_meas_ctrl_en_regwen;
619
620 always_comb begin
621 1/1 usb_usb_meas_ctrl_en_qs = 4'h9;
Tests: T1 T2 T3
622 1/1 usb_usb_meas_ctrl_en_ds = 4'h9;
Tests: T1 T2 T3
623 1/1 usb_usb_meas_ctrl_en_ds = usb_usb_meas_ctrl_en_ds_int;
Tests: T1 T2 T3
624 1/1 usb_usb_meas_ctrl_en_qs = usb_usb_meas_ctrl_en_qs_int;
Tests: T1 T2 T3
625 end
626
627 prim_reg_cdc #(
628 .DataWidth(4),
629 .ResetVal(4'h9),
630 .BitMask(4'hf),
631 .DstWrReq(1)
632 ) u_usb_meas_ctrl_en_cdc (
633 .clk_src_i (clk_i),
634 .rst_src_ni (rst_ni),
635 .clk_dst_i (clk_usb_i),
636 .rst_dst_ni (rst_usb_ni),
637 .src_regwen_i (measure_ctrl_regwen_qs),
638 .src_we_i (usb_meas_ctrl_en_we),
639 .src_re_i ('0),
640 .src_wd_i (reg_wdata[3:0]),
641 .src_busy_o (usb_meas_ctrl_en_busy),
642 .src_qs_o (usb_meas_ctrl_en_qs), // for software read back
643 .dst_update_i (usb_usb_meas_ctrl_en_qe),
644 .dst_ds_i (usb_usb_meas_ctrl_en_ds),
645 .dst_qs_i (usb_usb_meas_ctrl_en_qs),
646 .dst_we_o (usb_usb_meas_ctrl_en_we),
647 .dst_re_o (),
648 .dst_regwen_o (usb_usb_meas_ctrl_en_regwen),
649 .dst_wd_o (usb_usb_meas_ctrl_en_wdata)
650 );
651 1/1 assign unused_usb_usb_meas_ctrl_en_wdata =
Tests: T1 T2 T3
652 ^usb_usb_meas_ctrl_en_wdata;
653
654 logic [8:0] usb_usb_meas_ctrl_shadowed_hi_qs_int;
655 logic [8:0] usb_usb_meas_ctrl_shadowed_lo_qs_int;
656 logic [17:0] usb_usb_meas_ctrl_shadowed_qs;
657 logic [17:0] usb_usb_meas_ctrl_shadowed_wdata;
658 logic usb_usb_meas_ctrl_shadowed_we;
659 logic unused_usb_usb_meas_ctrl_shadowed_wdata;
660 logic usb_usb_meas_ctrl_shadowed_re;
661 logic usb_usb_meas_ctrl_shadowed_regwen;
662
663 always_comb begin
664 1/1 usb_usb_meas_ctrl_shadowed_qs = 18'h1ccfa;
Tests: T1 T2 T3
665 1/1 usb_usb_meas_ctrl_shadowed_qs[8:0] = usb_usb_meas_ctrl_shadowed_hi_qs_int;
Tests: T1 T2 T3
666 1/1 usb_usb_meas_ctrl_shadowed_qs[17:9] = usb_usb_meas_ctrl_shadowed_lo_qs_int;
Tests: T1 T2 T3
667 end
668
669 prim_reg_cdc #(
670 .DataWidth(18),
671 .ResetVal(18'h1ccfa),
672 .BitMask(18'h3ffff),
673 .DstWrReq(0)
674 ) u_usb_meas_ctrl_shadowed_cdc (
675 .clk_src_i (clk_i),
676 .rst_src_ni (rst_ni),
677 .clk_dst_i (clk_usb_i),
678 .rst_dst_ni (rst_usb_ni),
679 .src_regwen_i (measure_ctrl_regwen_qs),
680 .src_we_i (usb_meas_ctrl_shadowed_we),
681 .src_re_i (usb_meas_ctrl_shadowed_re),
682 .src_wd_i (reg_wdata[17:0]),
683 .src_busy_o (usb_meas_ctrl_shadowed_busy),
684 .src_qs_o (usb_meas_ctrl_shadowed_qs), // for software read back
685 .dst_update_i ('0),
686 .dst_ds_i ('0),
687 .dst_qs_i (usb_usb_meas_ctrl_shadowed_qs),
688 .dst_we_o (usb_usb_meas_ctrl_shadowed_we),
689 .dst_re_o (usb_usb_meas_ctrl_shadowed_re),
690 .dst_regwen_o (usb_usb_meas_ctrl_shadowed_regwen),
691 .dst_wd_o (usb_usb_meas_ctrl_shadowed_wdata)
692 );
693 1/1 assign unused_usb_usb_meas_ctrl_shadowed_wdata =
Tests: T1 T2 T3
694 ^usb_usb_meas_ctrl_shadowed_wdata;
695
696 // Register instances
697 // R[alert_test]: V(True)
698 logic alert_test_qe;
699 logic [1:0] alert_test_flds_we;
700 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T69 T22 T64
701 // F[recov_fault]: 0:0
702 prim_subreg_ext #(
703 .DW (1)
704 ) u_alert_test_recov_fault (
705 .re (1'b0),
706 .we (alert_test_we),
707 .wd (alert_test_recov_fault_wd),
708 .d ('0),
709 .qre (),
710 .qe (alert_test_flds_we[0]),
711 .q (reg2hw.alert_test.recov_fault.q),
712 .ds (),
713 .qs ()
714 );
715 1/1 assign reg2hw.alert_test.recov_fault.qe = alert_test_qe;
Tests: T69 T22 T64
716
717 // F[fatal_fault]: 1:1
718 prim_subreg_ext #(
719 .DW (1)
720 ) u_alert_test_fatal_fault (
721 .re (1'b0),
722 .we (alert_test_we),
723 .wd (alert_test_fatal_fault_wd),
724 .d ('0),
725 .qre (),
726 .qe (alert_test_flds_we[1]),
727 .q (reg2hw.alert_test.fatal_fault.q),
728 .ds (),
729 .qs ()
730 );
731 1/1 assign reg2hw.alert_test.fatal_fault.qe = alert_test_qe;
Tests: T69 T22 T64
732
733
734 // R[extclk_ctrl_regwen]: V(False)
735 prim_subreg #(
736 .DW (1),
737 .SwAccess(prim_subreg_pkg::SwAccessW0C),
738 .RESVAL (1'h1),
739 .Mubi (1'b0)
740 ) u_extclk_ctrl_regwen (
741 .clk_i (clk_i),
742 .rst_ni (rst_ni),
743
744 // from register interface
745 .we (extclk_ctrl_regwen_we),
746 .wd (extclk_ctrl_regwen_wd),
747
748 // from internal hardware
749 .de (1'b0),
750 .d ('0),
751
752 // to internal hardware
753 .qe (),
754 .q (),
755 .ds (),
756
757 // to register interface (read)
758 .qs (extclk_ctrl_regwen_qs)
759 );
760
761
762 // R[extclk_ctrl]: V(False)
763 // Create REGWEN-gated WE signal
764 logic extclk_ctrl_gated_we;
765 1/1 assign extclk_ctrl_gated_we = extclk_ctrl_we & extclk_ctrl_regwen_qs;
Tests: T5 T30 T31
766 // F[sel]: 3:0
767 prim_subreg #(
768 .DW (4),
769 .SwAccess(prim_subreg_pkg::SwAccessRW),
770 .RESVAL (4'h9),
771 .Mubi (1'b1)
772 ) u_extclk_ctrl_sel (
773 .clk_i (clk_i),
774 .rst_ni (rst_ni),
775
776 // from register interface
777 .we (extclk_ctrl_gated_we),
778 .wd (extclk_ctrl_sel_wd),
779
780 // from internal hardware
781 .de (1'b0),
782 .d ('0),
783
784 // to internal hardware
785 .qe (),
786 .q (reg2hw.extclk_ctrl.sel.q),
787 .ds (),
788
789 // to register interface (read)
790 .qs (extclk_ctrl_sel_qs)
791 );
792
793 // F[hi_speed_sel]: 7:4
794 prim_subreg #(
795 .DW (4),
796 .SwAccess(prim_subreg_pkg::SwAccessRW),
797 .RESVAL (4'h9),
798 .Mubi (1'b1)
799 ) u_extclk_ctrl_hi_speed_sel (
800 .clk_i (clk_i),
801 .rst_ni (rst_ni),
802
803 // from register interface
804 .we (extclk_ctrl_gated_we),
805 .wd (extclk_ctrl_hi_speed_sel_wd),
806
807 // from internal hardware
808 .de (1'b0),
809 .d ('0),
810
811 // to internal hardware
812 .qe (),
813 .q (reg2hw.extclk_ctrl.hi_speed_sel.q),
814 .ds (),
815
816 // to register interface (read)
817 .qs (extclk_ctrl_hi_speed_sel_qs)
818 );
819
820
821 // R[extclk_status]: V(True)
822 prim_subreg_ext #(
823 .DW (4)
824 ) u_extclk_status (
825 .re (extclk_status_re),
826 .we (1'b0),
827 .wd ('0),
828 .d (hw2reg.extclk_status.d),
829 .qre (),
830 .qe (),
831 .q (),
832 .ds (),
833 .qs (extclk_status_qs)
834 );
835
836
837 // R[jitter_regwen]: V(False)
838 prim_subreg #(
839 .DW (1),
840 .SwAccess(prim_subreg_pkg::SwAccessW0C),
841 .RESVAL (1'h1),
842 .Mubi (1'b0)
843 ) u_jitter_regwen (
844 .clk_i (clk_i),
845 .rst_ni (rst_ni),
846
847 // from register interface
848 .we (jitter_regwen_we),
849 .wd (jitter_regwen_wd),
850
851 // from internal hardware
852 .de (1'b0),
853 .d ('0),
854
855 // to internal hardware
856 .qe (),
857 .q (),
858 .ds (),
859
860 // to register interface (read)
861 .qs (jitter_regwen_qs)
862 );
863
864
865 // R[jitter_enable]: V(False)
866 prim_subreg #(
867 .DW (4),
868 .SwAccess(prim_subreg_pkg::SwAccessRW),
869 .RESVAL (4'h9),
870 .Mubi (1'b1)
871 ) u_jitter_enable (
872 .clk_i (clk_i),
873 .rst_ni (rst_ni),
874
875 // from register interface
876 .we (jitter_enable_we),
877 .wd (prim_mubi_pkg::MuBi4True),
878
879 // from internal hardware
880 .de (1'b0),
881 .d ('0),
882
883 // to internal hardware
884 .qe (),
885 .q (reg2hw.jitter_enable.q),
886 .ds (),
887
888 // to register interface (read)
889 .qs (jitter_enable_qs)
890 );
891
892
893 // R[clk_enables]: V(False)
894 // F[clk_io_div4_peri_en]: 0:0
895 prim_subreg #(
896 .DW (1),
897 .SwAccess(prim_subreg_pkg::SwAccessRW),
898 .RESVAL (1'h1),
899 .Mubi (1'b0)
900 ) u_clk_enables_clk_io_div4_peri_en (
901 .clk_i (clk_i),
902 .rst_ni (rst_ni),
903
904 // from register interface
905 .we (clk_enables_we),
906 .wd (clk_enables_clk_io_div4_peri_en_wd),
907
908 // from internal hardware
909 .de (1'b0),
910 .d ('0),
911
912 // to internal hardware
913 .qe (),
914 .q (reg2hw.clk_enables.clk_io_div4_peri_en.q),
915 .ds (),
916
917 // to register interface (read)
918 .qs (clk_enables_clk_io_div4_peri_en_qs)
919 );
920
921 // F[clk_io_div2_peri_en]: 1:1
922 prim_subreg #(
923 .DW (1),
924 .SwAccess(prim_subreg_pkg::SwAccessRW),
925 .RESVAL (1'h1),
926 .Mubi (1'b0)
927 ) u_clk_enables_clk_io_div2_peri_en (
928 .clk_i (clk_i),
929 .rst_ni (rst_ni),
930
931 // from register interface
932 .we (clk_enables_we),
933 .wd (clk_enables_clk_io_div2_peri_en_wd),
934
935 // from internal hardware
936 .de (1'b0),
937 .d ('0),
938
939 // to internal hardware
940 .qe (),
941 .q (reg2hw.clk_enables.clk_io_div2_peri_en.q),
942 .ds (),
943
944 // to register interface (read)
945 .qs (clk_enables_clk_io_div2_peri_en_qs)
946 );
947
948 // F[clk_io_peri_en]: 2:2
949 prim_subreg #(
950 .DW (1),
951 .SwAccess(prim_subreg_pkg::SwAccessRW),
952 .RESVAL (1'h1),
953 .Mubi (1'b0)
954 ) u_clk_enables_clk_io_peri_en (
955 .clk_i (clk_i),
956 .rst_ni (rst_ni),
957
958 // from register interface
959 .we (clk_enables_we),
960 .wd (clk_enables_clk_io_peri_en_wd),
961
962 // from internal hardware
963 .de (1'b0),
964 .d ('0),
965
966 // to internal hardware
967 .qe (),
968 .q (reg2hw.clk_enables.clk_io_peri_en.q),
969 .ds (),
970
971 // to register interface (read)
972 .qs (clk_enables_clk_io_peri_en_qs)
973 );
974
975 // F[clk_usb_peri_en]: 3:3
976 prim_subreg #(
977 .DW (1),
978 .SwAccess(prim_subreg_pkg::SwAccessRW),
979 .RESVAL (1'h1),
980 .Mubi (1'b0)
981 ) u_clk_enables_clk_usb_peri_en (
982 .clk_i (clk_i),
983 .rst_ni (rst_ni),
984
985 // from register interface
986 .we (clk_enables_we),
987 .wd (clk_enables_clk_usb_peri_en_wd),
988
989 // from internal hardware
990 .de (1'b0),
991 .d ('0),
992
993 // to internal hardware
994 .qe (),
995 .q (reg2hw.clk_enables.clk_usb_peri_en.q),
996 .ds (),
997
998 // to register interface (read)
999 .qs (clk_enables_clk_usb_peri_en_qs)
1000 );
1001
1002
1003 // R[clk_hints]: V(False)
1004 // F[clk_main_aes_hint]: 0:0
1005 prim_subreg #(
1006 .DW (1),
1007 .SwAccess(prim_subreg_pkg::SwAccessRW),
1008 .RESVAL (1'h1),
1009 .Mubi (1'b0)
1010 ) u_clk_hints_clk_main_aes_hint (
1011 .clk_i (clk_i),
1012 .rst_ni (rst_ni),
1013
1014 // from register interface
1015 .we (clk_hints_we),
1016 .wd (clk_hints_clk_main_aes_hint_wd),
1017
1018 // from internal hardware
1019 .de (1'b0),
1020 .d ('0),
1021
1022 // to internal hardware
1023 .qe (),
1024 .q (reg2hw.clk_hints.clk_main_aes_hint.q),
1025 .ds (),
1026
1027 // to register interface (read)
1028 .qs (clk_hints_clk_main_aes_hint_qs)
1029 );
1030
1031 // F[clk_main_hmac_hint]: 1:1
1032 prim_subreg #(
1033 .DW (1),
1034 .SwAccess(prim_subreg_pkg::SwAccessRW),
1035 .RESVAL (1'h1),
1036 .Mubi (1'b0)
1037 ) u_clk_hints_clk_main_hmac_hint (
1038 .clk_i (clk_i),
1039 .rst_ni (rst_ni),
1040
1041 // from register interface
1042 .we (clk_hints_we),
1043 .wd (clk_hints_clk_main_hmac_hint_wd),
1044
1045 // from internal hardware
1046 .de (1'b0),
1047 .d ('0),
1048
1049 // to internal hardware
1050 .qe (),
1051 .q (reg2hw.clk_hints.clk_main_hmac_hint.q),
1052 .ds (),
1053
1054 // to register interface (read)
1055 .qs (clk_hints_clk_main_hmac_hint_qs)
1056 );
1057
1058 // F[clk_main_kmac_hint]: 2:2
1059 prim_subreg #(
1060 .DW (1),
1061 .SwAccess(prim_subreg_pkg::SwAccessRW),
1062 .RESVAL (1'h1),
1063 .Mubi (1'b0)
1064 ) u_clk_hints_clk_main_kmac_hint (
1065 .clk_i (clk_i),
1066 .rst_ni (rst_ni),
1067
1068 // from register interface
1069 .we (clk_hints_we),
1070 .wd (clk_hints_clk_main_kmac_hint_wd),
1071
1072 // from internal hardware
1073 .de (1'b0),
1074 .d ('0),
1075
1076 // to internal hardware
1077 .qe (),
1078 .q (reg2hw.clk_hints.clk_main_kmac_hint.q),
1079 .ds (),
1080
1081 // to register interface (read)
1082 .qs (clk_hints_clk_main_kmac_hint_qs)
1083 );
1084
1085 // F[clk_main_otbn_hint]: 3:3
1086 prim_subreg #(
1087 .DW (1),
1088 .SwAccess(prim_subreg_pkg::SwAccessRW),
1089 .RESVAL (1'h1),
1090 .Mubi (1'b0)
1091 ) u_clk_hints_clk_main_otbn_hint (
1092 .clk_i (clk_i),
1093 .rst_ni (rst_ni),
1094
1095 // from register interface
1096 .we (clk_hints_we),
1097 .wd (clk_hints_clk_main_otbn_hint_wd),
1098
1099 // from internal hardware
1100 .de (1'b0),
1101 .d ('0),
1102
1103 // to internal hardware
1104 .qe (),
1105 .q (reg2hw.clk_hints.clk_main_otbn_hint.q),
1106 .ds (),
1107
1108 // to register interface (read)
1109 .qs (clk_hints_clk_main_otbn_hint_qs)
1110 );
1111
1112
1113 // R[clk_hints_status]: V(False)
1114 // F[clk_main_aes_val]: 0:0
1115 prim_subreg #(
1116 .DW (1),
1117 .SwAccess(prim_subreg_pkg::SwAccessRO),
1118 .RESVAL (1'h1),
1119 .Mubi (1'b0)
1120 ) u_clk_hints_status_clk_main_aes_val (
1121 .clk_i (clk_i),
1122 .rst_ni (rst_ni),
1123
1124 // from register interface
1125 .we (1'b0),
1126 .wd ('0),
1127
1128 // from internal hardware
1129 .de (hw2reg.clk_hints_status.clk_main_aes_val.de),
1130 .d (hw2reg.clk_hints_status.clk_main_aes_val.d),
1131
1132 // to internal hardware
1133 .qe (),
1134 .q (),
1135 .ds (),
1136
1137 // to register interface (read)
1138 .qs (clk_hints_status_clk_main_aes_val_qs)
1139 );
1140
1141 // F[clk_main_hmac_val]: 1:1
1142 prim_subreg #(
1143 .DW (1),
1144 .SwAccess(prim_subreg_pkg::SwAccessRO),
1145 .RESVAL (1'h1),
1146 .Mubi (1'b0)
1147 ) u_clk_hints_status_clk_main_hmac_val (
1148 .clk_i (clk_i),
1149 .rst_ni (rst_ni),
1150
1151 // from register interface
1152 .we (1'b0),
1153 .wd ('0),
1154
1155 // from internal hardware
1156 .de (hw2reg.clk_hints_status.clk_main_hmac_val.de),
1157 .d (hw2reg.clk_hints_status.clk_main_hmac_val.d),
1158
1159 // to internal hardware
1160 .qe (),
1161 .q (),
1162 .ds (),
1163
1164 // to register interface (read)
1165 .qs (clk_hints_status_clk_main_hmac_val_qs)
1166 );
1167
1168 // F[clk_main_kmac_val]: 2:2
1169 prim_subreg #(
1170 .DW (1),
1171 .SwAccess(prim_subreg_pkg::SwAccessRO),
1172 .RESVAL (1'h1),
1173 .Mubi (1'b0)
1174 ) u_clk_hints_status_clk_main_kmac_val (
1175 .clk_i (clk_i),
1176 .rst_ni (rst_ni),
1177
1178 // from register interface
1179 .we (1'b0),
1180 .wd ('0),
1181
1182 // from internal hardware
1183 .de (hw2reg.clk_hints_status.clk_main_kmac_val.de),
1184 .d (hw2reg.clk_hints_status.clk_main_kmac_val.d),
1185
1186 // to internal hardware
1187 .qe (),
1188 .q (),
1189 .ds (),
1190
1191 // to register interface (read)
1192 .qs (clk_hints_status_clk_main_kmac_val_qs)
1193 );
1194
1195 // F[clk_main_otbn_val]: 3:3
1196 prim_subreg #(
1197 .DW (1),
1198 .SwAccess(prim_subreg_pkg::SwAccessRO),
1199 .RESVAL (1'h1),
1200 .Mubi (1'b0)
1201 ) u_clk_hints_status_clk_main_otbn_val (
1202 .clk_i (clk_i),
1203 .rst_ni (rst_ni),
1204
1205 // from register interface
1206 .we (1'b0),
1207 .wd ('0),
1208
1209 // from internal hardware
1210 .de (hw2reg.clk_hints_status.clk_main_otbn_val.de),
1211 .d (hw2reg.clk_hints_status.clk_main_otbn_val.d),
1212
1213 // to internal hardware
1214 .qe (),
1215 .q (),
1216 .ds (),
1217
1218 // to register interface (read)
1219 .qs (clk_hints_status_clk_main_otbn_val_qs)
1220 );
1221
1222
1223 // R[measure_ctrl_regwen]: V(False)
1224 prim_subreg #(
1225 .DW (1),
1226 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1227 .RESVAL (1'h1),
1228 .Mubi (1'b0)
1229 ) u_measure_ctrl_regwen (
1230 .clk_i (clk_i),
1231 .rst_ni (rst_ni),
1232
1233 // from register interface
1234 .we (measure_ctrl_regwen_we),
1235 .wd (measure_ctrl_regwen_wd),
1236
1237 // from internal hardware
1238 .de (hw2reg.measure_ctrl_regwen.de),
1239 .d (hw2reg.measure_ctrl_regwen.d),
1240
1241 // to internal hardware
1242 .qe (),
1243 .q (reg2hw.measure_ctrl_regwen.q),
1244 .ds (),
1245
1246 // to register interface (read)
1247 .qs (measure_ctrl_regwen_qs)
1248 );
1249
1250
1251 // R[io_meas_ctrl_en]: V(False)
1252 logic [0:0] io_meas_ctrl_en_flds_we;
1253 1/1 assign io_io_meas_ctrl_en_qe = |io_meas_ctrl_en_flds_we;
Tests: T1 T2 T3
1254 // Create REGWEN-gated WE signal
1255 logic io_io_meas_ctrl_en_gated_we;
1256 1/1 assign io_io_meas_ctrl_en_gated_we = io_io_meas_ctrl_en_we & io_io_meas_ctrl_en_regwen;
Tests: T1 T2 T3
1257 prim_subreg #(
1258 .DW (4),
1259 .SwAccess(prim_subreg_pkg::SwAccessRW),
1260 .RESVAL (4'h9),
1261 .Mubi (1'b1)
1262 ) u_io_meas_ctrl_en (
1263 .clk_i (clk_io_i),
1264 .rst_ni (rst_io_ni),
1265
1266 // from register interface
1267 .we (io_io_meas_ctrl_en_gated_we),
1268 .wd (io_io_meas_ctrl_en_wdata[3:0]),
1269
1270 // from internal hardware
1271 .de (hw2reg.io_meas_ctrl_en.de),
1272 .d (hw2reg.io_meas_ctrl_en.d),
1273
1274 // to internal hardware
1275 .qe (io_meas_ctrl_en_flds_we[0]),
1276 .q (reg2hw.io_meas_ctrl_en.q),
1277 .ds (io_io_meas_ctrl_en_ds_int),
1278
1279 // to register interface (read)
1280 .qs (io_io_meas_ctrl_en_qs_int)
1281 );
1282
1283
1284 // R[io_meas_ctrl_shadowed]: V(False)
1285 // Create REGWEN-gated WE signal
1286 logic io_io_meas_ctrl_shadowed_gated_we;
1287 1/1 assign io_io_meas_ctrl_shadowed_gated_we =
Tests: T1 T2 T3
1288 io_io_meas_ctrl_shadowed_we & io_io_meas_ctrl_shadowed_regwen;
1289 // F[hi]: 9:0
1290 logic async_io_meas_ctrl_shadowed_hi_err_update;
1291 logic async_io_meas_ctrl_shadowed_hi_err_storage;
1292
1293 // storage error is persistent and can be sampled at any time
1294 prim_flop_2sync #(
1295 .Width(1),
1296 .ResetValue('0)
1297 ) u_io_meas_ctrl_shadowed_hi_err_storage_sync (
1298 .clk_i,
1299 .rst_ni,
1300 .d_i(async_io_meas_ctrl_shadowed_hi_err_storage),
1301 .q_o(io_meas_ctrl_shadowed_hi_storage_err)
1302 );
1303
1304 // update error is transient and must be immediately captured
1305 prim_pulse_sync u_io_meas_ctrl_shadowed_hi_err_update_sync (
1306 .clk_src_i(clk_io_i),
1307 .rst_src_ni(rst_io_ni),
1308 .src_pulse_i(async_io_meas_ctrl_shadowed_hi_err_update),
1309 .clk_dst_i(clk_i),
1310 .rst_dst_ni(rst_ni),
1311 .dst_pulse_o(io_meas_ctrl_shadowed_hi_update_err)
1312 );
1313 prim_subreg_shadow #(
1314 .DW (10),
1315 .SwAccess(prim_subreg_pkg::SwAccessRW),
1316 .RESVAL (10'h1ea),
1317 .Mubi (1'b0)
1318 ) u_io_meas_ctrl_shadowed_hi (
1319 .clk_i (clk_io_i),
1320 .rst_ni (rst_io_ni),
1321 .rst_shadowed_ni (rst_shadowed_ni),
1322
1323 // from register interface
1324 .re (io_io_meas_ctrl_shadowed_re),
1325 .we (io_io_meas_ctrl_shadowed_gated_we),
1326 .wd (io_io_meas_ctrl_shadowed_wdata[9:0]),
1327
1328 // from internal hardware
1329 .de (1'b0),
1330 .d ('0),
1331
1332 // to internal hardware
1333 .qe (),
1334 .q (reg2hw.io_meas_ctrl_shadowed.hi.q),
1335 .ds (),
1336
1337 // to register interface (read)
1338 .qs (io_io_meas_ctrl_shadowed_hi_qs_int),
1339
1340 // Shadow register phase. Relevant for hwext only.
1341 .phase (),
1342
1343 // Shadow register error conditions
1344 .err_update (async_io_meas_ctrl_shadowed_hi_err_update),
1345 .err_storage (async_io_meas_ctrl_shadowed_hi_err_storage)
1346 );
1347
1348 // F[lo]: 19:10
1349 logic async_io_meas_ctrl_shadowed_lo_err_update;
1350 logic async_io_meas_ctrl_shadowed_lo_err_storage;
1351
1352 // storage error is persistent and can be sampled at any time
1353 prim_flop_2sync #(
1354 .Width(1),
1355 .ResetValue('0)
1356 ) u_io_meas_ctrl_shadowed_lo_err_storage_sync (
1357 .clk_i,
1358 .rst_ni,
1359 .d_i(async_io_meas_ctrl_shadowed_lo_err_storage),
1360 .q_o(io_meas_ctrl_shadowed_lo_storage_err)
1361 );
1362
1363 // update error is transient and must be immediately captured
1364 prim_pulse_sync u_io_meas_ctrl_shadowed_lo_err_update_sync (
1365 .clk_src_i(clk_io_i),
1366 .rst_src_ni(rst_io_ni),
1367 .src_pulse_i(async_io_meas_ctrl_shadowed_lo_err_update),
1368 .clk_dst_i(clk_i),
1369 .rst_dst_ni(rst_ni),
1370 .dst_pulse_o(io_meas_ctrl_shadowed_lo_update_err)
1371 );
1372 prim_subreg_shadow #(
1373 .DW (10),
1374 .SwAccess(prim_subreg_pkg::SwAccessRW),
1375 .RESVAL (10'h1d6),
1376 .Mubi (1'b0)
1377 ) u_io_meas_ctrl_shadowed_lo (
1378 .clk_i (clk_io_i),
1379 .rst_ni (rst_io_ni),
1380 .rst_shadowed_ni (rst_shadowed_ni),
1381
1382 // from register interface
1383 .re (io_io_meas_ctrl_shadowed_re),
1384 .we (io_io_meas_ctrl_shadowed_gated_we),
1385 .wd (io_io_meas_ctrl_shadowed_wdata[19:10]),
1386
1387 // from internal hardware
1388 .de (1'b0),
1389 .d ('0),
1390
1391 // to internal hardware
1392 .qe (),
1393 .q (reg2hw.io_meas_ctrl_shadowed.lo.q),
1394 .ds (),
1395
1396 // to register interface (read)
1397 .qs (io_io_meas_ctrl_shadowed_lo_qs_int),
1398
1399 // Shadow register phase. Relevant for hwext only.
1400 .phase (),
1401
1402 // Shadow register error conditions
1403 .err_update (async_io_meas_ctrl_shadowed_lo_err_update),
1404 .err_storage (async_io_meas_ctrl_shadowed_lo_err_storage)
1405 );
1406
1407
1408 // R[io_div2_meas_ctrl_en]: V(False)
1409 logic [0:0] io_div2_meas_ctrl_en_flds_we;
1410 1/1 assign io_div2_io_div2_meas_ctrl_en_qe = |io_div2_meas_ctrl_en_flds_we;
Tests: T1 T2 T3
1411 // Create REGWEN-gated WE signal
1412 logic io_div2_io_div2_meas_ctrl_en_gated_we;
1413 1/1 assign io_div2_io_div2_meas_ctrl_en_gated_we =
Tests: T1 T2 T3
1414 io_div2_io_div2_meas_ctrl_en_we & io_div2_io_div2_meas_ctrl_en_regwen;
1415 prim_subreg #(
1416 .DW (4),
1417 .SwAccess(prim_subreg_pkg::SwAccessRW),
1418 .RESVAL (4'h9),
1419 .Mubi (1'b1)
1420 ) u_io_div2_meas_ctrl_en (
1421 .clk_i (clk_io_div2_i),
1422 .rst_ni (rst_io_div2_ni),
1423
1424 // from register interface
1425 .we (io_div2_io_div2_meas_ctrl_en_gated_we),
1426 .wd (io_div2_io_div2_meas_ctrl_en_wdata[3:0]),
1427
1428 // from internal hardware
1429 .de (hw2reg.io_div2_meas_ctrl_en.de),
1430 .d (hw2reg.io_div2_meas_ctrl_en.d),
1431
1432 // to internal hardware
1433 .qe (io_div2_meas_ctrl_en_flds_we[0]),
1434 .q (reg2hw.io_div2_meas_ctrl_en.q),
1435 .ds (io_div2_io_div2_meas_ctrl_en_ds_int),
1436
1437 // to register interface (read)
1438 .qs (io_div2_io_div2_meas_ctrl_en_qs_int)
1439 );
1440
1441
1442 // R[io_div2_meas_ctrl_shadowed]: V(False)
1443 // Create REGWEN-gated WE signal
1444 logic io_div2_io_div2_meas_ctrl_shadowed_gated_we;
1445 1/1 assign io_div2_io_div2_meas_ctrl_shadowed_gated_we =
Tests: T1 T2 T3
1446 io_div2_io_div2_meas_ctrl_shadowed_we & io_div2_io_div2_meas_ctrl_shadowed_regwen;
1447 // F[hi]: 8:0
1448 logic async_io_div2_meas_ctrl_shadowed_hi_err_update;
1449 logic async_io_div2_meas_ctrl_shadowed_hi_err_storage;
1450
1451 // storage error is persistent and can be sampled at any time
1452 prim_flop_2sync #(
1453 .Width(1),
1454 .ResetValue('0)
1455 ) u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync (
1456 .clk_i,
1457 .rst_ni,
1458 .d_i(async_io_div2_meas_ctrl_shadowed_hi_err_storage),
1459 .q_o(io_div2_meas_ctrl_shadowed_hi_storage_err)
1460 );
1461
1462 // update error is transient and must be immediately captured
1463 prim_pulse_sync u_io_div2_meas_ctrl_shadowed_hi_err_update_sync (
1464 .clk_src_i(clk_io_div2_i),
1465 .rst_src_ni(rst_io_div2_ni),
1466 .src_pulse_i(async_io_div2_meas_ctrl_shadowed_hi_err_update),
1467 .clk_dst_i(clk_i),
1468 .rst_dst_ni(rst_ni),
1469 .dst_pulse_o(io_div2_meas_ctrl_shadowed_hi_update_err)
1470 );
1471 prim_subreg_shadow #(
1472 .DW (9),
1473 .SwAccess(prim_subreg_pkg::SwAccessRW),
1474 .RESVAL (9'hfa),
1475 .Mubi (1'b0)
1476 ) u_io_div2_meas_ctrl_shadowed_hi (
1477 .clk_i (clk_io_div2_i),
1478 .rst_ni (rst_io_div2_ni),
1479 .rst_shadowed_ni (rst_shadowed_ni),
1480
1481 // from register interface
1482 .re (io_div2_io_div2_meas_ctrl_shadowed_re),
1483 .we (io_div2_io_div2_meas_ctrl_shadowed_gated_we),
1484 .wd (io_div2_io_div2_meas_ctrl_shadowed_wdata[8:0]),
1485
1486 // from internal hardware
1487 .de (1'b0),
1488 .d ('0),
1489
1490 // to internal hardware
1491 .qe (),
1492 .q (reg2hw.io_div2_meas_ctrl_shadowed.hi.q),
1493 .ds (),
1494
1495 // to register interface (read)
1496 .qs (io_div2_io_div2_meas_ctrl_shadowed_hi_qs_int),
1497
1498 // Shadow register phase. Relevant for hwext only.
1499 .phase (),
1500
1501 // Shadow register error conditions
1502 .err_update (async_io_div2_meas_ctrl_shadowed_hi_err_update),
1503 .err_storage (async_io_div2_meas_ctrl_shadowed_hi_err_storage)
1504 );
1505
1506 // F[lo]: 17:9
1507 logic async_io_div2_meas_ctrl_shadowed_lo_err_update;
1508 logic async_io_div2_meas_ctrl_shadowed_lo_err_storage;
1509
1510 // storage error is persistent and can be sampled at any time
1511 prim_flop_2sync #(
1512 .Width(1),
1513 .ResetValue('0)
1514 ) u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync (
1515 .clk_i,
1516 .rst_ni,
1517 .d_i(async_io_div2_meas_ctrl_shadowed_lo_err_storage),
1518 .q_o(io_div2_meas_ctrl_shadowed_lo_storage_err)
1519 );
1520
1521 // update error is transient and must be immediately captured
1522 prim_pulse_sync u_io_div2_meas_ctrl_shadowed_lo_err_update_sync (
1523 .clk_src_i(clk_io_div2_i),
1524 .rst_src_ni(rst_io_div2_ni),
1525 .src_pulse_i(async_io_div2_meas_ctrl_shadowed_lo_err_update),
1526 .clk_dst_i(clk_i),
1527 .rst_dst_ni(rst_ni),
1528 .dst_pulse_o(io_div2_meas_ctrl_shadowed_lo_update_err)
1529 );
1530 prim_subreg_shadow #(
1531 .DW (9),
1532 .SwAccess(prim_subreg_pkg::SwAccessRW),
1533 .RESVAL (9'he6),
1534 .Mubi (1'b0)
1535 ) u_io_div2_meas_ctrl_shadowed_lo (
1536 .clk_i (clk_io_div2_i),
1537 .rst_ni (rst_io_div2_ni),
1538 .rst_shadowed_ni (rst_shadowed_ni),
1539
1540 // from register interface
1541 .re (io_div2_io_div2_meas_ctrl_shadowed_re),
1542 .we (io_div2_io_div2_meas_ctrl_shadowed_gated_we),
1543 .wd (io_div2_io_div2_meas_ctrl_shadowed_wdata[17:9]),
1544
1545 // from internal hardware
1546 .de (1'b0),
1547 .d ('0),
1548
1549 // to internal hardware
1550 .qe (),
1551 .q (reg2hw.io_div2_meas_ctrl_shadowed.lo.q),
1552 .ds (),
1553
1554 // to register interface (read)
1555 .qs (io_div2_io_div2_meas_ctrl_shadowed_lo_qs_int),
1556
1557 // Shadow register phase. Relevant for hwext only.
1558 .phase (),
1559
1560 // Shadow register error conditions
1561 .err_update (async_io_div2_meas_ctrl_shadowed_lo_err_update),
1562 .err_storage (async_io_div2_meas_ctrl_shadowed_lo_err_storage)
1563 );
1564
1565
1566 // R[io_div4_meas_ctrl_en]: V(False)
1567 logic [0:0] io_div4_meas_ctrl_en_flds_we;
1568 1/1 assign io_div4_io_div4_meas_ctrl_en_qe = |io_div4_meas_ctrl_en_flds_we;
Tests: T1 T2 T3
1569 // Create REGWEN-gated WE signal
1570 logic io_div4_io_div4_meas_ctrl_en_gated_we;
1571 1/1 assign io_div4_io_div4_meas_ctrl_en_gated_we =
Tests: T1 T2 T3
1572 io_div4_io_div4_meas_ctrl_en_we & io_div4_io_div4_meas_ctrl_en_regwen;
1573 prim_subreg #(
1574 .DW (4),
1575 .SwAccess(prim_subreg_pkg::SwAccessRW),
1576 .RESVAL (4'h9),
1577 .Mubi (1'b1)
1578 ) u_io_div4_meas_ctrl_en (
1579 .clk_i (clk_io_div4_i),
1580 .rst_ni (rst_io_div4_ni),
1581
1582 // from register interface
1583 .we (io_div4_io_div4_meas_ctrl_en_gated_we),
1584 .wd (io_div4_io_div4_meas_ctrl_en_wdata[3:0]),
1585
1586 // from internal hardware
1587 .de (hw2reg.io_div4_meas_ctrl_en.de),
1588 .d (hw2reg.io_div4_meas_ctrl_en.d),
1589
1590 // to internal hardware
1591 .qe (io_div4_meas_ctrl_en_flds_we[0]),
1592 .q (reg2hw.io_div4_meas_ctrl_en.q),
1593 .ds (io_div4_io_div4_meas_ctrl_en_ds_int),
1594
1595 // to register interface (read)
1596 .qs (io_div4_io_div4_meas_ctrl_en_qs_int)
1597 );
1598
1599
1600 // R[io_div4_meas_ctrl_shadowed]: V(False)
1601 // Create REGWEN-gated WE signal
1602 logic io_div4_io_div4_meas_ctrl_shadowed_gated_we;
1603 1/1 assign io_div4_io_div4_meas_ctrl_shadowed_gated_we =
Tests: T1 T2 T3
1604 io_div4_io_div4_meas_ctrl_shadowed_we & io_div4_io_div4_meas_ctrl_shadowed_regwen;
1605 // F[hi]: 7:0
1606 logic async_io_div4_meas_ctrl_shadowed_hi_err_update;
1607 logic async_io_div4_meas_ctrl_shadowed_hi_err_storage;
1608
1609 // storage error is persistent and can be sampled at any time
1610 prim_flop_2sync #(
1611 .Width(1),
1612 .ResetValue('0)
1613 ) u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync (
1614 .clk_i,
1615 .rst_ni,
1616 .d_i(async_io_div4_meas_ctrl_shadowed_hi_err_storage),
1617 .q_o(io_div4_meas_ctrl_shadowed_hi_storage_err)
1618 );
1619
1620 // update error is transient and must be immediately captured
1621 prim_pulse_sync u_io_div4_meas_ctrl_shadowed_hi_err_update_sync (
1622 .clk_src_i(clk_io_div4_i),
1623 .rst_src_ni(rst_io_div4_ni),
1624 .src_pulse_i(async_io_div4_meas_ctrl_shadowed_hi_err_update),
1625 .clk_dst_i(clk_i),
1626 .rst_dst_ni(rst_ni),
1627 .dst_pulse_o(io_div4_meas_ctrl_shadowed_hi_update_err)
1628 );
1629 prim_subreg_shadow #(
1630 .DW (8),
1631 .SwAccess(prim_subreg_pkg::SwAccessRW),
1632 .RESVAL (8'h82),
1633 .Mubi (1'b0)
1634 ) u_io_div4_meas_ctrl_shadowed_hi (
1635 .clk_i (clk_io_div4_i),
1636 .rst_ni (rst_io_div4_ni),
1637 .rst_shadowed_ni (rst_shadowed_ni),
1638
1639 // from register interface
1640 .re (io_div4_io_div4_meas_ctrl_shadowed_re),
1641 .we (io_div4_io_div4_meas_ctrl_shadowed_gated_we),
1642 .wd (io_div4_io_div4_meas_ctrl_shadowed_wdata[7:0]),
1643
1644 // from internal hardware
1645 .de (1'b0),
1646 .d ('0),
1647
1648 // to internal hardware
1649 .qe (),
1650 .q (reg2hw.io_div4_meas_ctrl_shadowed.hi.q),
1651 .ds (),
1652
1653 // to register interface (read)
1654 .qs (io_div4_io_div4_meas_ctrl_shadowed_hi_qs_int),
1655
1656 // Shadow register phase. Relevant for hwext only.
1657 .phase (),
1658
1659 // Shadow register error conditions
1660 .err_update (async_io_div4_meas_ctrl_shadowed_hi_err_update),
1661 .err_storage (async_io_div4_meas_ctrl_shadowed_hi_err_storage)
1662 );
1663
1664 // F[lo]: 15:8
1665 logic async_io_div4_meas_ctrl_shadowed_lo_err_update;
1666 logic async_io_div4_meas_ctrl_shadowed_lo_err_storage;
1667
1668 // storage error is persistent and can be sampled at any time
1669 prim_flop_2sync #(
1670 .Width(1),
1671 .ResetValue('0)
1672 ) u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync (
1673 .clk_i,
1674 .rst_ni,
1675 .d_i(async_io_div4_meas_ctrl_shadowed_lo_err_storage),
1676 .q_o(io_div4_meas_ctrl_shadowed_lo_storage_err)
1677 );
1678
1679 // update error is transient and must be immediately captured
1680 prim_pulse_sync u_io_div4_meas_ctrl_shadowed_lo_err_update_sync (
1681 .clk_src_i(clk_io_div4_i),
1682 .rst_src_ni(rst_io_div4_ni),
1683 .src_pulse_i(async_io_div4_meas_ctrl_shadowed_lo_err_update),
1684 .clk_dst_i(clk_i),
1685 .rst_dst_ni(rst_ni),
1686 .dst_pulse_o(io_div4_meas_ctrl_shadowed_lo_update_err)
1687 );
1688 prim_subreg_shadow #(
1689 .DW (8),
1690 .SwAccess(prim_subreg_pkg::SwAccessRW),
1691 .RESVAL (8'h6e),
1692 .Mubi (1'b0)
1693 ) u_io_div4_meas_ctrl_shadowed_lo (
1694 .clk_i (clk_io_div4_i),
1695 .rst_ni (rst_io_div4_ni),
1696 .rst_shadowed_ni (rst_shadowed_ni),
1697
1698 // from register interface
1699 .re (io_div4_io_div4_meas_ctrl_shadowed_re),
1700 .we (io_div4_io_div4_meas_ctrl_shadowed_gated_we),
1701 .wd (io_div4_io_div4_meas_ctrl_shadowed_wdata[15:8]),
1702
1703 // from internal hardware
1704 .de (1'b0),
1705 .d ('0),
1706
1707 // to internal hardware
1708 .qe (),
1709 .q (reg2hw.io_div4_meas_ctrl_shadowed.lo.q),
1710 .ds (),
1711
1712 // to register interface (read)
1713 .qs (io_div4_io_div4_meas_ctrl_shadowed_lo_qs_int),
1714
1715 // Shadow register phase. Relevant for hwext only.
1716 .phase (),
1717
1718 // Shadow register error conditions
1719 .err_update (async_io_div4_meas_ctrl_shadowed_lo_err_update),
1720 .err_storage (async_io_div4_meas_ctrl_shadowed_lo_err_storage)
1721 );
1722
1723
1724 // R[main_meas_ctrl_en]: V(False)
1725 logic [0:0] main_meas_ctrl_en_flds_we;
1726 1/1 assign main_main_meas_ctrl_en_qe = |main_meas_ctrl_en_flds_we;
Tests: T1 T2 T3
1727 // Create REGWEN-gated WE signal
1728 logic main_main_meas_ctrl_en_gated_we;
1729 1/1 assign main_main_meas_ctrl_en_gated_we =
Tests: T1 T2 T3
1730 main_main_meas_ctrl_en_we & main_main_meas_ctrl_en_regwen;
1731 prim_subreg #(
1732 .DW (4),
1733 .SwAccess(prim_subreg_pkg::SwAccessRW),
1734 .RESVAL (4'h9),
1735 .Mubi (1'b1)
1736 ) u_main_meas_ctrl_en (
1737 .clk_i (clk_main_i),
1738 .rst_ni (rst_main_ni),
1739
1740 // from register interface
1741 .we (main_main_meas_ctrl_en_gated_we),
1742 .wd (main_main_meas_ctrl_en_wdata[3:0]),
1743
1744 // from internal hardware
1745 .de (hw2reg.main_meas_ctrl_en.de),
1746 .d (hw2reg.main_meas_ctrl_en.d),
1747
1748 // to internal hardware
1749 .qe (main_meas_ctrl_en_flds_we[0]),
1750 .q (reg2hw.main_meas_ctrl_en.q),
1751 .ds (main_main_meas_ctrl_en_ds_int),
1752
1753 // to register interface (read)
1754 .qs (main_main_meas_ctrl_en_qs_int)
1755 );
1756
1757
1758 // R[main_meas_ctrl_shadowed]: V(False)
1759 // Create REGWEN-gated WE signal
1760 logic main_main_meas_ctrl_shadowed_gated_we;
1761 1/1 assign main_main_meas_ctrl_shadowed_gated_we =
Tests: T1 T2 T3
1762 main_main_meas_ctrl_shadowed_we & main_main_meas_ctrl_shadowed_regwen;
1763 // F[hi]: 9:0
1764 logic async_main_meas_ctrl_shadowed_hi_err_update;
1765 logic async_main_meas_ctrl_shadowed_hi_err_storage;
1766 logic deglitched_main_meas_ctrl_shadowed_hi_err_storage;
1767
1768 // flop storage error to filter combinational glitches before sending it across CDC
1769 prim_flop #(
1770 .Width(1),
1771 .ResetValue('0)
1772 ) u_main_meas_ctrl_shadowed_hi_err_storage_deglitch (
1773 .clk_i (clk_main_i),
1774 .rst_ni(rst_main_ni),
1775 .d_i (async_main_meas_ctrl_shadowed_hi_err_storage),
1776 .q_o (deglitched_main_meas_ctrl_shadowed_hi_err_storage)
1777 );
1778
1779 // storage error is persistent and can be sampled at any time
1780 prim_flop_2sync #(
1781 .Width(1),
1782 .ResetValue('0)
1783 ) u_main_meas_ctrl_shadowed_hi_err_storage_sync (
1784 .clk_i,
1785 .rst_ni,
1786 .d_i(deglitched_main_meas_ctrl_shadowed_hi_err_storage),
1787 .q_o(main_meas_ctrl_shadowed_hi_storage_err)
1788 );
1789
1790 // update error is transient and must be immediately captured
1791 prim_pulse_sync u_main_meas_ctrl_shadowed_hi_err_update_sync (
1792 .clk_src_i(clk_main_i),
1793 .rst_src_ni(rst_main_ni),
1794 .src_pulse_i(async_main_meas_ctrl_shadowed_hi_err_update),
1795 .clk_dst_i(clk_i),
1796 .rst_dst_ni(rst_ni),
1797 .dst_pulse_o(main_meas_ctrl_shadowed_hi_update_err)
1798 );
1799 prim_subreg_shadow #(
1800 .DW (10),
1801 .SwAccess(prim_subreg_pkg::SwAccessRW),
1802 .RESVAL (10'h1fe),
1803 .Mubi (1'b0)
1804 ) u_main_meas_ctrl_shadowed_hi (
1805 .clk_i (clk_main_i),
1806 .rst_ni (rst_main_ni),
1807 .rst_shadowed_ni (rst_shadowed_ni),
1808
1809 // from register interface
1810 .re (main_main_meas_ctrl_shadowed_re),
1811 .we (main_main_meas_ctrl_shadowed_gated_we),
1812 .wd (main_main_meas_ctrl_shadowed_wdata[9:0]),
1813
1814 // from internal hardware
1815 .de (1'b0),
1816 .d ('0),
1817
1818 // to internal hardware
1819 .qe (),
1820 .q (reg2hw.main_meas_ctrl_shadowed.hi.q),
1821 .ds (),
1822
1823 // to register interface (read)
1824 .qs (main_main_meas_ctrl_shadowed_hi_qs_int),
1825
1826 // Shadow register phase. Relevant for hwext only.
1827 .phase (),
1828
1829 // Shadow register error conditions
1830 .err_update (async_main_meas_ctrl_shadowed_hi_err_update),
1831 .err_storage (async_main_meas_ctrl_shadowed_hi_err_storage)
1832 );
1833
1834 // F[lo]: 19:10
1835 logic async_main_meas_ctrl_shadowed_lo_err_update;
1836 logic async_main_meas_ctrl_shadowed_lo_err_storage;
1837 logic deglitched_main_meas_ctrl_shadowed_lo_err_storage;
1838
1839 // flop storage error to filter combinational glitches before sending it across CDC
1840 prim_flop #(
1841 .Width(1),
1842 .ResetValue('0)
1843 ) u_main_meas_ctrl_shadowed_lo_err_storage_deglitch (
1844 .clk_i (clk_main_i),
1845 .rst_ni(rst_main_ni),
1846 .d_i (async_main_meas_ctrl_shadowed_lo_err_storage),
1847 .q_o (deglitched_main_meas_ctrl_shadowed_lo_err_storage)
1848 );
1849
1850 // storage error is persistent and can be sampled at any time
1851 prim_flop_2sync #(
1852 .Width(1),
1853 .ResetValue('0)
1854 ) u_main_meas_ctrl_shadowed_lo_err_storage_sync (
1855 .clk_i,
1856 .rst_ni,
1857 .d_i(deglitched_main_meas_ctrl_shadowed_lo_err_storage),
1858 .q_o(main_meas_ctrl_shadowed_lo_storage_err)
1859 );
1860
1861 // update error is transient and must be immediately captured
1862 prim_pulse_sync u_main_meas_ctrl_shadowed_lo_err_update_sync (
1863 .clk_src_i(clk_main_i),
1864 .rst_src_ni(rst_main_ni),
1865 .src_pulse_i(async_main_meas_ctrl_shadowed_lo_err_update),
1866 .clk_dst_i(clk_i),
1867 .rst_dst_ni(rst_ni),
1868 .dst_pulse_o(main_meas_ctrl_shadowed_lo_update_err)
1869 );
1870 prim_subreg_shadow #(
1871 .DW (10),
1872 .SwAccess(prim_subreg_pkg::SwAccessRW),
1873 .RESVAL (10'h1ea),
1874 .Mubi (1'b0)
1875 ) u_main_meas_ctrl_shadowed_lo (
1876 .clk_i (clk_main_i),
1877 .rst_ni (rst_main_ni),
1878 .rst_shadowed_ni (rst_shadowed_ni),
1879
1880 // from register interface
1881 .re (main_main_meas_ctrl_shadowed_re),
1882 .we (main_main_meas_ctrl_shadowed_gated_we),
1883 .wd (main_main_meas_ctrl_shadowed_wdata[19:10]),
1884
1885 // from internal hardware
1886 .de (1'b0),
1887 .d ('0),
1888
1889 // to internal hardware
1890 .qe (),
1891 .q (reg2hw.main_meas_ctrl_shadowed.lo.q),
1892 .ds (),
1893
1894 // to register interface (read)
1895 .qs (main_main_meas_ctrl_shadowed_lo_qs_int),
1896
1897 // Shadow register phase. Relevant for hwext only.
1898 .phase (),
1899
1900 // Shadow register error conditions
1901 .err_update (async_main_meas_ctrl_shadowed_lo_err_update),
1902 .err_storage (async_main_meas_ctrl_shadowed_lo_err_storage)
1903 );
1904
1905
1906 // R[usb_meas_ctrl_en]: V(False)
1907 logic [0:0] usb_meas_ctrl_en_flds_we;
1908 1/1 assign usb_usb_meas_ctrl_en_qe = |usb_meas_ctrl_en_flds_we;
Tests: T1 T2 T3
1909 // Create REGWEN-gated WE signal
1910 logic usb_usb_meas_ctrl_en_gated_we;
1911 1/1 assign usb_usb_meas_ctrl_en_gated_we = usb_usb_meas_ctrl_en_we & usb_usb_meas_ctrl_en_regwen;
Tests: T1 T2 T3
1912 prim_subreg #(
1913 .DW (4),
1914 .SwAccess(prim_subreg_pkg::SwAccessRW),
1915 .RESVAL (4'h9),
1916 .Mubi (1'b1)
1917 ) u_usb_meas_ctrl_en (
1918 .clk_i (clk_usb_i),
1919 .rst_ni (rst_usb_ni),
1920
1921 // from register interface
1922 .we (usb_usb_meas_ctrl_en_gated_we),
1923 .wd (usb_usb_meas_ctrl_en_wdata[3:0]),
1924
1925 // from internal hardware
1926 .de (hw2reg.usb_meas_ctrl_en.de),
1927 .d (hw2reg.usb_meas_ctrl_en.d),
1928
1929 // to internal hardware
1930 .qe (usb_meas_ctrl_en_flds_we[0]),
1931 .q (reg2hw.usb_meas_ctrl_en.q),
1932 .ds (usb_usb_meas_ctrl_en_ds_int),
1933
1934 // to register interface (read)
1935 .qs (usb_usb_meas_ctrl_en_qs_int)
1936 );
1937
1938
1939 // R[usb_meas_ctrl_shadowed]: V(False)
1940 // Create REGWEN-gated WE signal
1941 logic usb_usb_meas_ctrl_shadowed_gated_we;
1942 1/1 assign usb_usb_meas_ctrl_shadowed_gated_we =
Tests: T1 T2 T3
1943 usb_usb_meas_ctrl_shadowed_we & usb_usb_meas_ctrl_shadowed_regwen;
1944 // F[hi]: 8:0
1945 logic async_usb_meas_ctrl_shadowed_hi_err_update;
1946 logic async_usb_meas_ctrl_shadowed_hi_err_storage;
1947
1948 // storage error is persistent and can be sampled at any time
1949 prim_flop_2sync #(
1950 .Width(1),
1951 .ResetValue('0)
1952 ) u_usb_meas_ctrl_shadowed_hi_err_storage_sync (
1953 .clk_i,
1954 .rst_ni,
1955 .d_i(async_usb_meas_ctrl_shadowed_hi_err_storage),
1956 .q_o(usb_meas_ctrl_shadowed_hi_storage_err)
1957 );
1958
1959 // update error is transient and must be immediately captured
1960 prim_pulse_sync u_usb_meas_ctrl_shadowed_hi_err_update_sync (
1961 .clk_src_i(clk_usb_i),
1962 .rst_src_ni(rst_usb_ni),
1963 .src_pulse_i(async_usb_meas_ctrl_shadowed_hi_err_update),
1964 .clk_dst_i(clk_i),
1965 .rst_dst_ni(rst_ni),
1966 .dst_pulse_o(usb_meas_ctrl_shadowed_hi_update_err)
1967 );
1968 prim_subreg_shadow #(
1969 .DW (9),
1970 .SwAccess(prim_subreg_pkg::SwAccessRW),
1971 .RESVAL (9'hfa),
1972 .Mubi (1'b0)
1973 ) u_usb_meas_ctrl_shadowed_hi (
1974 .clk_i (clk_usb_i),
1975 .rst_ni (rst_usb_ni),
1976 .rst_shadowed_ni (rst_shadowed_ni),
1977
1978 // from register interface
1979 .re (usb_usb_meas_ctrl_shadowed_re),
1980 .we (usb_usb_meas_ctrl_shadowed_gated_we),
1981 .wd (usb_usb_meas_ctrl_shadowed_wdata[8:0]),
1982
1983 // from internal hardware
1984 .de (1'b0),
1985 .d ('0),
1986
1987 // to internal hardware
1988 .qe (),
1989 .q (reg2hw.usb_meas_ctrl_shadowed.hi.q),
1990 .ds (),
1991
1992 // to register interface (read)
1993 .qs (usb_usb_meas_ctrl_shadowed_hi_qs_int),
1994
1995 // Shadow register phase. Relevant for hwext only.
1996 .phase (),
1997
1998 // Shadow register error conditions
1999 .err_update (async_usb_meas_ctrl_shadowed_hi_err_update),
2000 .err_storage (async_usb_meas_ctrl_shadowed_hi_err_storage)
2001 );
2002
2003 // F[lo]: 17:9
2004 logic async_usb_meas_ctrl_shadowed_lo_err_update;
2005 logic async_usb_meas_ctrl_shadowed_lo_err_storage;
2006
2007 // storage error is persistent and can be sampled at any time
2008 prim_flop_2sync #(
2009 .Width(1),
2010 .ResetValue('0)
2011 ) u_usb_meas_ctrl_shadowed_lo_err_storage_sync (
2012 .clk_i,
2013 .rst_ni,
2014 .d_i(async_usb_meas_ctrl_shadowed_lo_err_storage),
2015 .q_o(usb_meas_ctrl_shadowed_lo_storage_err)
2016 );
2017
2018 // update error is transient and must be immediately captured
2019 prim_pulse_sync u_usb_meas_ctrl_shadowed_lo_err_update_sync (
2020 .clk_src_i(clk_usb_i),
2021 .rst_src_ni(rst_usb_ni),
2022 .src_pulse_i(async_usb_meas_ctrl_shadowed_lo_err_update),
2023 .clk_dst_i(clk_i),
2024 .rst_dst_ni(rst_ni),
2025 .dst_pulse_o(usb_meas_ctrl_shadowed_lo_update_err)
2026 );
2027 prim_subreg_shadow #(
2028 .DW (9),
2029 .SwAccess(prim_subreg_pkg::SwAccessRW),
2030 .RESVAL (9'he6),
2031 .Mubi (1'b0)
2032 ) u_usb_meas_ctrl_shadowed_lo (
2033 .clk_i (clk_usb_i),
2034 .rst_ni (rst_usb_ni),
2035 .rst_shadowed_ni (rst_shadowed_ni),
2036
2037 // from register interface
2038 .re (usb_usb_meas_ctrl_shadowed_re),
2039 .we (usb_usb_meas_ctrl_shadowed_gated_we),
2040 .wd (usb_usb_meas_ctrl_shadowed_wdata[17:9]),
2041
2042 // from internal hardware
2043 .de (1'b0),
2044 .d ('0),
2045
2046 // to internal hardware
2047 .qe (),
2048 .q (reg2hw.usb_meas_ctrl_shadowed.lo.q),
2049 .ds (),
2050
2051 // to register interface (read)
2052 .qs (usb_usb_meas_ctrl_shadowed_lo_qs_int),
2053
2054 // Shadow register phase. Relevant for hwext only.
2055 .phase (),
2056
2057 // Shadow register error conditions
2058 .err_update (async_usb_meas_ctrl_shadowed_lo_err_update),
2059 .err_storage (async_usb_meas_ctrl_shadowed_lo_err_storage)
2060 );
2061
2062
2063 // R[recov_err_code]: V(False)
2064 // F[shadow_update_err]: 0:0
2065 prim_subreg #(
2066 .DW (1),
2067 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2068 .RESVAL (1'h0),
2069 .Mubi (1'b0)
2070 ) u_recov_err_code_shadow_update_err (
2071 .clk_i (clk_i),
2072 .rst_ni (rst_ni),
2073
2074 // from register interface
2075 .we (recov_err_code_we),
2076 .wd (recov_err_code_shadow_update_err_wd),
2077
2078 // from internal hardware
2079 .de (hw2reg.recov_err_code.shadow_update_err.de),
2080 .d (hw2reg.recov_err_code.shadow_update_err.d),
2081
2082 // to internal hardware
2083 .qe (),
2084 .q (),
2085 .ds (),
2086
2087 // to register interface (read)
2088 .qs (recov_err_code_shadow_update_err_qs)
2089 );
2090
2091 // F[io_measure_err]: 1:1
2092 prim_subreg #(
2093 .DW (1),
2094 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2095 .RESVAL (1'h0),
2096 .Mubi (1'b0)
2097 ) u_recov_err_code_io_measure_err (
2098 .clk_i (clk_i),
2099 .rst_ni (rst_ni),
2100
2101 // from register interface
2102 .we (recov_err_code_we),
2103 .wd (recov_err_code_io_measure_err_wd),
2104
2105 // from internal hardware
2106 .de (hw2reg.recov_err_code.io_measure_err.de),
2107 .d (hw2reg.recov_err_code.io_measure_err.d),
2108
2109 // to internal hardware
2110 .qe (),
2111 .q (),
2112 .ds (),
2113
2114 // to register interface (read)
2115 .qs (recov_err_code_io_measure_err_qs)
2116 );
2117
2118 // F[io_div2_measure_err]: 2:2
2119 prim_subreg #(
2120 .DW (1),
2121 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2122 .RESVAL (1'h0),
2123 .Mubi (1'b0)
2124 ) u_recov_err_code_io_div2_measure_err (
2125 .clk_i (clk_i),
2126 .rst_ni (rst_ni),
2127
2128 // from register interface
2129 .we (recov_err_code_we),
2130 .wd (recov_err_code_io_div2_measure_err_wd),
2131
2132 // from internal hardware
2133 .de (hw2reg.recov_err_code.io_div2_measure_err.de),
2134 .d (hw2reg.recov_err_code.io_div2_measure_err.d),
2135
2136 // to internal hardware
2137 .qe (),
2138 .q (),
2139 .ds (),
2140
2141 // to register interface (read)
2142 .qs (recov_err_code_io_div2_measure_err_qs)
2143 );
2144
2145 // F[io_div4_measure_err]: 3:3
2146 prim_subreg #(
2147 .DW (1),
2148 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2149 .RESVAL (1'h0),
2150 .Mubi (1'b0)
2151 ) u_recov_err_code_io_div4_measure_err (
2152 .clk_i (clk_i),
2153 .rst_ni (rst_ni),
2154
2155 // from register interface
2156 .we (recov_err_code_we),
2157 .wd (recov_err_code_io_div4_measure_err_wd),
2158
2159 // from internal hardware
2160 .de (hw2reg.recov_err_code.io_div4_measure_err.de),
2161 .d (hw2reg.recov_err_code.io_div4_measure_err.d),
2162
2163 // to internal hardware
2164 .qe (),
2165 .q (),
2166 .ds (),
2167
2168 // to register interface (read)
2169 .qs (recov_err_code_io_div4_measure_err_qs)
2170 );
2171
2172 // F[main_measure_err]: 4:4
2173 prim_subreg #(
2174 .DW (1),
2175 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2176 .RESVAL (1'h0),
2177 .Mubi (1'b0)
2178 ) u_recov_err_code_main_measure_err (
2179 .clk_i (clk_i),
2180 .rst_ni (rst_ni),
2181
2182 // from register interface
2183 .we (recov_err_code_we),
2184 .wd (recov_err_code_main_measure_err_wd),
2185
2186 // from internal hardware
2187 .de (hw2reg.recov_err_code.main_measure_err.de),
2188 .d (hw2reg.recov_err_code.main_measure_err.d),
2189
2190 // to internal hardware
2191 .qe (),
2192 .q (),
2193 .ds (),
2194
2195 // to register interface (read)
2196 .qs (recov_err_code_main_measure_err_qs)
2197 );
2198
2199 // F[usb_measure_err]: 5:5
2200 prim_subreg #(
2201 .DW (1),
2202 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2203 .RESVAL (1'h0),
2204 .Mubi (1'b0)
2205 ) u_recov_err_code_usb_measure_err (
2206 .clk_i (clk_i),
2207 .rst_ni (rst_ni),
2208
2209 // from register interface
2210 .we (recov_err_code_we),
2211 .wd (recov_err_code_usb_measure_err_wd),
2212
2213 // from internal hardware
2214 .de (hw2reg.recov_err_code.usb_measure_err.de),
2215 .d (hw2reg.recov_err_code.usb_measure_err.d),
2216
2217 // to internal hardware
2218 .qe (),
2219 .q (),
2220 .ds (),
2221
2222 // to register interface (read)
2223 .qs (recov_err_code_usb_measure_err_qs)
2224 );
2225
2226 // F[io_timeout_err]: 6:6
2227 prim_subreg #(
2228 .DW (1),
2229 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2230 .RESVAL (1'h0),
2231 .Mubi (1'b0)
2232 ) u_recov_err_code_io_timeout_err (
2233 .clk_i (clk_i),
2234 .rst_ni (rst_ni),
2235
2236 // from register interface
2237 .we (recov_err_code_we),
2238 .wd (recov_err_code_io_timeout_err_wd),
2239
2240 // from internal hardware
2241 .de (hw2reg.recov_err_code.io_timeout_err.de),
2242 .d (hw2reg.recov_err_code.io_timeout_err.d),
2243
2244 // to internal hardware
2245 .qe (),
2246 .q (),
2247 .ds (),
2248
2249 // to register interface (read)
2250 .qs (recov_err_code_io_timeout_err_qs)
2251 );
2252
2253 // F[io_div2_timeout_err]: 7:7
2254 prim_subreg #(
2255 .DW (1),
2256 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2257 .RESVAL (1'h0),
2258 .Mubi (1'b0)
2259 ) u_recov_err_code_io_div2_timeout_err (
2260 .clk_i (clk_i),
2261 .rst_ni (rst_ni),
2262
2263 // from register interface
2264 .we (recov_err_code_we),
2265 .wd (recov_err_code_io_div2_timeout_err_wd),
2266
2267 // from internal hardware
2268 .de (hw2reg.recov_err_code.io_div2_timeout_err.de),
2269 .d (hw2reg.recov_err_code.io_div2_timeout_err.d),
2270
2271 // to internal hardware
2272 .qe (),
2273 .q (),
2274 .ds (),
2275
2276 // to register interface (read)
2277 .qs (recov_err_code_io_div2_timeout_err_qs)
2278 );
2279
2280 // F[io_div4_timeout_err]: 8:8
2281 prim_subreg #(
2282 .DW (1),
2283 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2284 .RESVAL (1'h0),
2285 .Mubi (1'b0)
2286 ) u_recov_err_code_io_div4_timeout_err (
2287 .clk_i (clk_i),
2288 .rst_ni (rst_ni),
2289
2290 // from register interface
2291 .we (recov_err_code_we),
2292 .wd (recov_err_code_io_div4_timeout_err_wd),
2293
2294 // from internal hardware
2295 .de (hw2reg.recov_err_code.io_div4_timeout_err.de),
2296 .d (hw2reg.recov_err_code.io_div4_timeout_err.d),
2297
2298 // to internal hardware
2299 .qe (),
2300 .q (),
2301 .ds (),
2302
2303 // to register interface (read)
2304 .qs (recov_err_code_io_div4_timeout_err_qs)
2305 );
2306
2307 // F[main_timeout_err]: 9:9
2308 prim_subreg #(
2309 .DW (1),
2310 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2311 .RESVAL (1'h0),
2312 .Mubi (1'b0)
2313 ) u_recov_err_code_main_timeout_err (
2314 .clk_i (clk_i),
2315 .rst_ni (rst_ni),
2316
2317 // from register interface
2318 .we (recov_err_code_we),
2319 .wd (recov_err_code_main_timeout_err_wd),
2320
2321 // from internal hardware
2322 .de (hw2reg.recov_err_code.main_timeout_err.de),
2323 .d (hw2reg.recov_err_code.main_timeout_err.d),
2324
2325 // to internal hardware
2326 .qe (),
2327 .q (),
2328 .ds (),
2329
2330 // to register interface (read)
2331 .qs (recov_err_code_main_timeout_err_qs)
2332 );
2333
2334 // F[usb_timeout_err]: 10:10
2335 prim_subreg #(
2336 .DW (1),
2337 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2338 .RESVAL (1'h0),
2339 .Mubi (1'b0)
2340 ) u_recov_err_code_usb_timeout_err (
2341 .clk_i (clk_i),
2342 .rst_ni (rst_ni),
2343
2344 // from register interface
2345 .we (recov_err_code_we),
2346 .wd (recov_err_code_usb_timeout_err_wd),
2347
2348 // from internal hardware
2349 .de (hw2reg.recov_err_code.usb_timeout_err.de),
2350 .d (hw2reg.recov_err_code.usb_timeout_err.d),
2351
2352 // to internal hardware
2353 .qe (),
2354 .q (),
2355 .ds (),
2356
2357 // to register interface (read)
2358 .qs (recov_err_code_usb_timeout_err_qs)
2359 );
2360
2361
2362 // R[fatal_err_code]: V(False)
2363 // F[reg_intg]: 0:0
2364 prim_subreg #(
2365 .DW (1),
2366 .SwAccess(prim_subreg_pkg::SwAccessRO),
2367 .RESVAL (1'h0),
2368 .Mubi (1'b0)
2369 ) u_fatal_err_code_reg_intg (
2370 .clk_i (clk_i),
2371 .rst_ni (rst_ni),
2372
2373 // from register interface
2374 .we (1'b0),
2375 .wd ('0),
2376
2377 // from internal hardware
2378 .de (hw2reg.fatal_err_code.reg_intg.de),
2379 .d (hw2reg.fatal_err_code.reg_intg.d),
2380
2381 // to internal hardware
2382 .qe (),
2383 .q (reg2hw.fatal_err_code.reg_intg.q),
2384 .ds (),
2385
2386 // to register interface (read)
2387 .qs (fatal_err_code_reg_intg_qs)
2388 );
2389
2390 // F[idle_cnt]: 1:1
2391 prim_subreg #(
2392 .DW (1),
2393 .SwAccess(prim_subreg_pkg::SwAccessRO),
2394 .RESVAL (1'h0),
2395 .Mubi (1'b0)
2396 ) u_fatal_err_code_idle_cnt (
2397 .clk_i (clk_i),
2398 .rst_ni (rst_ni),
2399
2400 // from register interface
2401 .we (1'b0),
2402 .wd ('0),
2403
2404 // from internal hardware
2405 .de (hw2reg.fatal_err_code.idle_cnt.de),
2406 .d (hw2reg.fatal_err_code.idle_cnt.d),
2407
2408 // to internal hardware
2409 .qe (),
2410 .q (reg2hw.fatal_err_code.idle_cnt.q),
2411 .ds (),
2412
2413 // to register interface (read)
2414 .qs (fatal_err_code_idle_cnt_qs)
2415 );
2416
2417 // F[shadow_storage_err]: 2:2
2418 prim_subreg #(
2419 .DW (1),
2420 .SwAccess(prim_subreg_pkg::SwAccessRO),
2421 .RESVAL (1'h0),
2422 .Mubi (1'b0)
2423 ) u_fatal_err_code_shadow_storage_err (
2424 .clk_i (clk_i),
2425 .rst_ni (rst_ni),
2426
2427 // from register interface
2428 .we (1'b0),
2429 .wd ('0),
2430
2431 // from internal hardware
2432 .de (hw2reg.fatal_err_code.shadow_storage_err.de),
2433 .d (hw2reg.fatal_err_code.shadow_storage_err.d),
2434
2435 // to internal hardware
2436 .qe (),
2437 .q (reg2hw.fatal_err_code.shadow_storage_err.q),
2438 .ds (),
2439
2440 // to register interface (read)
2441 .qs (fatal_err_code_shadow_storage_err_qs)
2442 );
2443
2444
2445
2446 logic [21:0] addr_hit;
2447 always_comb begin
2448 1/1 addr_hit = '0;
Tests: T4 T5 T6
2449 1/1 addr_hit[ 0] = (reg_addr == CLKMGR_ALERT_TEST_OFFSET);
Tests: T4 T5 T6
2450 1/1 addr_hit[ 1] = (reg_addr == CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET);
Tests: T4 T5 T6
2451 1/1 addr_hit[ 2] = (reg_addr == CLKMGR_EXTCLK_CTRL_OFFSET);
Tests: T4 T5 T6
2452 1/1 addr_hit[ 3] = (reg_addr == CLKMGR_EXTCLK_STATUS_OFFSET);
Tests: T4 T5 T6
2453 1/1 addr_hit[ 4] = (reg_addr == CLKMGR_JITTER_REGWEN_OFFSET);
Tests: T4 T5 T6
2454 1/1 addr_hit[ 5] = (reg_addr == CLKMGR_JITTER_ENABLE_OFFSET);
Tests: T4 T5 T6
2455 1/1 addr_hit[ 6] = (reg_addr == CLKMGR_CLK_ENABLES_OFFSET);
Tests: T4 T5 T6
2456 1/1 addr_hit[ 7] = (reg_addr == CLKMGR_CLK_HINTS_OFFSET);
Tests: T4 T5 T6
2457 1/1 addr_hit[ 8] = (reg_addr == CLKMGR_CLK_HINTS_STATUS_OFFSET);
Tests: T4 T5 T6
2458 1/1 addr_hit[ 9] = (reg_addr == CLKMGR_MEASURE_CTRL_REGWEN_OFFSET);
Tests: T4 T5 T6
2459 1/1 addr_hit[10] = (reg_addr == CLKMGR_IO_MEAS_CTRL_EN_OFFSET);
Tests: T4 T5 T6
2460 1/1 addr_hit[11] = (reg_addr == CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET);
Tests: T4 T5 T6
2461 1/1 addr_hit[12] = (reg_addr == CLKMGR_IO_DIV2_MEAS_CTRL_EN_OFFSET);
Tests: T4 T5 T6
2462 1/1 addr_hit[13] = (reg_addr == CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET);
Tests: T4 T5 T6
2463 1/1 addr_hit[14] = (reg_addr == CLKMGR_IO_DIV4_MEAS_CTRL_EN_OFFSET);
Tests: T4 T5 T6
2464 1/1 addr_hit[15] = (reg_addr == CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET);
Tests: T4 T5 T6
2465 1/1 addr_hit[16] = (reg_addr == CLKMGR_MAIN_MEAS_CTRL_EN_OFFSET);
Tests: T4 T5 T6
2466 1/1 addr_hit[17] = (reg_addr == CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET);
Tests: T4 T5 T6
2467 1/1 addr_hit[18] = (reg_addr == CLKMGR_USB_MEAS_CTRL_EN_OFFSET);
Tests: T4 T5 T6
2468 1/1 addr_hit[19] = (reg_addr == CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET);
Tests: T4 T5 T6
2469 1/1 addr_hit[20] = (reg_addr == CLKMGR_RECOV_ERR_CODE_OFFSET);
Tests: T4 T5 T6
2470 1/1 addr_hit[21] = (reg_addr == CLKMGR_FATAL_ERR_CODE_OFFSET);
Tests: T4 T5 T6
2471 end
2472
2473 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T4 T5 T6
2474
2475 // Check sub-word write is permitted
2476 always_comb begin
2477 1/1 wr_err = (reg_we &
Tests: T4 T5 T6
2478 ((addr_hit[ 0] & (|(CLKMGR_PERMIT[ 0] & ~reg_be))) |
2479 (addr_hit[ 1] & (|(CLKMGR_PERMIT[ 1] & ~reg_be))) |
2480 (addr_hit[ 2] & (|(CLKMGR_PERMIT[ 2] & ~reg_be))) |
2481 (addr_hit[ 3] & (|(CLKMGR_PERMIT[ 3] & ~reg_be))) |
2482 (addr_hit[ 4] & (|(CLKMGR_PERMIT[ 4] & ~reg_be))) |
2483 (addr_hit[ 5] & (|(CLKMGR_PERMIT[ 5] & ~reg_be))) |
2484 (addr_hit[ 6] & (|(CLKMGR_PERMIT[ 6] & ~reg_be))) |
2485 (addr_hit[ 7] & (|(CLKMGR_PERMIT[ 7] & ~reg_be))) |
2486 (addr_hit[ 8] & (|(CLKMGR_PERMIT[ 8] & ~reg_be))) |
2487 (addr_hit[ 9] & (|(CLKMGR_PERMIT[ 9] & ~reg_be))) |
2488 (addr_hit[10] & (|(CLKMGR_PERMIT[10] & ~reg_be))) |
2489 (addr_hit[11] & (|(CLKMGR_PERMIT[11] & ~reg_be))) |
2490 (addr_hit[12] & (|(CLKMGR_PERMIT[12] & ~reg_be))) |
2491 (addr_hit[13] & (|(CLKMGR_PERMIT[13] & ~reg_be))) |
2492 (addr_hit[14] & (|(CLKMGR_PERMIT[14] & ~reg_be))) |
2493 (addr_hit[15] & (|(CLKMGR_PERMIT[15] & ~reg_be))) |
2494 (addr_hit[16] & (|(CLKMGR_PERMIT[16] & ~reg_be))) |
2495 (addr_hit[17] & (|(CLKMGR_PERMIT[17] & ~reg_be))) |
2496 (addr_hit[18] & (|(CLKMGR_PERMIT[18] & ~reg_be))) |
2497 (addr_hit[19] & (|(CLKMGR_PERMIT[19] & ~reg_be))) |
2498 (addr_hit[20] & (|(CLKMGR_PERMIT[20] & ~reg_be))) |
2499 (addr_hit[21] & (|(CLKMGR_PERMIT[21] & ~reg_be)))));
2500 end
2501
2502 // Generate write-enables
2503 1/1 assign alert_test_we = addr_hit[0] & reg_we & !reg_error;
Tests: T4 T5 T6
2504
2505 1/1 assign alert_test_recov_fault_wd = reg_wdata[0];
Tests: T4 T5 T6
2506
2507 1/1 assign alert_test_fatal_fault_wd = reg_wdata[1];
Tests: T4 T5 T6
2508 1/1 assign extclk_ctrl_regwen_we = addr_hit[1] & reg_we & !reg_error;
Tests: T4 T5 T6
2509
2510 1/1 assign extclk_ctrl_regwen_wd = reg_wdata[0];
Tests: T4 T5 T6
2511 1/1 assign extclk_ctrl_we = addr_hit[2] & reg_we & !reg_error;
Tests: T4 T5 T6
2512
2513 1/1 assign extclk_ctrl_sel_wd = reg_wdata[3:0];
Tests: T4 T5 T6
2514
2515 1/1 assign extclk_ctrl_hi_speed_sel_wd = reg_wdata[7:4];
Tests: T4 T5 T6
2516 1/1 assign extclk_status_re = addr_hit[3] & reg_re & !reg_error;
Tests: T4 T5 T29
2517 1/1 assign jitter_regwen_we = addr_hit[4] & reg_we & !reg_error;
Tests: T4 T5 T6
2518
2519 1/1 assign jitter_regwen_wd = reg_wdata[0];
Tests: T4 T5 T6
2520 1/1 assign jitter_enable_we = addr_hit[5] & reg_we & !reg_error;
Tests: T4 T5 T6
2521
2522 1/1 assign jitter_enable_wd = reg_wdata[3:0];
Tests: T4 T5 T6
2523 1/1 assign clk_enables_we = addr_hit[6] & reg_we & !reg_error;
Tests: T4 T5 T6
2524
2525 1/1 assign clk_enables_clk_io_div4_peri_en_wd = reg_wdata[0];
Tests: T4 T5 T6
2526
2527 1/1 assign clk_enables_clk_io_div2_peri_en_wd = reg_wdata[1];
Tests: T4 T5 T6
2528
2529 1/1 assign clk_enables_clk_io_peri_en_wd = reg_wdata[2];
Tests: T4 T5 T6
2530
2531 1/1 assign clk_enables_clk_usb_peri_en_wd = reg_wdata[3];
Tests: T4 T5 T6
2532 1/1 assign clk_hints_we = addr_hit[7] & reg_we & !reg_error;
Tests: T4 T5 T6
2533
2534 1/1 assign clk_hints_clk_main_aes_hint_wd = reg_wdata[0];
Tests: T4 T5 T6
2535
2536 1/1 assign clk_hints_clk_main_hmac_hint_wd = reg_wdata[1];
Tests: T4 T5 T6
2537
2538 1/1 assign clk_hints_clk_main_kmac_hint_wd = reg_wdata[2];
Tests: T4 T5 T6
2539
2540 1/1 assign clk_hints_clk_main_otbn_hint_wd = reg_wdata[3];
Tests: T4 T5 T6
2541 1/1 assign measure_ctrl_regwen_we = addr_hit[9] & reg_we & !reg_error;
Tests: T4 T5 T6
2542
2543 1/1 assign measure_ctrl_regwen_wd = reg_wdata[0];
Tests: T4 T5 T6
2544 1/1 assign io_meas_ctrl_en_we = addr_hit[10] & reg_we & !reg_error;
Tests: T4 T5 T6
2545
2546 1/1 assign io_meas_ctrl_shadowed_re = addr_hit[11] & reg_re & !reg_error;
Tests: T4 T5 T6
2547 1/1 assign io_meas_ctrl_shadowed_we = addr_hit[11] & reg_we & !reg_error;
Tests: T4 T5 T6
2548
2549
2550 1/1 assign io_div2_meas_ctrl_en_we = addr_hit[12] & reg_we & !reg_error;
Tests: T4 T5 T6
2551
2552 1/1 assign io_div2_meas_ctrl_shadowed_re = addr_hit[13] & reg_re & !reg_error;
Tests: T4 T5 T29
2553 1/1 assign io_div2_meas_ctrl_shadowed_we = addr_hit[13] & reg_we & !reg_error;
Tests: T4 T5 T6
2554
2555
2556 1/1 assign io_div4_meas_ctrl_en_we = addr_hit[14] & reg_we & !reg_error;
Tests: T4 T5 T6
2557
2558 1/1 assign io_div4_meas_ctrl_shadowed_re = addr_hit[15] & reg_re & !reg_error;
Tests: T4 T5 T29
2559 1/1 assign io_div4_meas_ctrl_shadowed_we = addr_hit[15] & reg_we & !reg_error;
Tests: T4 T5 T6
2560
2561
2562 1/1 assign main_meas_ctrl_en_we = addr_hit[16] & reg_we & !reg_error;
Tests: T4 T5 T6
2563
2564 1/1 assign main_meas_ctrl_shadowed_re = addr_hit[17] & reg_re & !reg_error;
Tests: T4 T5 T29
2565 1/1 assign main_meas_ctrl_shadowed_we = addr_hit[17] & reg_we & !reg_error;
Tests: T4 T5 T6
2566
2567
2568 1/1 assign usb_meas_ctrl_en_we = addr_hit[18] & reg_we & !reg_error;
Tests: T4 T5 T6
2569
2570 1/1 assign usb_meas_ctrl_shadowed_re = addr_hit[19] & reg_re & !reg_error;
Tests: T4 T5 T6
2571 1/1 assign usb_meas_ctrl_shadowed_we = addr_hit[19] & reg_we & !reg_error;
Tests: T4 T5 T6
2572
2573
2574 1/1 assign recov_err_code_we = addr_hit[20] & reg_we & !reg_error;
Tests: T4 T5 T6
2575
2576 1/1 assign recov_err_code_shadow_update_err_wd = reg_wdata[0];
Tests: T4 T5 T6
2577
2578 1/1 assign recov_err_code_io_measure_err_wd = reg_wdata[1];
Tests: T4 T5 T6
2579
2580 1/1 assign recov_err_code_io_div2_measure_err_wd = reg_wdata[2];
Tests: T4 T5 T6
2581
2582 1/1 assign recov_err_code_io_div4_measure_err_wd = reg_wdata[3];
Tests: T4 T5 T6
2583
2584 1/1 assign recov_err_code_main_measure_err_wd = reg_wdata[4];
Tests: T4 T5 T6
2585
2586 1/1 assign recov_err_code_usb_measure_err_wd = reg_wdata[5];
Tests: T4 T5 T6
2587
2588 1/1 assign recov_err_code_io_timeout_err_wd = reg_wdata[6];
Tests: T4 T5 T6
2589
2590 1/1 assign recov_err_code_io_div2_timeout_err_wd = reg_wdata[7];
Tests: T4 T5 T6
2591
2592 1/1 assign recov_err_code_io_div4_timeout_err_wd = reg_wdata[8];
Tests: T4 T5 T6
2593
2594 1/1 assign recov_err_code_main_timeout_err_wd = reg_wdata[9];
Tests: T4 T5 T6
2595
2596 1/1 assign recov_err_code_usb_timeout_err_wd = reg_wdata[10];
Tests: T4 T5 T6
2597
2598 // Assign write-enables to checker logic vector.
2599 always_comb begin
2600 1/1 reg_we_check = '0;
Tests: T4 T5 T6
2601 1/1 reg_we_check[0] = alert_test_we;
Tests: T4 T5 T6
2602 1/1 reg_we_check[1] = extclk_ctrl_regwen_we;
Tests: T4 T5 T6
2603 1/1 reg_we_check[2] = extclk_ctrl_gated_we;
Tests: T4 T5 T6
2604 1/1 reg_we_check[3] = 1'b0;
Tests: T4 T5 T6
2605 1/1 reg_we_check[4] = jitter_regwen_we;
Tests: T4 T5 T6
2606 1/1 reg_we_check[5] = jitter_enable_we;
Tests: T4 T5 T6
2607 1/1 reg_we_check[6] = clk_enables_we;
Tests: T4 T5 T6
2608 1/1 reg_we_check[7] = clk_hints_we;
Tests: T4 T5 T6
2609 1/1 reg_we_check[8] = 1'b0;
Tests: T4 T5 T6
2610 1/1 reg_we_check[9] = measure_ctrl_regwen_we;
Tests: T4 T5 T6
2611 1/1 reg_we_check[10] = io_meas_ctrl_en_we;
Tests: T4 T5 T6
2612 1/1 reg_we_check[11] = io_meas_ctrl_shadowed_we;
Tests: T4 T5 T6
2613 1/1 reg_we_check[12] = io_div2_meas_ctrl_en_we;
Tests: T4 T5 T6
2614 1/1 reg_we_check[13] = io_div2_meas_ctrl_shadowed_we;
Tests: T4 T5 T6
2615 1/1 reg_we_check[14] = io_div4_meas_ctrl_en_we;
Tests: T4 T5 T6
2616 1/1 reg_we_check[15] = io_div4_meas_ctrl_shadowed_we;
Tests: T4 T5 T6
2617 1/1 reg_we_check[16] = main_meas_ctrl_en_we;
Tests: T4 T5 T6
2618 1/1 reg_we_check[17] = main_meas_ctrl_shadowed_we;
Tests: T4 T5 T6
2619 1/1 reg_we_check[18] = usb_meas_ctrl_en_we;
Tests: T4 T5 T6
2620 1/1 reg_we_check[19] = usb_meas_ctrl_shadowed_we;
Tests: T4 T5 T6
2621 1/1 reg_we_check[20] = recov_err_code_we;
Tests: T4 T5 T6
2622 1/1 reg_we_check[21] = 1'b0;
Tests: T4 T5 T6
2623 end
2624
2625 // Read data return
2626 always_comb begin
2627 1/1 reg_rdata_next = '0;
Tests: T4 T5 T6
2628 1/1 unique case (1'b1)
Tests: T4 T5 T6
2629 addr_hit[0]: begin
2630 1/1 reg_rdata_next[0] = '0;
Tests: T4 T5 T28
2631 1/1 reg_rdata_next[1] = '0;
Tests: T4 T5 T28
2632 end
2633
2634 addr_hit[1]: begin
2635 1/1 reg_rdata_next[0] = extclk_ctrl_regwen_qs;
Tests: T4 T5 T6
2636 end
2637
2638 addr_hit[2]: begin
2639 1/1 reg_rdata_next[3:0] = extclk_ctrl_sel_qs;
Tests: T4 T5 T28
2640 1/1 reg_rdata_next[7:4] = extclk_ctrl_hi_speed_sel_qs;
Tests: T4 T5 T28
2641 end
2642
2643 addr_hit[3]: begin
2644 1/1 reg_rdata_next[3:0] = extclk_status_qs;
Tests: T4 T28 T29
2645 end
2646
2647 addr_hit[4]: begin
2648 1/1 reg_rdata_next[0] = jitter_regwen_qs;
Tests: T4 T28 T29
2649 end
2650
2651 addr_hit[5]: begin
2652 1/1 reg_rdata_next[3:0] = jitter_enable_qs;
Tests: T4 T28 T29
2653 end
2654
2655 addr_hit[6]: begin
2656 1/1 reg_rdata_next[0] = clk_enables_clk_io_div4_peri_en_qs;
Tests: T4 T6 T28
2657 1/1 reg_rdata_next[1] = clk_enables_clk_io_div2_peri_en_qs;
Tests: T4 T6 T28
2658 1/1 reg_rdata_next[2] = clk_enables_clk_io_peri_en_qs;
Tests: T4 T6 T28
2659 1/1 reg_rdata_next[3] = clk_enables_clk_usb_peri_en_qs;
Tests: T4 T6 T28
2660 end
2661
2662 addr_hit[7]: begin
2663 1/1 reg_rdata_next[0] = clk_hints_clk_main_aes_hint_qs;
Tests: T4 T5 T28
2664 1/1 reg_rdata_next[1] = clk_hints_clk_main_hmac_hint_qs;
Tests: T4 T5 T28
2665 1/1 reg_rdata_next[2] = clk_hints_clk_main_kmac_hint_qs;
Tests: T4 T5 T28
2666 1/1 reg_rdata_next[3] = clk_hints_clk_main_otbn_hint_qs;
Tests: T4 T5 T28
2667 end
2668
2669 addr_hit[8]: begin
2670 1/1 reg_rdata_next[0] = clk_hints_status_clk_main_aes_val_qs;
Tests: T4 T5 T28
2671 1/1 reg_rdata_next[1] = clk_hints_status_clk_main_hmac_val_qs;
Tests: T4 T5 T28
2672 1/1 reg_rdata_next[2] = clk_hints_status_clk_main_kmac_val_qs;
Tests: T4 T5 T28
2673 1/1 reg_rdata_next[3] = clk_hints_status_clk_main_otbn_val_qs;
Tests: T4 T5 T28
2674 end
2675
2676 addr_hit[9]: begin
2677 1/1 reg_rdata_next[0] = measure_ctrl_regwen_qs;
Tests: T4 T28 T29
2678 end
2679
2680 addr_hit[10]: begin
2681 1/1 reg_rdata_next = DW'(io_meas_ctrl_en_qs);
Tests: T4 T5 T28
2682 end
2683 addr_hit[11]: begin
2684 1/1 reg_rdata_next = DW'(io_meas_ctrl_shadowed_qs);
Tests: T4 T5 T6
2685 end
2686 addr_hit[12]: begin
2687 1/1 reg_rdata_next = DW'(io_div2_meas_ctrl_en_qs);
Tests: T4 T28 T29
2688 end
2689 addr_hit[13]: begin
2690 1/1 reg_rdata_next = DW'(io_div2_meas_ctrl_shadowed_qs);
Tests: T4 T5 T28
2691 end
2692 addr_hit[14]: begin
2693 1/1 reg_rdata_next = DW'(io_div4_meas_ctrl_en_qs);
Tests: T4 T5 T28
2694 end
2695 addr_hit[15]: begin
2696 1/1 reg_rdata_next = DW'(io_div4_meas_ctrl_shadowed_qs);
Tests: T4 T28 T29
2697 end
2698 addr_hit[16]: begin
2699 1/1 reg_rdata_next = DW'(main_meas_ctrl_en_qs);
Tests: T4 T6 T28
2700 end
2701 addr_hit[17]: begin
2702 1/1 reg_rdata_next = DW'(main_meas_ctrl_shadowed_qs);
Tests: T4 T5 T28
2703 end
2704 addr_hit[18]: begin
2705 1/1 reg_rdata_next = DW'(usb_meas_ctrl_en_qs);
Tests: T4 T28 T29
2706 end
2707 addr_hit[19]: begin
2708 1/1 reg_rdata_next = DW'(usb_meas_ctrl_shadowed_qs);
Tests: T4 T6 T28
2709 end
2710 addr_hit[20]: begin
2711 1/1 reg_rdata_next[0] = recov_err_code_shadow_update_err_qs;
Tests: T4 T5 T28
2712 1/1 reg_rdata_next[1] = recov_err_code_io_measure_err_qs;
Tests: T4 T5 T28
2713 1/1 reg_rdata_next[2] = recov_err_code_io_div2_measure_err_qs;
Tests: T4 T5 T28
2714 1/1 reg_rdata_next[3] = recov_err_code_io_div4_measure_err_qs;
Tests: T4 T5 T28
2715 1/1 reg_rdata_next[4] = recov_err_code_main_measure_err_qs;
Tests: T4 T5 T28
2716 1/1 reg_rdata_next[5] = recov_err_code_usb_measure_err_qs;
Tests: T4 T5 T28
2717 1/1 reg_rdata_next[6] = recov_err_code_io_timeout_err_qs;
Tests: T4 T5 T28
2718 1/1 reg_rdata_next[7] = recov_err_code_io_div2_timeout_err_qs;
Tests: T4 T5 T28
2719 1/1 reg_rdata_next[8] = recov_err_code_io_div4_timeout_err_qs;
Tests: T4 T5 T28
2720 1/1 reg_rdata_next[9] = recov_err_code_main_timeout_err_qs;
Tests: T4 T5 T28
2721 1/1 reg_rdata_next[10] = recov_err_code_usb_timeout_err_qs;
Tests: T4 T5 T28
2722 end
2723
2724 addr_hit[21]: begin
2725 1/1 reg_rdata_next[0] = fatal_err_code_reg_intg_qs;
Tests: T4 T5 T28
2726 1/1 reg_rdata_next[1] = fatal_err_code_idle_cnt_qs;
Tests: T4 T5 T28
2727 1/1 reg_rdata_next[2] = fatal_err_code_shadow_storage_err_qs;
Tests: T4 T5 T28
2728 end
2729
2730 default: begin
2731 reg_rdata_next = '1;
2732 end
2733 endcase
2734 end
2735
2736 // shadow busy
2737 logic shadow_busy;
2738 logic rst_done;
2739 logic shadow_rst_done;
2740 always_ff @(posedge clk_i or negedge rst_ni) begin
2741 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
2742 1/1 rst_done <= '0;
Tests: T4 T5 T6
2743 end else begin
2744 1/1 rst_done <= 1'b1;
Tests: T4 T5 T6
2745 end
2746 end
2747
2748 always_ff @(posedge clk_i or negedge rst_shadowed_ni) begin
2749 1/1 if (!rst_shadowed_ni) begin
Tests: T4 T5 T6
2750 1/1 shadow_rst_done <= '0;
Tests: T4 T5 T6
2751 end else begin
2752 1/1 shadow_rst_done <= 1'b1;
Tests: T4 T5 T6
2753 end
2754 end
2755
2756 // both shadow and normal resets have been released
2757 1/1 assign shadow_busy = ~(rst_done & shadow_rst_done);
Tests: T4 T5 T6
2758
2759 // Collect up storage and update errors
2760 1/1 assign shadowed_storage_err_o = |{
Tests: T78 T79 T80
2761 io_meas_ctrl_shadowed_hi_storage_err,
2762 io_meas_ctrl_shadowed_lo_storage_err,
2763 io_div2_meas_ctrl_shadowed_hi_storage_err,
2764 io_div2_meas_ctrl_shadowed_lo_storage_err,
2765 io_div4_meas_ctrl_shadowed_hi_storage_err,
2766 io_div4_meas_ctrl_shadowed_lo_storage_err,
2767 main_meas_ctrl_shadowed_hi_storage_err,
2768 main_meas_ctrl_shadowed_lo_storage_err,
2769 usb_meas_ctrl_shadowed_hi_storage_err,
2770 usb_meas_ctrl_shadowed_lo_storage_err
2771 };
2772 1/1 assign shadowed_update_err_o = |{
Tests: T78 T79 T80
2773 io_meas_ctrl_shadowed_hi_update_err,
2774 io_meas_ctrl_shadowed_lo_update_err,
2775 io_div2_meas_ctrl_shadowed_hi_update_err,
2776 io_div2_meas_ctrl_shadowed_lo_update_err,
2777 io_div4_meas_ctrl_shadowed_hi_update_err,
2778 io_div4_meas_ctrl_shadowed_lo_update_err,
2779 main_meas_ctrl_shadowed_hi_update_err,
2780 main_meas_ctrl_shadowed_lo_update_err,
2781 usb_meas_ctrl_shadowed_hi_update_err,
2782 usb_meas_ctrl_shadowed_lo_update_err
2783 };
2784
2785 // register busy
2786 logic reg_busy_sel;
2787 1/1 assign reg_busy = reg_busy_sel | shadow_busy;
Tests: T4 T5 T6
2788 always_comb begin
2789 1/1 reg_busy_sel = '0;
Tests: T4 T5 T6
2790 1/1 unique case (1'b1)
Tests: T4 T5 T6
2791 addr_hit[10]: begin
2792 1/1 reg_busy_sel = io_meas_ctrl_en_busy;
Tests: T4 T5 T29
2793 end
2794 addr_hit[11]: begin
2795 1/1 reg_busy_sel = io_meas_ctrl_shadowed_busy;
Tests: T4 T5 T6
2796 end
2797 addr_hit[12]: begin
2798 1/1 reg_busy_sel = io_div2_meas_ctrl_en_busy;
Tests: T4 T29 T30
2799 end
2800 addr_hit[13]: begin
2801 1/1 reg_busy_sel = io_div2_meas_ctrl_shadowed_busy;
Tests: T4 T5 T29
2802 end
2803 addr_hit[14]: begin
2804 1/1 reg_busy_sel = io_div4_meas_ctrl_en_busy;
Tests: T4 T5 T29
2805 end
2806 addr_hit[15]: begin
2807 1/1 reg_busy_sel = io_div4_meas_ctrl_shadowed_busy;
Tests: T4 T29 T30
2808 end
2809 addr_hit[16]: begin
2810 1/1 reg_busy_sel = main_meas_ctrl_en_busy;
Tests: T4 T6 T29
2811 end
2812 addr_hit[17]: begin
2813 1/1 reg_busy_sel = main_meas_ctrl_shadowed_busy;
Tests: T4 T5 T29
2814 end
2815 addr_hit[18]: begin
2816 1/1 reg_busy_sel = usb_meas_ctrl_en_busy;
Tests: T4 T29 T30
2817 end
2818 addr_hit[19]: begin
2819 1/1 reg_busy_sel = usb_meas_ctrl_shadowed_busy;
Tests: T4 T6 T29
2820 end
2821 default: begin
2822 reg_busy_sel = '0;
2823 end
2824 endcase
2825 end
2826
2827
2828 // Unused signal tieoff
2829
2830 // Any write to the jitter_enable CSR writes MuBi4True.
2831 // The actual write data is ignored.
2832 logic unused_jitter_enable_wd;
2833 1/1 assign unused_jitter_enable_wd = ^jitter_enable_wd;
Tests: T4 T5 T6
2834
2835 // wdata / byte enable are not always fully used
2836 // add a blanket unused statement to handle lint waivers
2837 logic unused_wdata;
2838 logic unused_be;
2839 1/1 assign unused_wdata = ^reg_wdata;
Tests: T4 T5 T6
2840 1/1 assign unused_be = ^reg_be;
Tests: T4 T5 T6