Module Definition
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Module : clkmgr_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.57 100.00 98.30 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_reg_0.1/rtl/clkmgr_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.64 98.40 95.42 100.00 97.91 96.48


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test_fatal_fault 100.00 100.00
u_alert_test_recov_fault 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_clk_enables_clk_io_div2_peri_en 100.00 100.00 100.00 100.00
u_clk_enables_clk_io_div4_peri_en 100.00 100.00 100.00 100.00
u_clk_enables_clk_io_peri_en 100.00 100.00 100.00 100.00
u_clk_enables_clk_usb_peri_en 100.00 100.00 100.00 100.00
u_clk_hints_clk_main_aes_hint 100.00 100.00 100.00 100.00
u_clk_hints_clk_main_hmac_hint 100.00 100.00 100.00 100.00
u_clk_hints_clk_main_kmac_hint 100.00 100.00 100.00 100.00
u_clk_hints_clk_main_otbn_hint 100.00 100.00 100.00 100.00
u_clk_hints_status_clk_main_aes_val 92.59 77.78 100.00 100.00
u_clk_hints_status_clk_main_hmac_val 92.59 77.78 100.00 100.00
u_clk_hints_status_clk_main_kmac_val 92.59 77.78 100.00 100.00
u_clk_hints_status_clk_main_otbn_val 92.59 77.78 100.00 100.00
u_extclk_ctrl_hi_speed_sel 100.00 100.00 100.00 100.00
u_extclk_ctrl_regwen 100.00 100.00 100.00 100.00
u_extclk_ctrl_sel 100.00 100.00 100.00 100.00
u_extclk_status 100.00 100.00
u_fatal_err_code_idle_cnt 96.30 88.89 100.00 100.00
u_fatal_err_code_reg_intg 96.30 88.89 100.00 100.00
u_fatal_err_code_shadow_storage_err 96.30 88.89 100.00 100.00
u_io_div2_meas_ctrl_en 100.00 100.00 100.00 100.00
u_io_div2_meas_ctrl_en_cdc 89.66 96.24 80.88 91.53 90.00
u_io_div2_meas_ctrl_shadowed_cdc 98.39 100.00 93.55 100.00 100.00
u_io_div2_meas_ctrl_shadowed_hi 99.55 100.00 98.21 100.00 100.00
u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync 100.00 100.00 100.00
u_io_div2_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_io_div2_meas_ctrl_shadowed_lo 99.55 100.00 98.21 100.00 100.00
u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync 100.00 100.00 100.00
u_io_div2_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_io_div4_meas_ctrl_en 100.00 100.00 100.00 100.00
u_io_div4_meas_ctrl_en_cdc 92.36 97.74 86.76 94.92 90.00
u_io_div4_meas_ctrl_shadowed_cdc 98.39 100.00 93.55 100.00 100.00
u_io_div4_meas_ctrl_shadowed_hi 99.55 100.00 98.21 100.00 100.00
u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync 100.00 100.00 100.00
u_io_div4_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_io_div4_meas_ctrl_shadowed_lo 99.55 100.00 98.21 100.00 100.00
u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync 100.00 100.00 100.00
u_io_div4_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_io_meas_ctrl_en 100.00 100.00 100.00 100.00
u_io_meas_ctrl_en_cdc 89.66 96.24 80.88 91.53 90.00
u_io_meas_ctrl_shadowed_cdc 98.39 100.00 93.55 100.00 100.00
u_io_meas_ctrl_shadowed_hi 99.55 100.00 98.21 100.00 100.00
u_io_meas_ctrl_shadowed_hi_err_storage_sync 100.00 100.00 100.00
u_io_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_io_meas_ctrl_shadowed_lo 99.55 100.00 98.21 100.00 100.00
u_io_meas_ctrl_shadowed_lo_err_storage_sync 100.00 100.00 100.00
u_io_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_jitter_enable 100.00 100.00 100.00 100.00
u_jitter_regwen 100.00 100.00 100.00 100.00
u_main_meas_ctrl_en 100.00 100.00 100.00 100.00
u_main_meas_ctrl_en_cdc 89.66 96.24 80.88 91.53 90.00
u_main_meas_ctrl_shadowed_cdc 98.39 100.00 93.55 100.00 100.00
u_main_meas_ctrl_shadowed_hi 99.55 100.00 98.21 100.00 100.00
u_main_meas_ctrl_shadowed_hi_err_storage_deglitch 100.00 100.00 100.00
u_main_meas_ctrl_shadowed_hi_err_storage_sync 100.00 100.00 100.00
u_main_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_main_meas_ctrl_shadowed_lo 99.55 100.00 98.21 100.00 100.00
u_main_meas_ctrl_shadowed_lo_err_storage_deglitch 100.00 100.00 100.00
u_main_meas_ctrl_shadowed_lo_err_storage_sync 100.00 100.00 100.00
u_main_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_measure_ctrl_regwen 100.00 100.00 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_recov_err_code_io_div2_measure_err 100.00 100.00 100.00 100.00
u_recov_err_code_io_div2_timeout_err 100.00 100.00 100.00 100.00
u_recov_err_code_io_div4_measure_err 100.00 100.00 100.00 100.00
u_recov_err_code_io_div4_timeout_err 100.00 100.00 100.00 100.00
u_recov_err_code_io_measure_err 100.00 100.00 100.00 100.00
u_recov_err_code_io_timeout_err 100.00 100.00 100.00 100.00
u_recov_err_code_main_measure_err 100.00 100.00 100.00 100.00
u_recov_err_code_main_timeout_err 100.00 100.00 100.00 100.00
u_recov_err_code_shadow_update_err 97.22 100.00 91.67 100.00
u_recov_err_code_usb_measure_err 100.00 100.00 100.00 100.00
u_recov_err_code_usb_timeout_err 100.00 100.00 100.00 100.00
u_reg_if 98.98 97.14 98.80 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_usb_meas_ctrl_en 100.00 100.00 100.00 100.00
u_usb_meas_ctrl_en_cdc 89.66 96.24 80.88 91.53 90.00
u_usb_meas_ctrl_shadowed_cdc 98.39 100.00 93.55 100.00 100.00
u_usb_meas_ctrl_shadowed_hi 99.55 100.00 98.21 100.00 100.00
u_usb_meas_ctrl_shadowed_hi_err_storage_sync 100.00 100.00 100.00
u_usb_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_usb_meas_ctrl_shadowed_lo 99.55 100.00 98.21 100.00 100.00
u_usb_meas_ctrl_shadowed_lo_err_storage_sync 100.00 100.00 100.00
u_usb_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : clkmgr_reg_top
Line No.TotalCoveredPercent
TOTAL245245100.00
ALWAYS8244100.00
CONT_ASSIGN9111100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13311100.00
ALWAYS27744100.00
CONT_ASSIGN30711100.00
ALWAYS32033100.00
CONT_ASSIGN34911100.00
ALWAYS36344100.00
CONT_ASSIGN39311100.00
ALWAYS40633100.00
CONT_ASSIGN43511100.00
ALWAYS44944100.00
CONT_ASSIGN47911100.00
ALWAYS49233100.00
CONT_ASSIGN52111100.00
ALWAYS53544100.00
CONT_ASSIGN56511100.00
ALWAYS57833100.00
CONT_ASSIGN60711100.00
ALWAYS62144100.00
CONT_ASSIGN65111100.00
ALWAYS66433100.00
CONT_ASSIGN69311100.00
CONT_ASSIGN70011100.00
CONT_ASSIGN71511100.00
CONT_ASSIGN73111100.00
CONT_ASSIGN76511100.00
CONT_ASSIGN125311100.00
CONT_ASSIGN125611100.00
CONT_ASSIGN128711100.00
CONT_ASSIGN141011100.00
CONT_ASSIGN141311100.00
CONT_ASSIGN144511100.00
CONT_ASSIGN156811100.00
CONT_ASSIGN157111100.00
CONT_ASSIGN160311100.00
CONT_ASSIGN172611100.00
CONT_ASSIGN172911100.00
CONT_ASSIGN176111100.00
CONT_ASSIGN190811100.00
CONT_ASSIGN191111100.00
CONT_ASSIGN194211100.00
ALWAYS24482323100.00
CONT_ASSIGN247311100.00
ALWAYS247711100.00
CONT_ASSIGN250311100.00
CONT_ASSIGN250511100.00
CONT_ASSIGN250711100.00
CONT_ASSIGN250811100.00
CONT_ASSIGN251011100.00
CONT_ASSIGN251111100.00
CONT_ASSIGN251311100.00
CONT_ASSIGN251511100.00
CONT_ASSIGN251611100.00
CONT_ASSIGN251711100.00
CONT_ASSIGN251911100.00
CONT_ASSIGN252011100.00
CONT_ASSIGN252211100.00
CONT_ASSIGN252311100.00
CONT_ASSIGN252511100.00
CONT_ASSIGN252711100.00
CONT_ASSIGN252911100.00
CONT_ASSIGN253111100.00
CONT_ASSIGN253211100.00
CONT_ASSIGN253411100.00
CONT_ASSIGN253611100.00
CONT_ASSIGN253811100.00
CONT_ASSIGN254011100.00
CONT_ASSIGN254111100.00
CONT_ASSIGN254311100.00
CONT_ASSIGN254411100.00
CONT_ASSIGN254611100.00
CONT_ASSIGN254711100.00
CONT_ASSIGN255011100.00
CONT_ASSIGN255211100.00
CONT_ASSIGN255311100.00
CONT_ASSIGN255611100.00
CONT_ASSIGN255811100.00
CONT_ASSIGN255911100.00
CONT_ASSIGN256211100.00
CONT_ASSIGN256411100.00
CONT_ASSIGN256511100.00
CONT_ASSIGN256811100.00
CONT_ASSIGN257011100.00
CONT_ASSIGN257111100.00
CONT_ASSIGN257411100.00
CONT_ASSIGN257611100.00
CONT_ASSIGN257811100.00
CONT_ASSIGN258011100.00
CONT_ASSIGN258211100.00
CONT_ASSIGN258411100.00
CONT_ASSIGN258611100.00
CONT_ASSIGN258811100.00
CONT_ASSIGN259011100.00
CONT_ASSIGN259211100.00
CONT_ASSIGN259411100.00
CONT_ASSIGN259611100.00
ALWAYS26002323100.00
ALWAYS26274747100.00
ALWAYS274133100.00
ALWAYS274933100.00
CONT_ASSIGN275711100.00
CONT_ASSIGN276011100.00
CONT_ASSIGN277211100.00
CONT_ASSIGN278711100.00
ALWAYS27891212100.00
CONT_ASSIGN283311100.00
CONT_ASSIGN283911100.00
CONT_ASSIGN284011100.00

Click here to see the source line report.
Cond Coverage for Module : clkmgr_reg_top
TotalCoveredPercent
Conditions29428998.30
Logical29428998.30
Non-Logical00
Event00

 LINE       72
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT73,T74,T75
11CoveredT4,T5,T6 

 LINE       84
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT55,T20,T67
10CoveredT123,T124,T125 

 LINE       91
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT55,T20,T67
010CoveredT123,T124,T125
100CoveredT55,T20,T67 

 LINE       133
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT123,T124,T125
010CoveredT73,T74,T75
100CoveredT73,T74,T75 

 LINE       765
 EXPRESSION (extclk_ctrl_we & extclk_ctrl_regwen_qs)
             -------1------   ----------2----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T11,T27
11CoveredT5,T30,T31 

 LINE       1256
 EXPRESSION (io_io_meas_ctrl_en_we & io_io_meas_ctrl_en_regwen)
             ----------1----------   ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T11,T27
11CoveredT1,T2,T3 

 LINE       1287
 EXPRESSION (io_io_meas_ctrl_shadowed_we & io_io_meas_ctrl_shadowed_regwen)
             -------------1-------------   ---------------2---------------
-1--2-StatusTests
01CoveredT1,T11,T27
10CoveredT1,T11,T27
11CoveredT1,T2,T3 

 LINE       1413
 EXPRESSION (io_div2_io_div2_meas_ctrl_en_we & io_div2_io_div2_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T11,T27
11CoveredT1,T2,T3 

 LINE       1445
 EXPRESSION (io_div2_io_div2_meas_ctrl_shadowed_we & io_div2_io_div2_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT1,T11,T27
10CoveredT1,T11,T27
11CoveredT1,T2,T3 

 LINE       1571
 EXPRESSION (io_div4_io_div4_meas_ctrl_en_we & io_div4_io_div4_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T11,T27
11CoveredT1,T2,T3 

 LINE       1603
 EXPRESSION (io_div4_io_div4_meas_ctrl_shadowed_we & io_div4_io_div4_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT1,T11,T27
10CoveredT1,T11,T27
11CoveredT1,T2,T3 

 LINE       1729
 EXPRESSION (main_main_meas_ctrl_en_we & main_main_meas_ctrl_en_regwen)
             ------------1------------   --------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T11,T27
11CoveredT1,T2,T3 

 LINE       1761
 EXPRESSION (main_main_meas_ctrl_shadowed_we & main_main_meas_ctrl_shadowed_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTests
01CoveredT1,T11,T27
10CoveredT1,T11,T27
11CoveredT1,T2,T3 

 LINE       1911
 EXPRESSION (usb_usb_meas_ctrl_en_we & usb_usb_meas_ctrl_en_regwen)
             -----------1-----------   -------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T11,T27
11CoveredT1,T2,T3 

 LINE       1942
 EXPRESSION (usb_usb_meas_ctrl_shadowed_we & usb_usb_meas_ctrl_shadowed_regwen)
             --------------1--------------   ----------------2----------------
-1--2-StatusTests
01CoveredT1,T11,T27
10CoveredT1,T11,T27
11CoveredT1,T2,T3 

 LINE       2449
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T31,T69 

 LINE       2450
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T30 

 LINE       2451
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T30,T31 

 LINE       2452
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_STATUS_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT31,T1,T57 

 LINE       2453
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_REGWEN_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T57,T11 

 LINE       2454
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_ENABLE_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T68,T1 

 LINE       2455
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_ENABLES_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T6,T68 

 LINE       2456
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_OFFSET)
            --------------------------1--------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T29 

 LINE       2457
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_STATUS_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T29,T31 

 LINE       2458
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MEASURE_CTRL_REGWEN_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3 

 LINE       2459
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_EN_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T68,T1 

 LINE       2460
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T1 

 LINE       2461
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3 

 LINE       2462
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T31,T68 

 LINE       2463
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T68,T1 

 LINE       2464
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT68,T1,T57 

 LINE       2465
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_EN_OFFSET)
            ------------------------------1------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T1,T57 

 LINE       2466
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T31,T1 

 LINE       2467
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_EN_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T57,T2 

 LINE       2468
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T68,T1 

 LINE       2469
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_RECOV_ERR_CODE_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T68,T1 

 LINE       2470
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_FATAL_ERR_CODE_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T1,T55 

 LINE       2473
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       2473
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT4,T5,T29 

 LINE       2477
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT73,T74,T75 

 LINE       2477
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT4,T5,T6
22 (addr_hit[21] & ((|(4'...CoveredT5,T1,T9
21 (addr_hit[20] & ((|(4'...CoveredT5,T68,T1
20 (addr_hit[19] & ((|(4'...CoveredT6,T68,T1
19 (addr_hit[18] & ((|(4'...CoveredT1,T2,T19
18 (addr_hit[17] & ((|(4'...CoveredT31,T1,T11
17 (addr_hit[16] & ((|(4'...CoveredT6,T1,T2
16 (addr_hit[15] & ((|(4'...CoveredT68,T1,T57
15 (addr_hit[14] & ((|(4'...CoveredT5,T68,T1
14 (addr_hit[13] & ((|(4'...CoveredT5,T31,T68
13 (addr_hit[12] & ((|(4'...CoveredT1,T2,T19
12 (addr_hit[11] & ((|(4'...CoveredT6,T1,T19
11 (addr_hit[10] & ((|(4'...CoveredT1,T2,T19
10 (addr_hit[9] & ((|(4'b...CoveredT1,T2,T11
9 (addr_hit[8] & ((|(4'b...CoveredT29,T31,T32
8 (addr_hit[7] & ((|(4'b...CoveredT5,T68,T1
7 (addr_hit[6] & ((|(4'b...CoveredT1,T9,T50
6 (addr_hit[5] & ((|(4'b...CoveredT4,T68,T1
5 (addr_hit[4] & ((|(4'b...CoveredT1,T9,T40
4 (addr_hit[3] & ((|(4'b...CoveredT31,T1,T58
3 (addr_hit[2] & ((|(4'b...CoveredT5,T30,T33
2 (addr_hit[1] & ((|(4'b...CoveredT6,T68,T1
1 (addr_hit[0] & ((|(4'b...CoveredT1,T9,T40 

 LINE       2477
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T31,T69
11CoveredT1,T9,T40 

 LINE       2477
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T30,T31
11CoveredT6,T68,T1 

 LINE       2477
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T30,T31
11CoveredT5,T30,T33 

 LINE       2477
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T57,T58
11CoveredT31,T1,T58 

 LINE       2477
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T57,T11
11CoveredT1,T9,T40 

 LINE       2477
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT5,T6,T29
10CoveredT4,T68,T1
11CoveredT4,T68,T1 

 LINE       2477
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T6,T68
11CoveredT1,T9,T50 

 LINE       2477
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T29,T32
11CoveredT5,T68,T1 

 LINE       2477
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T29,T32
11CoveredT29,T31,T32 

 LINE       2477
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T11 

 LINE       2477
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T68,T1
11CoveredT1,T2,T19 

 LINE       2477
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T1,T2
11CoveredT6,T1,T19 

 LINE       2477
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T19 

 LINE       2477
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT5,T31,T68 

 LINE       2477
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T1,T2
11CoveredT5,T68,T1 

 LINE       2477
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT68,T1,T57 

 LINE       2477
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T57,T2
11CoveredT6,T1,T2 

 LINE       2477
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T1,T2
11CoveredT31,T1,T11 

 LINE       2477
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T57,T2
11CoveredT1,T2,T19 

 LINE       2477
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT68,T1,T2
11CoveredT6,T68,T1 

 LINE       2477
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT5,T68,T1 

 LINE       2477
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T55,T19
11CoveredT5,T1,T9 

 LINE       2503
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T31,T69
110CoveredT73,T74,T75
111CoveredT69,T22,T64 

 LINE       2508
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T30
110CoveredT73,T74,T75
111CoveredT5,T30,T31 

 LINE       2511
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T30,T31
110CoveredT73,T74,T75
111CoveredT5,T30,T31 

 LINE       2516
 EXPRESSION (addr_hit[3] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T29
101CoveredT31,T1,T57
110CoveredT126,T127,T128
111CoveredT31,T58,T62 

 LINE       2517
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T57,T11
110CoveredT73,T74,T75
111CoveredT1,T11,T27 

 LINE       2520
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT4,T68,T1
110CoveredT73,T74,T75
111CoveredT4,T68,T1 

 LINE       2523
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T29
101CoveredT4,T6,T68
110CoveredT73,T74,T75
111CoveredT4,T6,T68 

 LINE       2532
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT4,T5,T29
110CoveredT73,T74,T75
111CoveredT4,T29,T32 

 LINE       2541
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T2,T3
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2544
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T68,T1
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2546
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T29
101CoveredT5,T6,T1
110CoveredT124,T129,T126
111CoveredT1,T11,T27 

 LINE       2547
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T1
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2550
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T57,T2
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2552
 EXPRESSION (addr_hit[13] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T29
101CoveredT5,T31,T68
110CoveredT130,T131,T132
111CoveredT1,T11,T27 

 LINE       2553
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T31,T68
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2556
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T68,T1
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2558
 EXPRESSION (addr_hit[15] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T29
101CoveredT31,T68,T1
110CoveredT129
111CoveredT1,T11,T27 

 LINE       2559
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT31,T68,T1
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2562
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT6,T1,T53
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2564
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T29
101CoveredT5,T31,T1
110CoveredT125
111CoveredT1,T11,T27 

 LINE       2565
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T31,T1
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2568
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T57,T2
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2570
 EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T29
101CoveredT6,T68,T1
110CoveredT124,T126,T133
111CoveredT1,T11,T27 

 LINE       2571
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT6,T68,T1
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2574
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T68,T1
110CoveredT73,T74,T75
111CoveredT2,T3,T9 

 LINE       2757
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------
-1--2-StatusTests
01CoveredT78,T79,T80
10CoveredT55,T134,T135
11CoveredT4,T5,T6 

 LINE       2787
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT5,T6,T31
10CoveredT1,T2,T3
Branch Coverage for Module : clkmgr_reg_top
Line No.TotalCoveredPercent
Branches 43 43 100.00
TERNARY 2473 2 2 100.00
IF 82 3 3 100.00
CASE 2628 23 23 100.00
IF 2741 2 2 100.00
IF 2749 2 2 100.00
CASE 2790 11 11 100.00 



2473         assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



82             if (!rst_ni) begin
               -1-  
83               err_q <= '0;
                 ==>
84             end else if (intg_err || reg_we_err) begin
                        -2-  
85               err_q <= 1'b1;
                 ==>
86             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T55,T20,T67
0 0 Covered T4,T5,T6 



2628           unique case (1'b1)
                      -1-  
2629             addr_hit[0]: begin
2630               reg_rdata_next[0] = '0;
                   ==>
2631               reg_rdata_next[1] = '0;
2632             end
2633       
2634             addr_hit[1]: begin
2635               reg_rdata_next[0] = extclk_ctrl_regwen_qs;
                   ==>
2636             end
2637       
2638             addr_hit[2]: begin
2639               reg_rdata_next[3:0] = extclk_ctrl_sel_qs;
                   ==>
2640               reg_rdata_next[7:4] = extclk_ctrl_hi_speed_sel_qs;
2641             end
2642       
2643             addr_hit[3]: begin
2644               reg_rdata_next[3:0] = extclk_status_qs;
                   ==>
2645             end
2646       
2647             addr_hit[4]: begin
2648               reg_rdata_next[0] = jitter_regwen_qs;
                   ==>
2649             end
2650       
2651             addr_hit[5]: begin
2652               reg_rdata_next[3:0] = jitter_enable_qs;
                   ==>
2653             end
2654       
2655             addr_hit[6]: begin
2656               reg_rdata_next[0] = clk_enables_clk_io_div4_peri_en_qs;
                   ==>
2657               reg_rdata_next[1] = clk_enables_clk_io_div2_peri_en_qs;
2658               reg_rdata_next[2] = clk_enables_clk_io_peri_en_qs;
2659               reg_rdata_next[3] = clk_enables_clk_usb_peri_en_qs;
2660             end
2661       
2662             addr_hit[7]: begin
2663               reg_rdata_next[0] = clk_hints_clk_main_aes_hint_qs;
                   ==>
2664               reg_rdata_next[1] = clk_hints_clk_main_hmac_hint_qs;
2665               reg_rdata_next[2] = clk_hints_clk_main_kmac_hint_qs;
2666               reg_rdata_next[3] = clk_hints_clk_main_otbn_hint_qs;
2667             end
2668       
2669             addr_hit[8]: begin
2670               reg_rdata_next[0] = clk_hints_status_clk_main_aes_val_qs;
                   ==>
2671               reg_rdata_next[1] = clk_hints_status_clk_main_hmac_val_qs;
2672               reg_rdata_next[2] = clk_hints_status_clk_main_kmac_val_qs;
2673               reg_rdata_next[3] = clk_hints_status_clk_main_otbn_val_qs;
2674             end
2675       
2676             addr_hit[9]: begin
2677               reg_rdata_next[0] = measure_ctrl_regwen_qs;
                   ==>
2678             end
2679       
2680             addr_hit[10]: begin
2681               reg_rdata_next = DW'(io_meas_ctrl_en_qs);
                   ==>
2682             end
2683             addr_hit[11]: begin
2684               reg_rdata_next = DW'(io_meas_ctrl_shadowed_qs);
                   ==>
2685             end
2686             addr_hit[12]: begin
2687               reg_rdata_next = DW'(io_div2_meas_ctrl_en_qs);
                   ==>
2688             end
2689             addr_hit[13]: begin
2690               reg_rdata_next = DW'(io_div2_meas_ctrl_shadowed_qs);
                   ==>
2691             end
2692             addr_hit[14]: begin
2693               reg_rdata_next = DW'(io_div4_meas_ctrl_en_qs);
                   ==>
2694             end
2695             addr_hit[15]: begin
2696               reg_rdata_next = DW'(io_div4_meas_ctrl_shadowed_qs);
                   ==>
2697             end
2698             addr_hit[16]: begin
2699               reg_rdata_next = DW'(main_meas_ctrl_en_qs);
                   ==>
2700             end
2701             addr_hit[17]: begin
2702               reg_rdata_next = DW'(main_meas_ctrl_shadowed_qs);
                   ==>
2703             end
2704             addr_hit[18]: begin
2705               reg_rdata_next = DW'(usb_meas_ctrl_en_qs);
                   ==>
2706             end
2707             addr_hit[19]: begin
2708               reg_rdata_next = DW'(usb_meas_ctrl_shadowed_qs);
                   ==>
2709             end
2710             addr_hit[20]: begin
2711               reg_rdata_next[0] = recov_err_code_shadow_update_err_qs;
                   ==>
2712               reg_rdata_next[1] = recov_err_code_io_measure_err_qs;
2713               reg_rdata_next[2] = recov_err_code_io_div2_measure_err_qs;
2714               reg_rdata_next[3] = recov_err_code_io_div4_measure_err_qs;
2715               reg_rdata_next[4] = recov_err_code_main_measure_err_qs;
2716               reg_rdata_next[5] = recov_err_code_usb_measure_err_qs;
2717               reg_rdata_next[6] = recov_err_code_io_timeout_err_qs;
2718               reg_rdata_next[7] = recov_err_code_io_div2_timeout_err_qs;
2719               reg_rdata_next[8] = recov_err_code_io_div4_timeout_err_qs;
2720               reg_rdata_next[9] = recov_err_code_main_timeout_err_qs;
2721               reg_rdata_next[10] = recov_err_code_usb_timeout_err_qs;
2722             end
2723       
2724             addr_hit[21]: begin
2725               reg_rdata_next[0] = fatal_err_code_reg_intg_qs;
                   ==>
2726               reg_rdata_next[1] = fatal_err_code_idle_cnt_qs;
2727               reg_rdata_next[2] = fatal_err_code_shadow_storage_err_qs;
2728             end
2729       
2730             default: begin
2731               reg_rdata_next = '1;
                   ==>

Branches:
-1-StatusTests
addr_hit[0] Covered T4,T5,T28
addr_hit[1] Covered T4,T5,T6
addr_hit[2] Covered T4,T5,T28
addr_hit[3] Covered T4,T28,T29
addr_hit[4] Covered T4,T28,T29
addr_hit[5] Covered T4,T28,T29
addr_hit[6] Covered T4,T6,T28
addr_hit[7] Covered T4,T5,T28
addr_hit[8] Covered T4,T5,T28
addr_hit[9] Covered T4,T28,T29
addr_hit[10] Covered T4,T5,T28
addr_hit[11] Covered T4,T5,T6
addr_hit[12] Covered T4,T28,T29
addr_hit[13] Covered T4,T5,T28
addr_hit[14] Covered T4,T5,T28
addr_hit[15] Covered T4,T28,T29
addr_hit[16] Covered T4,T6,T28
addr_hit[17] Covered T4,T5,T28
addr_hit[18] Covered T4,T28,T29
addr_hit[19] Covered T4,T6,T28
addr_hit[20] Covered T4,T5,T28
addr_hit[21] Covered T4,T5,T28
default Covered T4,T5,T6 



2741           if (!rst_ni) begin
               -1-  
2742             rst_done <= '0;
                 ==>
2743           end else begin
2744             rst_done <= 1'b1;
                 ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



2749           if (!rst_shadowed_ni) begin
               -1-  
2750             shadow_rst_done <= '0;
                 ==>
2751           end else begin
2752             shadow_rst_done <= 1'b1;
                 ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



2790           unique case (1'b1)
                      -1-  
2791             addr_hit[10]: begin
2792               reg_busy_sel = io_meas_ctrl_en_busy;
                   ==>
2793             end
2794             addr_hit[11]: begin
2795               reg_busy_sel = io_meas_ctrl_shadowed_busy;
                   ==>
2796             end
2797             addr_hit[12]: begin
2798               reg_busy_sel = io_div2_meas_ctrl_en_busy;
                   ==>
2799             end
2800             addr_hit[13]: begin
2801               reg_busy_sel = io_div2_meas_ctrl_shadowed_busy;
                   ==>
2802             end
2803             addr_hit[14]: begin
2804               reg_busy_sel = io_div4_meas_ctrl_en_busy;
                   ==>
2805             end
2806             addr_hit[15]: begin
2807               reg_busy_sel = io_div4_meas_ctrl_shadowed_busy;
                   ==>
2808             end
2809             addr_hit[16]: begin
2810               reg_busy_sel = main_meas_ctrl_en_busy;
                   ==>
2811             end
2812             addr_hit[17]: begin
2813               reg_busy_sel = main_meas_ctrl_shadowed_busy;
                   ==>
2814             end
2815             addr_hit[18]: begin
2816               reg_busy_sel = usb_meas_ctrl_en_busy;
                   ==>
2817             end
2818             addr_hit[19]: begin
2819               reg_busy_sel = usb_meas_ctrl_shadowed_busy;
                   ==>
2820             end
2821             default: begin
2822               reg_busy_sel  = '0;
                   ==>

Branches:
-1-StatusTests
addr_hit[10] Covered T4,T5,T29
addr_hit[11] Covered T4,T5,T6
addr_hit[12] Covered T4,T29,T30
addr_hit[13] Covered T4,T5,T29
addr_hit[14] Covered T4,T5,T29
addr_hit[15] Covered T4,T29,T30
addr_hit[16] Covered T4,T6,T29
addr_hit[17] Covered T4,T5,T29
addr_hit[18] Covered T4,T29,T30
addr_hit[19] Covered T4,T6,T29
default Covered T4,T5,T6

Assert Coverage for Module : clkmgr_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
en2addrHit 172024014 823959 0 0
reAfterRv 172024014 823959 0 0
rePulse 172024014 180770 0 0
wePulse 172024014 643189 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 172024014 823959 0 0
T4 1267 22 0 0
T5 1229 19 0 0
T6 1446 5 0 0
T28 1362 0 0 0
T29 1501 49 0 0
T30 1454 28 0 0
T31 1340 8 0 0
T32 2243 70 0 0
T33 1756 61 0 0
T34 2129 49 0 0
T69 0 12 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 172024014 823959 0 0
T4 1267 22 0 0
T5 1229 19 0 0
T6 1446 5 0 0
T28 1362 0 0 0
T29 1501 49 0 0
T30 1454 28 0 0
T31 1340 8 0 0
T32 2243 70 0 0
T33 1756 61 0 0
T34 2129 49 0 0
T69 0 12 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 172024014 180770 0 0
T4 1267 13 0 0
T5 1229 6 0 0
T6 1446 0 0 0
T28 1362 0 0 0
T29 1501 28 0 0
T30 1454 9 0 0
T31 1340 3 0 0
T32 2243 40 0 0
T33 1756 20 0 0
T34 2129 16 0 0
T68 0 13 0 0
T104 0 6 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 172024014 643189 0 0
T4 1267 9 0 0
T5 1229 13 0 0
T6 1446 5 0 0
T28 1362 0 0 0
T29 1501 21 0 0
T30 1454 19 0 0
T31 1340 5 0 0
T32 2243 30 0 0
T33 1756 41 0 0
T34 2129 33 0 0
T69 0 12 0 0

Line Coverage for Instance : tb.dut.u_reg
Line No.TotalCoveredPercent
TOTAL245245100.00
ALWAYS8244100.00
CONT_ASSIGN9111100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13311100.00
ALWAYS27744100.00
CONT_ASSIGN30711100.00
ALWAYS32033100.00
CONT_ASSIGN34911100.00
ALWAYS36344100.00
CONT_ASSIGN39311100.00
ALWAYS40633100.00
CONT_ASSIGN43511100.00
ALWAYS44944100.00
CONT_ASSIGN47911100.00
ALWAYS49233100.00
CONT_ASSIGN52111100.00
ALWAYS53544100.00
CONT_ASSIGN56511100.00
ALWAYS57833100.00
CONT_ASSIGN60711100.00
ALWAYS62144100.00
CONT_ASSIGN65111100.00
ALWAYS66433100.00
CONT_ASSIGN69311100.00
CONT_ASSIGN70011100.00
CONT_ASSIGN71511100.00
CONT_ASSIGN73111100.00
CONT_ASSIGN76511100.00
CONT_ASSIGN125311100.00
CONT_ASSIGN125611100.00
CONT_ASSIGN128711100.00
CONT_ASSIGN141011100.00
CONT_ASSIGN141311100.00
CONT_ASSIGN144511100.00
CONT_ASSIGN156811100.00
CONT_ASSIGN157111100.00
CONT_ASSIGN160311100.00
CONT_ASSIGN172611100.00
CONT_ASSIGN172911100.00
CONT_ASSIGN176111100.00
CONT_ASSIGN190811100.00
CONT_ASSIGN191111100.00
CONT_ASSIGN194211100.00
ALWAYS24482323100.00
CONT_ASSIGN247311100.00
ALWAYS247711100.00
CONT_ASSIGN250311100.00
CONT_ASSIGN250511100.00
CONT_ASSIGN250711100.00
CONT_ASSIGN250811100.00
CONT_ASSIGN251011100.00
CONT_ASSIGN251111100.00
CONT_ASSIGN251311100.00
CONT_ASSIGN251511100.00
CONT_ASSIGN251611100.00
CONT_ASSIGN251711100.00
CONT_ASSIGN251911100.00
CONT_ASSIGN252011100.00
CONT_ASSIGN252211100.00
CONT_ASSIGN252311100.00
CONT_ASSIGN252511100.00
CONT_ASSIGN252711100.00
CONT_ASSIGN252911100.00
CONT_ASSIGN253111100.00
CONT_ASSIGN253211100.00
CONT_ASSIGN253411100.00
CONT_ASSIGN253611100.00
CONT_ASSIGN253811100.00
CONT_ASSIGN254011100.00
CONT_ASSIGN254111100.00
CONT_ASSIGN254311100.00
CONT_ASSIGN254411100.00
CONT_ASSIGN254611100.00
CONT_ASSIGN254711100.00
CONT_ASSIGN255011100.00
CONT_ASSIGN255211100.00
CONT_ASSIGN255311100.00
CONT_ASSIGN255611100.00
CONT_ASSIGN255811100.00
CONT_ASSIGN255911100.00
CONT_ASSIGN256211100.00
CONT_ASSIGN256411100.00
CONT_ASSIGN256511100.00
CONT_ASSIGN256811100.00
CONT_ASSIGN257011100.00
CONT_ASSIGN257111100.00
CONT_ASSIGN257411100.00
CONT_ASSIGN257611100.00
CONT_ASSIGN257811100.00
CONT_ASSIGN258011100.00
CONT_ASSIGN258211100.00
CONT_ASSIGN258411100.00
CONT_ASSIGN258611100.00
CONT_ASSIGN258811100.00
CONT_ASSIGN259011100.00
CONT_ASSIGN259211100.00
CONT_ASSIGN259411100.00
CONT_ASSIGN259611100.00
ALWAYS26002323100.00
ALWAYS26274747100.00
ALWAYS274133100.00
ALWAYS274933100.00
CONT_ASSIGN275711100.00
CONT_ASSIGN276011100.00
CONT_ASSIGN277211100.00
CONT_ASSIGN278711100.00
ALWAYS27891212100.00
CONT_ASSIGN283311100.00
CONT_ASSIGN283911100.00
CONT_ASSIGN284011100.00

Click here to see the source line report.
Cond Coverage for Instance : tb.dut.u_reg
TotalCoveredPercent
Conditions289289100.00
Logical289289100.00
Non-Logical00
Event00

 LINE       72
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT73,T74,T75
11CoveredT4,T5,T6 

 LINE       84
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT55,T20,T67
10CoveredT123,T124,T125 

 LINE       91
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT55,T20,T67
010CoveredT123,T124,T125
100CoveredT55,T20,T67 

 LINE       133
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT123,T124,T125
010CoveredT73,T74,T75
100CoveredT73,T74,T75 

 LINE       765
 EXPRESSION (extclk_ctrl_we & extclk_ctrl_regwen_qs)
             -------1------   ----------2----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T11,T27
11CoveredT5,T30,T31 

 LINE       1256
 EXPRESSION (io_io_meas_ctrl_en_we & io_io_meas_ctrl_en_regwen)
             ----------1----------   ------------2------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT1,T11,T27
11CoveredT1,T2,T3 

 LINE       1287
 EXPRESSION (io_io_meas_ctrl_shadowed_we & io_io_meas_ctrl_shadowed_regwen)
             -------------1-------------   ---------------2---------------
-1--2-StatusTests
01CoveredT1,T11,T27
10CoveredT1,T11,T27
11CoveredT1,T2,T3 

 LINE       1413
 EXPRESSION (io_div2_io_div2_meas_ctrl_en_we & io_div2_io_div2_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT1,T11,T27
11CoveredT1,T2,T3 

 LINE       1445
 EXPRESSION (io_div2_io_div2_meas_ctrl_shadowed_we & io_div2_io_div2_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT1,T11,T27
10CoveredT1,T11,T27
11CoveredT1,T2,T3 

 LINE       1571
 EXPRESSION (io_div4_io_div4_meas_ctrl_en_we & io_div4_io_div4_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT1,T11,T27
11CoveredT1,T2,T3 

 LINE       1603
 EXPRESSION (io_div4_io_div4_meas_ctrl_shadowed_we & io_div4_io_div4_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT1,T11,T27
10CoveredT1,T11,T27
11CoveredT1,T2,T3 

 LINE       1729
 EXPRESSION (main_main_meas_ctrl_en_we & main_main_meas_ctrl_en_regwen)
             ------------1------------   --------------2--------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT1,T11,T27
11CoveredT1,T2,T3 

 LINE       1761
 EXPRESSION (main_main_meas_ctrl_shadowed_we & main_main_meas_ctrl_shadowed_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTests
01CoveredT1,T11,T27
10CoveredT1,T11,T27
11CoveredT1,T2,T3 

 LINE       1911
 EXPRESSION (usb_usb_meas_ctrl_en_we & usb_usb_meas_ctrl_en_regwen)
             -----------1-----------   -------------2-------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT1,T11,T27
11CoveredT1,T2,T3 

 LINE       1942
 EXPRESSION (usb_usb_meas_ctrl_shadowed_we & usb_usb_meas_ctrl_shadowed_regwen)
             --------------1--------------   ----------------2----------------
-1--2-StatusTests
01CoveredT1,T11,T27
10CoveredT1,T11,T27
11CoveredT1,T2,T3 

 LINE       2449
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T31,T69 

 LINE       2450
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T30 

 LINE       2451
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T30,T31 

 LINE       2452
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_STATUS_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT31,T1,T57 

 LINE       2453
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_REGWEN_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T57,T11 

 LINE       2454
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_ENABLE_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T68,T1 

 LINE       2455
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_ENABLES_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T6,T68 

 LINE       2456
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_OFFSET)
            --------------------------1--------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T29 

 LINE       2457
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_STATUS_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T29,T31 

 LINE       2458
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MEASURE_CTRL_REGWEN_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3 

 LINE       2459
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_EN_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T68,T1 

 LINE       2460
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T1 

 LINE       2461
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3 

 LINE       2462
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T31,T68 

 LINE       2463
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T68,T1 

 LINE       2464
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT68,T1,T57 

 LINE       2465
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_EN_OFFSET)
            ------------------------------1------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T1,T57 

 LINE       2466
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T31,T1 

 LINE       2467
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_EN_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T57,T2 

 LINE       2468
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT6,T68,T1 

 LINE       2469
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_RECOV_ERR_CODE_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T68,T1 

 LINE       2470
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_FATAL_ERR_CODE_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T1,T55 

 LINE       2473
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       2473
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT4,T5,T29 

 LINE       2477
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT73,T74,T75 

 LINE       2477
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT4,T5,T6
22 (addr_hit[21] & ((|(4'...CoveredT5,T1,T9
21 (addr_hit[20] & ((|(4'...CoveredT5,T68,T1
20 (addr_hit[19] & ((|(4'...CoveredT6,T68,T1
19 (addr_hit[18] & ((|(4'...CoveredT1,T2,T19
18 (addr_hit[17] & ((|(4'...CoveredT31,T1,T11
17 (addr_hit[16] & ((|(4'...CoveredT6,T1,T2
16 (addr_hit[15] & ((|(4'...CoveredT68,T1,T57
15 (addr_hit[14] & ((|(4'...CoveredT5,T68,T1
14 (addr_hit[13] & ((|(4'...CoveredT5,T31,T68
13 (addr_hit[12] & ((|(4'...CoveredT1,T2,T19
12 (addr_hit[11] & ((|(4'...CoveredT6,T1,T19
11 (addr_hit[10] & ((|(4'...CoveredT1,T2,T19
10 (addr_hit[9] & ((|(4'b...CoveredT1,T2,T11
9 (addr_hit[8] & ((|(4'b...CoveredT29,T31,T32
8 (addr_hit[7] & ((|(4'b...CoveredT5,T68,T1
7 (addr_hit[6] & ((|(4'b...CoveredT1,T9,T50
6 (addr_hit[5] & ((|(4'b...CoveredT4,T68,T1
5 (addr_hit[4] & ((|(4'b...CoveredT1,T9,T40
4 (addr_hit[3] & ((|(4'b...CoveredT31,T1,T58
3 (addr_hit[2] & ((|(4'b...CoveredT5,T30,T33
2 (addr_hit[1] & ((|(4'b...CoveredT6,T68,T1
1 (addr_hit[0] & ((|(4'b...CoveredT1,T9,T40 

 LINE       2477
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T31,T69
11CoveredT1,T9,T40 

 LINE       2477
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T30,T31
11CoveredT6,T68,T1 

 LINE       2477
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T30,T31
11CoveredT5,T30,T33 

 LINE       2477
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T57,T58
11CoveredT31,T1,T58 

 LINE       2477
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T57,T11
11CoveredT1,T9,T40 

 LINE       2477
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT5,T6,T29
10CoveredT4,T68,T1
11CoveredT4,T68,T1 

 LINE       2477
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T6,T68
11CoveredT1,T9,T50 

 LINE       2477
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T29,T32
11CoveredT5,T68,T1 

 LINE       2477
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T29,T32
11CoveredT29,T31,T32 

 LINE       2477
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T11 

 LINE       2477
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T68,T1
11CoveredT1,T2,T19 

 LINE       2477
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T1,T2
11CoveredT6,T1,T19 

 LINE       2477
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T19 

 LINE       2477
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT5,T31,T68 

 LINE       2477
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T1,T2
11CoveredT5,T68,T1 

 LINE       2477
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT68,T1,T57 

 LINE       2477
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T57,T2
11CoveredT6,T1,T2 

 LINE       2477
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T1,T2
11CoveredT31,T1,T11 

 LINE       2477
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T57,T2
11CoveredT1,T2,T19 

 LINE       2477
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT68,T1,T2
11CoveredT6,T68,T1 

 LINE       2477
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT5,T68,T1 

 LINE       2477
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T55,T19
11CoveredT5,T1,T9 

 LINE       2503
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T31,T69
110CoveredT73,T74,T75
111CoveredT69,T22,T64 

 LINE       2508
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T30
110CoveredT73,T74,T75
111CoveredT5,T30,T31 

 LINE       2511
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T30,T31
110CoveredT73,T74,T75
111CoveredT5,T30,T31 

 LINE       2516
 EXPRESSION (addr_hit[3] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T29
101CoveredT31,T1,T57
110CoveredT126,T127,T128
111CoveredT31,T58,T62 

 LINE       2517
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T57,T11
110CoveredT73,T74,T75
111CoveredT1,T11,T27 

 LINE       2520
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT4,T68,T1
110CoveredT73,T74,T75
111CoveredT4,T68,T1 

 LINE       2523
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T29
101CoveredT4,T6,T68
110CoveredT73,T74,T75
111CoveredT4,T6,T68 

 LINE       2532
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT4,T5,T29
110CoveredT73,T74,T75
111CoveredT4,T29,T32 

 LINE       2541
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T2,T3
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2544
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T68,T1
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2546
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T29
101CoveredT5,T6,T1
110CoveredT124,T129,T126
111CoveredT1,T11,T27 

 LINE       2547
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T1
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2550
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T57,T2
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2552
 EXPRESSION (addr_hit[13] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T29
101CoveredT5,T31,T68
110CoveredT130,T131,T132
111CoveredT1,T11,T27 

 LINE       2553
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T31,T68
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2556
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T68,T1
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2558
 EXPRESSION (addr_hit[15] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T29
101CoveredT31,T68,T1
110CoveredT129
111CoveredT1,T11,T27 

 LINE       2559
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT31,T68,T1
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2562
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT6,T1,T53
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2564
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T29
101CoveredT5,T31,T1
110CoveredT125
111CoveredT1,T11,T27 

 LINE       2565
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T31,T1
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2568
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T57,T2
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2570
 EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T29
101CoveredT6,T68,T1
110CoveredT124,T126,T133
111CoveredT1,T11,T27 

 LINE       2571
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT6,T68,T1
110CoveredT73,T74,T75
111CoveredT1,T2,T3 

 LINE       2574
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T68,T1
110CoveredT73,T74,T75
111CoveredT2,T3,T9 

 LINE       2757
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------
-1--2-StatusTests
01CoveredT78,T79,T80
10CoveredT55,T134,T135
11CoveredT4,T5,T6 

 LINE       2787
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT5,T6,T31
10CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_reg
Line No.TotalCoveredPercent
Branches 43 43 100.00
TERNARY 2473 2 2 100.00
IF 82 3 3 100.00
CASE 2628 23 23 100.00
IF 2741 2 2 100.00
IF 2749 2 2 100.00
CASE 2790 11 11 100.00 



2473         assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



82             if (!rst_ni) begin
               -1-  
83               err_q <= '0;
                 ==>
84             end else if (intg_err || reg_we_err) begin
                        -2-  
85               err_q <= 1'b1;
                 ==>
86             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T55,T20,T67
0 0 Covered T4,T5,T6 



2628           unique case (1'b1)
                      -1-  
2629             addr_hit[0]: begin
2630               reg_rdata_next[0] = '0;
                   ==>
2631               reg_rdata_next[1] = '0;
2632             end
2633       
2634             addr_hit[1]: begin
2635               reg_rdata_next[0] = extclk_ctrl_regwen_qs;
                   ==>
2636             end
2637       
2638             addr_hit[2]: begin
2639               reg_rdata_next[3:0] = extclk_ctrl_sel_qs;
                   ==>
2640               reg_rdata_next[7:4] = extclk_ctrl_hi_speed_sel_qs;
2641             end
2642       
2643             addr_hit[3]: begin
2644               reg_rdata_next[3:0] = extclk_status_qs;
                   ==>
2645             end
2646       
2647             addr_hit[4]: begin
2648               reg_rdata_next[0] = jitter_regwen_qs;
                   ==>
2649             end
2650       
2651             addr_hit[5]: begin
2652               reg_rdata_next[3:0] = jitter_enable_qs;
                   ==>
2653             end
2654       
2655             addr_hit[6]: begin
2656               reg_rdata_next[0] = clk_enables_clk_io_div4_peri_en_qs;
                   ==>
2657               reg_rdata_next[1] = clk_enables_clk_io_div2_peri_en_qs;
2658               reg_rdata_next[2] = clk_enables_clk_io_peri_en_qs;
2659               reg_rdata_next[3] = clk_enables_clk_usb_peri_en_qs;
2660             end
2661       
2662             addr_hit[7]: begin
2663               reg_rdata_next[0] = clk_hints_clk_main_aes_hint_qs;
                   ==>
2664               reg_rdata_next[1] = clk_hints_clk_main_hmac_hint_qs;
2665               reg_rdata_next[2] = clk_hints_clk_main_kmac_hint_qs;
2666               reg_rdata_next[3] = clk_hints_clk_main_otbn_hint_qs;
2667             end
2668       
2669             addr_hit[8]: begin
2670               reg_rdata_next[0] = clk_hints_status_clk_main_aes_val_qs;
                   ==>
2671               reg_rdata_next[1] = clk_hints_status_clk_main_hmac_val_qs;
2672               reg_rdata_next[2] = clk_hints_status_clk_main_kmac_val_qs;
2673               reg_rdata_next[3] = clk_hints_status_clk_main_otbn_val_qs;
2674             end
2675       
2676             addr_hit[9]: begin
2677               reg_rdata_next[0] = measure_ctrl_regwen_qs;
                   ==>
2678             end
2679       
2680             addr_hit[10]: begin
2681               reg_rdata_next = DW'(io_meas_ctrl_en_qs);
                   ==>
2682             end
2683             addr_hit[11]: begin
2684               reg_rdata_next = DW'(io_meas_ctrl_shadowed_qs);
                   ==>
2685             end
2686             addr_hit[12]: begin
2687               reg_rdata_next = DW'(io_div2_meas_ctrl_en_qs);
                   ==>
2688             end
2689             addr_hit[13]: begin
2690               reg_rdata_next = DW'(io_div2_meas_ctrl_shadowed_qs);
                   ==>
2691             end
2692             addr_hit[14]: begin
2693               reg_rdata_next = DW'(io_div4_meas_ctrl_en_qs);
                   ==>
2694             end
2695             addr_hit[15]: begin
2696               reg_rdata_next = DW'(io_div4_meas_ctrl_shadowed_qs);
                   ==>
2697             end
2698             addr_hit[16]: begin
2699               reg_rdata_next = DW'(main_meas_ctrl_en_qs);
                   ==>
2700             end
2701             addr_hit[17]: begin
2702               reg_rdata_next = DW'(main_meas_ctrl_shadowed_qs);
                   ==>
2703             end
2704             addr_hit[18]: begin
2705               reg_rdata_next = DW'(usb_meas_ctrl_en_qs);
                   ==>
2706             end
2707             addr_hit[19]: begin
2708               reg_rdata_next = DW'(usb_meas_ctrl_shadowed_qs);
                   ==>
2709             end
2710             addr_hit[20]: begin
2711               reg_rdata_next[0] = recov_err_code_shadow_update_err_qs;
                   ==>
2712               reg_rdata_next[1] = recov_err_code_io_measure_err_qs;
2713               reg_rdata_next[2] = recov_err_code_io_div2_measure_err_qs;
2714               reg_rdata_next[3] = recov_err_code_io_div4_measure_err_qs;
2715               reg_rdata_next[4] = recov_err_code_main_measure_err_qs;
2716               reg_rdata_next[5] = recov_err_code_usb_measure_err_qs;
2717               reg_rdata_next[6] = recov_err_code_io_timeout_err_qs;
2718               reg_rdata_next[7] = recov_err_code_io_div2_timeout_err_qs;
2719               reg_rdata_next[8] = recov_err_code_io_div4_timeout_err_qs;
2720               reg_rdata_next[9] = recov_err_code_main_timeout_err_qs;
2721               reg_rdata_next[10] = recov_err_code_usb_timeout_err_qs;
2722             end
2723       
2724             addr_hit[21]: begin
2725               reg_rdata_next[0] = fatal_err_code_reg_intg_qs;
                   ==>
2726               reg_rdata_next[1] = fatal_err_code_idle_cnt_qs;
2727               reg_rdata_next[2] = fatal_err_code_shadow_storage_err_qs;
2728             end
2729       
2730             default: begin
2731               reg_rdata_next = '1;
                   ==>

Branches:
-1-StatusTests
addr_hit[0] Covered T4,T5,T28
addr_hit[1] Covered T4,T5,T6
addr_hit[2] Covered T4,T5,T28
addr_hit[3] Covered T4,T28,T29
addr_hit[4] Covered T4,T28,T29
addr_hit[5] Covered T4,T28,T29
addr_hit[6] Covered T4,T6,T28
addr_hit[7] Covered T4,T5,T28
addr_hit[8] Covered T4,T5,T28
addr_hit[9] Covered T4,T28,T29
addr_hit[10] Covered T4,T5,T28
addr_hit[11] Covered T4,T5,T6
addr_hit[12] Covered T4,T28,T29
addr_hit[13] Covered T4,T5,T28
addr_hit[14] Covered T4,T5,T28
addr_hit[15] Covered T4,T28,T29
addr_hit[16] Covered T4,T6,T28
addr_hit[17] Covered T4,T5,T28
addr_hit[18] Covered T4,T28,T29
addr_hit[19] Covered T4,T6,T28
addr_hit[20] Covered T4,T5,T28
addr_hit[21] Covered T4,T5,T28
default Covered T4,T5,T6 



2741           if (!rst_ni) begin
               -1-  
2742             rst_done <= '0;
                 ==>
2743           end else begin
2744             rst_done <= 1'b1;
                 ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



2749           if (!rst_shadowed_ni) begin
               -1-  
2750             shadow_rst_done <= '0;
                 ==>
2751           end else begin
2752             shadow_rst_done <= 1'b1;
                 ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



2790           unique case (1'b1)
                      -1-  
2791             addr_hit[10]: begin
2792               reg_busy_sel = io_meas_ctrl_en_busy;
                   ==>
2793             end
2794             addr_hit[11]: begin
2795               reg_busy_sel = io_meas_ctrl_shadowed_busy;
                   ==>
2796             end
2797             addr_hit[12]: begin
2798               reg_busy_sel = io_div2_meas_ctrl_en_busy;
                   ==>
2799             end
2800             addr_hit[13]: begin
2801               reg_busy_sel = io_div2_meas_ctrl_shadowed_busy;
                   ==>
2802             end
2803             addr_hit[14]: begin
2804               reg_busy_sel = io_div4_meas_ctrl_en_busy;
                   ==>
2805             end
2806             addr_hit[15]: begin
2807               reg_busy_sel = io_div4_meas_ctrl_shadowed_busy;
                   ==>
2808             end
2809             addr_hit[16]: begin
2810               reg_busy_sel = main_meas_ctrl_en_busy;
                   ==>
2811             end
2812             addr_hit[17]: begin
2813               reg_busy_sel = main_meas_ctrl_shadowed_busy;
                   ==>
2814             end
2815             addr_hit[18]: begin
2816               reg_busy_sel = usb_meas_ctrl_en_busy;
                   ==>
2817             end
2818             addr_hit[19]: begin
2819               reg_busy_sel = usb_meas_ctrl_shadowed_busy;
                   ==>
2820             end
2821             default: begin
2822               reg_busy_sel  = '0;
                   ==>

Branches:
-1-StatusTests
addr_hit[10] Covered T4,T5,T29
addr_hit[11] Covered T4,T5,T6
addr_hit[12] Covered T4,T29,T30
addr_hit[13] Covered T4,T5,T29
addr_hit[14] Covered T4,T5,T29
addr_hit[15] Covered T4,T29,T30
addr_hit[16] Covered T4,T6,T29
addr_hit[17] Covered T4,T5,T29
addr_hit[18] Covered T4,T29,T30
addr_hit[19] Covered T4,T6,T29
default Covered T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
en2addrHit 172024014 823959 0 0
reAfterRv 172024014 823959 0 0
rePulse 172024014 180770 0 0
wePulse 172024014 643189 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 172024014 823959 0 0
T4 1267 22 0 0
T5 1229 19 0 0
T6 1446 5 0 0
T28 1362 0 0 0
T29 1501 49 0 0
T30 1454 28 0 0
T31 1340 8 0 0
T32 2243 70 0 0
T33 1756 61 0 0
T34 2129 49 0 0
T69 0 12 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 172024014 823959 0 0
T4 1267 22 0 0
T5 1229 19 0 0
T6 1446 5 0 0
T28 1362 0 0 0
T29 1501 49 0 0
T30 1454 28 0 0
T31 1340 8 0 0
T32 2243 70 0 0
T33 1756 61 0 0
T34 2129 49 0 0
T69 0 12 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 172024014 180770 0 0
T4 1267 13 0 0
T5 1229 6 0 0
T6 1446 0 0 0
T28 1362 0 0 0
T29 1501 28 0 0
T30 1454 9 0 0
T31 1340 3 0 0
T32 2243 40 0 0
T33 1756 20 0 0
T34 2129 16 0 0
T68 0 13 0 0
T104 0 6 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 172024014 643189 0 0
T4 1267 9 0 0
T5 1229 13 0 0
T6 1446 5 0 0
T28 1362 0 0 0
T29 1501 21 0 0
T30 1454 19 0 0
T31 1340 5 0 0
T32 2243 30 0 0
T33 1756 41 0 0
T34 2129 33 0 0
T69 0 12 0 0