Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

22                      
23         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T55,T20

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	171076067	168443173	0	0
AllClkBypReqTrue_A	171076067	141122	0	0
IoClkBypReqFalse_A	171076067	168353459	0	2415
IoClkBypReqTrue_A	171076067	226332	0	0
LcClkBypAckFalse_A	171076067	168451691	0	0
LcClkBypAckTrue_A	171076067	132604	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171076067	168443173	0	0
T4	1267	1162	0	0
T5	1229	1114	0	0
T6	1446	1376	0	0
T28	1362	1193	0	0
T29	1501	1477	0	0
T30	1454	1358	0	0
T31	1340	1092	0	0
T32	2243	2059	0	0
T33	1756	1652	0	0
T34	2129	1798	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171076067	141122	0	0
T5	1229	90	0	0
T6	1446	0	0	0
T19	0	346	0	0
T28	1362	0	0	0
T29	1501	0	0	0
T30	1454	0	0	0
T31	1340	35	0	0
T32	2243	0	0	0
T33	1756	72	0	0
T34	2129	190	0	0
T57	0	10	0	0
T58	0	129	0	0
T61	0	104	0	0
T62	0	206	0	0
T69	968	0	0	0
T104	0	108	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171076067	168353459	0	2415
T4	1267	1160	0	3
T5	1229	1079	0	3
T6	1446	1374	0	3
T28	1362	1191	0	3
T29	1501	1475	0	3
T30	1454	1197	0	3
T31	1340	1097	0	3
T32	2243	2057	0	3
T33	1756	1722	0	3
T34	2129	1758	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171076067	226332	0	0
T5	1229	123	0	0
T6	1446	0	0	0
T19	0	594	0	0
T23	0	47	0	0
T28	1362	0	0	0
T29	1501	0	0	0
T30	1454	159	0	0
T31	1340	28	0	0
T32	2243	0	0	0
T33	1756	0	0	0
T34	2129	228	0	0
T56	0	83	0	0
T58	0	160	0	0
T59	0	190	0	0
T69	968	0	0	0
T104	0	119	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171076067	168451691	0	0
T4	1267	1162	0	0
T5	1229	1127	0	0
T6	1446	1376	0	0
T28	1362	1193	0	0
T29	1501	1477	0	0
T30	1454	1289	0	0
T31	1340	1103	0	0
T32	2243	2059	0	0
T33	1756	1724	0	0
T34	2129	1841	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171076067	132604	0	0
T5	1229	77	0	0
T6	1446	0	0	0
T19	0	309	0	0
T28	1362	0	0	0
T29	1501	0	0	0
T30	1454	69	0	0
T31	1340	24	0	0
T32	2243	0	0	0
T33	1756	0	0	0
T34	2129	147	0	0
T56	0	73	0	0
T58	0	89	0	0
T59	0	91	0	0
T61	0	57	0	0
T69	968	0	0	0
T104	0	77	0	0