Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2023079500	15560	0	0
TransStop_A	2023079500	8016	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2023079500	15560	0	0
T4	6852	4	0	0
T5	32812	0	0	0
T6	5840	0	0	0
T21	0	4	0	0
T24	0	3	0	0
T28	5144	0	0	0
T29	25036	12	0	0
T30	12116	0	0	0
T31	5364	0	0	0
T32	8976	15	0	0
T33	28116	0	0	0
T34	8520	0	0	0
T43	0	13	0	0
T52	0	17	0	0
T54	0	7	0	0
T60	0	39	0	0
T65	0	4	0	0
T68	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2023079500	8016	0	0
T4	6852	4	0	0
T5	32812	0	0	0
T6	5840	0	0	0
T21	0	4	0	0
T28	5144	0	0	0
T29	25036	5	0	0
T30	12116	0	0	0
T31	5364	0	0	0
T32	8976	11	0	0
T33	28116	0	0	0
T34	8520	0	0	0
T43	0	15	0	0
T52	0	5	0	0
T54	0	3	0	0
T60	0	20	0	0
T65	0	4	0	0
T68	0	4	0	0
T136	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	505769875	3941	0	0
TransStop_A	505769875	2023	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505769875	3941	0	0
T4	1713	1	0	0
T5	8203	0	0	0
T6	1460	0	0	0
T21	0	1	0	0
T28	1286	0	0	0
T29	6259	2	0	0
T30	3029	0	0	0
T31	1341	0	0	0
T32	2244	3	0	0
T33	7029	0	0	0
T34	2130	0	0	0
T43	0	13	0	0
T52	0	4	0	0
T54	0	2	0	0
T60	0	8	0	0
T65	0	1	0	0
T68	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505769875	2023	0	0
T4	1713	1	0	0
T5	8203	0	0	0
T6	1460	0	0	0
T21	0	1	0	0
T28	1286	0	0	0
T29	6259	1	0	0
T30	3029	0	0	0
T31	1341	0	0	0
T32	2244	2	0	0
T33	7029	0	0	0
T34	2130	0	0	0
T43	0	4	0	0
T52	0	1	0	0
T54	0	1	0	0
T60	0	3	0	0
T65	0	1	0	0
T68	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	505769875	3849	0	0
TransStop_A	505769875	1979	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505769875	3849	0	0
T4	1713	1	0	0
T5	8203	0	0	0
T6	1460	0	0	0
T21	0	1	0	0
T24	0	1	0	0
T28	1286	0	0	0
T29	6259	4	0	0
T30	3029	0	0	0
T31	1341	0	0	0
T32	2244	5	0	0
T33	7029	0	0	0
T34	2130	0	0	0
T52	0	5	0	0
T54	0	1	0	0
T60	0	13	0	0
T65	0	1	0	0
T68	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505769875	1979	0	0
T4	1713	1	0	0
T5	8203	0	0	0
T6	1460	0	0	0
T21	0	1	0	0
T28	1286	0	0	0
T29	6259	1	0	0
T30	3029	0	0	0
T31	1341	0	0	0
T32	2244	3	0	0
T33	7029	0	0	0
T34	2130	0	0	0
T43	0	3	0	0
T52	0	2	0	0
T54	0	1	0	0
T60	0	8	0	0
T65	0	1	0	0
T68	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	505769875	3938	0	0
TransStop_A	505769875	2029	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505769875	3938	0	0
T4	1713	1	0	0
T5	8203	0	0	0
T6	1460	0	0	0
T21	0	1	0	0
T24	0	1	0	0
T28	1286	0	0	0
T29	6259	2	0	0
T30	3029	0	0	0
T31	1341	0	0	0
T32	2244	3	0	0
T33	7029	0	0	0
T34	2130	0	0	0
T52	0	3	0	0
T54	0	2	0	0
T60	0	9	0	0
T65	0	1	0	0
T68	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505769875	2029	0	0
T4	1713	1	0	0
T5	8203	0	0	0
T6	1460	0	0	0
T21	0	1	0	0
T28	1286	0	0	0
T29	6259	1	0	0
T30	3029	0	0	0
T31	1341	0	0	0
T32	2244	2	0	0
T33	7029	0	0	0
T34	2130	0	0	0
T43	0	4	0	0
T52	0	1	0	0
T54	0	1	0	0
T60	0	5	0	0
T65	0	1	0	0
T68	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	505769875	3832	0	0
TransStop_A	505769875	1985	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505769875	3832	0	0
T4	1713	1	0	0
T5	8203	0	0	0
T6	1460	0	0	0
T21	0	1	0	0
T24	0	1	0	0
T28	1286	0	0	0
T29	6259	4	0	0
T30	3029	0	0	0
T31	1341	0	0	0
T32	2244	4	0	0
T33	7029	0	0	0
T34	2130	0	0	0
T52	0	5	0	0
T54	0	2	0	0
T60	0	9	0	0
T65	0	1	0	0
T68	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505769875	1985	0	0
T4	1713	1	0	0
T5	8203	0	0	0
T6	1460	0	0	0
T21	0	1	0	0
T28	1286	0	0	0
T29	6259	2	0	0
T30	3029	0	0	0
T31	1341	0	0	0
T32	2244	4	0	0
T33	7029	0	0	0
T34	2130	0	0	0
T43	0	4	0	0
T52	0	1	0	0
T60	0	4	0	0
T65	0	1	0	0
T68	0	1	0	0
T136	0	1	0	0