Unified Coverage Report :: Module :: prim_generic_xor2

Module : prim_generic_xor2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_xor2_0/rtl/prim_generic_xor2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.u_mubi_xor.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.u_mubi_xor.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.u_mubi_xor.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.u_mubi_xor.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.u_mubi_xor.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.u_mubi_xor.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.u_mubi_xor.gen_generic.u_impl_generic	100.00	100.00

---

Module Instance : tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.u_mubi_xor.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.gen_stable_chks.u_mubi_xor

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.u_mubi_xor.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.gen_stable_chks.u_mubi_xor

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.u_mubi_xor.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.gen_stable_chks.u_mubi_xor

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.u_mubi_xor.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.gen_stable_chks.u_mubi_xor

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.u_mubi_xor.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.gen_stable_chks.u_mubi_xor

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.u_mubi_xor.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.gen_stable_chks.u_mubi_xor

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.u_mubi_xor.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_flops.gen_stable_chks.u_mubi_xor

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_xor2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	15	1	1	100.00

14                      
15         1/1            assign out_o = in0_i ^ in1_i;
           Tests:       T4 T5 T6 

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.u_mubi_xor.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	15	1	1	100.00

14                      
15         1/1            assign out_o = in0_i ^ in1_i;
           Tests:       T5 T30 T31 

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.u_mubi_xor.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	15	1	1	100.00

14                      
15         1/1            assign out_o = in0_i ^ in1_i;
           Tests:       T5 T30 T31 

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.u_mubi_xor.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	15	1	1	100.00

14                      
15         1/1            assign out_o = in0_i ^ in1_i;
           Tests:       T5 T30 T31 

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.u_mubi_xor.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	15	1	1	100.00

14                      
15         1/1            assign out_o = in0_i ^ in1_i;
           Tests:       T4 T5 T6 

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.u_mubi_xor.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	15	1	1	100.00

14                      
15         1/1            assign out_o = in0_i ^ in1_i;
           Tests:       T4 T5 T6 

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.u_mubi_xor.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	15	1	1	100.00

14                      
15         1/1            assign out_o = in0_i ^ in1_i;
           Tests:       T4 T5 T6 

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.u_mubi_xor.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	15	1	1	100.00

14                      
15         1/1            assign out_o = in0_i ^ in1_i;
           Tests:       T4 T5 T6