Unified Coverage Report :: Module :: prim_edge_detector

Module : prim_edge_detector

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_io_meas.u_timeout_err_sync	100.00	100.00	100.00			100.00
tb.dut.u_io_div2_meas.u_timeout_err_sync	100.00	100.00	100.00			100.00
tb.dut.u_io_div4_meas.u_timeout_err_sync	100.00	100.00	100.00			100.00
tb.dut.u_main_meas.u_timeout_err_sync	100.00	100.00	100.00			100.00
tb.dut.u_usb_meas.u_timeout_err_sync	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_io_meas.u_timeout_err_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_sync.u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_div2_meas.u_timeout_err_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_div2_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_sync.u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_div4_meas.u_timeout_err_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_div4_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_sync.u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_main_meas.u_timeout_err_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_main_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_sync.u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_usb_meas.u_timeout_err_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_usb_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_sync.u_sync	100.00	100.00				100.00

Line Coverage for Module : prim_edge_detector

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	45	1	1	100.00
ALWAYS	48	3	3	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00

44                      
45         1/1            assign q_sync_o = q_sync_d;
           Tests:       T1 T45 T46 
46                      
47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         2/2              if (!rst_ni) q_sync_q <= ResetValue;
           Tests:       T4 T5 T6  | T4 T5 T6 
49         1/1              else         q_sync_q <= q_sync_d;
           Tests:       T4 T5 T6 
50                        end
51                      
52         1/1            assign q_posedge_pulse_o = q_sync_d & ~q_sync_q;
           Tests:       T1 T45 T46 
53         1/1            assign q_negedge_pulse_o = ~q_sync_d & q_sync_q;
           Tests:       T1 T45 T46 

---

Cond Coverage for Module : prim_edge_detector

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T45,T46
1	1	Covered	T1,T45,T46

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T45,T46
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T45,T46

---

Branch Coverage for Module : prim_edge_detector

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	48	2	2	100.00

48             if (!rst_ni) q_sync_q <= ResetValue;
               -1-  
               ==>
49             else         q_sync_q <= q_sync_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_io_meas.u_timeout_err_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	45	1	1	100.00
ALWAYS	48	3	3	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00

44                      
45         1/1            assign q_sync_o = q_sync_d;
           Tests:       T1 T45 T51 
46                      
47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         2/2              if (!rst_ni) q_sync_q <= ResetValue;
           Tests:       T4 T5 T6  | T4 T5 T6 
49         1/1              else         q_sync_q <= q_sync_d;
           Tests:       T4 T5 T6 
50                        end
51                      
52         1/1            assign q_posedge_pulse_o = q_sync_d & ~q_sync_q;
           Tests:       T1 T45 T51 
53         1/1            assign q_negedge_pulse_o = ~q_sync_d & q_sync_q;
           Tests:       T1 T45 T51 

---

Cond Coverage for Instance : tb.dut.u_io_meas.u_timeout_err_sync

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T45,T51
1	1	Covered	T1,T45,T51

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T45,T51
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T45,T51

---

Branch Coverage for Instance : tb.dut.u_io_meas.u_timeout_err_sync

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	48	2	2	100.00

48             if (!rst_ni) q_sync_q <= ResetValue;
               -1-  
               ==>
49             else         q_sync_q <= q_sync_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_timeout_err_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	45	1	1	100.00
ALWAYS	48	3	3	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00

44                      
45         1/1            assign q_sync_o = q_sync_d;
           Tests:       T1 T45 T51 
46                      
47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         2/2              if (!rst_ni) q_sync_q <= ResetValue;
           Tests:       T4 T5 T6  | T4 T5 T6 
49         1/1              else         q_sync_q <= q_sync_d;
           Tests:       T4 T5 T6 
50                        end
51                      
52         1/1            assign q_posedge_pulse_o = q_sync_d & ~q_sync_q;
           Tests:       T1 T45 T51 
53         1/1            assign q_negedge_pulse_o = ~q_sync_d & q_sync_q;
           Tests:       T1 T45 T51 

---

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_timeout_err_sync

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T45,T51
1	1	Covered	T1,T45,T51

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T45,T51
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T45,T51

---

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_timeout_err_sync

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	48	2	2	100.00

48             if (!rst_ni) q_sync_q <= ResetValue;
               -1-  
               ==>
49             else         q_sync_q <= q_sync_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_timeout_err_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	45	1	1	100.00
ALWAYS	48	3	3	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00

44                      
45         1/1            assign q_sync_o = q_sync_d;
           Tests:       T1 T45 T51 
46                      
47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         2/2              if (!rst_ni) q_sync_q <= ResetValue;
           Tests:       T4 T5 T6  | T4 T5 T6 
49         1/1              else         q_sync_q <= q_sync_d;
           Tests:       T4 T5 T6 
50                        end
51                      
52         1/1            assign q_posedge_pulse_o = q_sync_d & ~q_sync_q;
           Tests:       T1 T45 T51 
53         1/1            assign q_negedge_pulse_o = ~q_sync_d & q_sync_q;
           Tests:       T1 T45 T51 

---

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_timeout_err_sync

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T45,T51
1	1	Covered	T1,T45,T51

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T45,T51
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T45,T51

---

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_timeout_err_sync

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	48	2	2	100.00

48             if (!rst_ni) q_sync_q <= ResetValue;
               -1-  
               ==>
49             else         q_sync_q <= q_sync_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_main_meas.u_timeout_err_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	45	1	1	100.00
ALWAYS	48	3	3	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00

44                      
45         1/1            assign q_sync_o = q_sync_d;
           Tests:       T45 T46 T51 
46                      
47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         2/2              if (!rst_ni) q_sync_q <= ResetValue;
           Tests:       T4 T5 T6  | T4 T5 T6 
49         1/1              else         q_sync_q <= q_sync_d;
           Tests:       T4 T5 T6 
50                        end
51                      
52         1/1            assign q_posedge_pulse_o = q_sync_d & ~q_sync_q;
           Tests:       T45 T46 T51 
53         1/1            assign q_negedge_pulse_o = ~q_sync_d & q_sync_q;
           Tests:       T45 T46 T51 

---

Cond Coverage for Instance : tb.dut.u_main_meas.u_timeout_err_sync

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T45,T46,T51
1	1	Covered	T45,T46,T51

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T45,T46,T51
1	0	Covered	T4,T5,T6
1	1	Covered	T45,T46,T51

---

Branch Coverage for Instance : tb.dut.u_main_meas.u_timeout_err_sync

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	48	2	2	100.00

48             if (!rst_ni) q_sync_q <= ResetValue;
               -1-  
               ==>
49             else         q_sync_q <= q_sync_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_usb_meas.u_timeout_err_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	45	1	1	100.00
ALWAYS	48	3	3	100.00
CONT_ASSIGN	52	1	1	100.00
CONT_ASSIGN	53	1	1	100.00

44                      
45         1/1            assign q_sync_o = q_sync_d;
           Tests:       T1 T45 T51 
46                      
47                        always_ff @(posedge clk_i or negedge rst_ni) begin
48         2/2              if (!rst_ni) q_sync_q <= ResetValue;
           Tests:       T4 T5 T6  | T4 T5 T6 
49         1/1              else         q_sync_q <= q_sync_d;
           Tests:       T4 T5 T6 
50                        end
51                      
52         1/1            assign q_posedge_pulse_o = q_sync_d & ~q_sync_q;
           Tests:       T1 T45 T51 
53         1/1            assign q_negedge_pulse_o = ~q_sync_d & q_sync_q;
           Tests:       T1 T45 T51 

---

Cond Coverage for Instance : tb.dut.u_usb_meas.u_timeout_err_sync

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T45,T51
1	1	Covered	T1,T45,T51

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T45,T51
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T45,T51

---

Branch Coverage for Instance : tb.dut.u_usb_meas.u_timeout_err_sync

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	48	2	2	100.00

48             if (!rst_ni) q_sync_q <= ResetValue;
               -1-  
               ==>
49             else         q_sync_q <= q_sync_d;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6