Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	171076067	18291599	0	64

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171076067	18291599	0	64
T2	36827	15077	0	1
T3	9450	0	0	0
T9	0	2432	0	1
T10	0	25687	0	1
T12	0	12853	0	1
T13	0	25178	0	0
T14	0	4569	0	0
T15	0	12445	0	0
T16	0	6782	0	1
T17	0	2848	0	1
T19	2995	0	0	0
T20	15327	0	0	0
T21	673	0	0	0
T22	821	0	0	0
T23	890	0	0	0
T24	1457	0	0	0
T25	2051	0	0	0
T26	1387	0	0	0
T35	0	0	0	1
T36	0	0	0	1
T39	0	850	0	1
T41	0	0	0	1