Unified Coverage Report :: Module

Module : prim_generic_buf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_step_down_req_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_step_down_req_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_step_down_req_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_step_down_req_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div2_div_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div2_div_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div2_div_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div2_div_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div4_div_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div4_div_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div4_div_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div4_div_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_reg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_io_byp_req.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_all_byp_req.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[4].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[4].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[4].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[4].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[5].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[5].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[5].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_calib_rdy_sync.gen_buffs[5].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_main_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_main_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_main_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_main_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_usb_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_io_peri_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_io_peri_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_io_peri_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_io_peri_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_usb_peri_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_usb_peri_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_usb_peri_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_usb_peri_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_aes_trans.u_prim_buf_en.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_hmac_trans.u_prim_buf_en.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_kmac_trans.u_prim_buf_en.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic	100.00	100.00
tb.dut.u_clk_main_otbn_trans.u_prim_buf_en.gen_generic.u_impl_generic	100.00	100.00

Module Instance : tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_step_down_req_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_step_down_req_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_step_down_req_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_step_down_req_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div2_div_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div2_div_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div2_div_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div2_div_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div4_div_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div4_div_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div4_div_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div4_div_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_io_byp_req.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_all_byp_req.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[1].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[2].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[3].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[4].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[4].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[4].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[4].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[4].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[4].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[4].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[4].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[5].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[5].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[5].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[5].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[5].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[5].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_calib_rdy_sync.gen_buffs[5].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[5].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_main_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_main_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_main_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_main_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_usb_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_usb_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_usb_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_usb_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_io_peri_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_io_peri_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_io_peri_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_io_peri_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_usb_peri_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_usb_peri_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_usb_peri_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_usb_peri_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_aes_trans.u_prim_buf_en.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_buf_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_hmac_trans.u_prim_buf_en.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_buf_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_kmac_trans.u_prim_buf_en.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_buf_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_secure_anchor_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[0].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[1].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[2].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_buffs[0].gen_bits[3].u_prim_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_clk_main_otbn_trans.u_prim_buf_en.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_buf_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_buf

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T32 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T32

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T32 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T32

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T32 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T32

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T32 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T32

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T32 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T32

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T32 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T32

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T32 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T32

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T32 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T32

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T32 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T32

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T32 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T32

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T32 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T32

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T30 T31 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T30 T31

Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[4].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[4].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[4].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[4].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[5].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[5].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[5].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_calib_rdy_sync.gen_buffs[5].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_buf_en.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_buf_en.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_buf_en.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T5 T6 T28 
16         1/1            assign out_o = ~inv;
           Tests:       T5 T6 T28

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_buf_en.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	15	1	1	100.00
CONT_ASSIGN	16	1	1	100.00



14                        logic [Width-1:0] inv;
15         1/1            assign inv = ~in_i;
           Tests:       T4 T5 T6 
16         1/1            assign out_o = ~inv;
           Tests:       T4 T5 T6