Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	172024014	5665498	0	0
clk_enables_rd_A	172024014	38429	0	0
clk_hints_rd_A	172024014	34097	0	0
extclk_ctrl_rd_A	172024014	42350	0	0
extclk_ctrl_regwen_rd_A	172024014	32743	0	0
jitter_enable_rd_A	172024014	34059	0	0
jitter_regwen_rd_A	172024014	35644	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172024014	5665498	0	0
T72	0	101652	0	0
T73	100954	34888	0	0
T74	0	41732	0	0
T75	0	40637	0	0
T89	0	100756	0	0
T90	0	52375	0	0
T91	0	49886	0	0
T92	0	63823	0	0
T93	0	62171	0	0
T94	0	110657	0	0
T95	1953	0	0	0
T96	1061	0	0	0
T97	1066	0	0	0
T98	2036	0	0	0
T99	53465	0	0	0
T100	2695	0	0	0
T101	2188	0	0	0
T102	1514	0	0	0
T103	534	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172024014	38429	0	0
T12	31868	0	0	0
T66	58532	0	0	0
T74	0	1693	0	0
T136	1122	2	0	0
T151	0	5	0	0
T152	0	4	0	0
T153	0	1	0	0
T154	0	19	0	0
T155	0	11	0	0
T156	0	4	0	0
T157	0	8	0	0
T158	0	2	0	0
T159	1088	0	0	0
T160	2793	0	0	0
T161	1566	0	0	0
T162	1116	0	0	0
T163	2019	0	0	0
T164	1083	0	0	0
T165	1303	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172024014	34097	0	0
T1	11360	0	0	0
T51	1708	0	0	0
T52	2146	0	0	0
T53	1103	0	0	0
T54	1294	0	0	0
T55	15841	0	0	0
T56	1421	0	0	0
T57	1110	0	0	0
T68	1441	2	0	0
T74	0	1520	0	0
T104	1571	0	0	0
T136	0	2	0	0
T152	0	2	0	0
T154	0	13	0	0
T155	0	1	0	0
T156	0	3	0	0
T157	0	4	0	0
T158	0	7	0	0
T166	0	3	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172024014	42350	0	0
T1	11360	23	0	0
T2	36827	0	0	0
T19	0	37	0	0
T27	0	68	0	0
T51	1708	0	0	0
T52	2146	0	0	0
T53	1103	0	0	0
T54	1294	0	0	0
T55	15841	0	0	0
T56	1421	0	0	0
T57	1110	0	0	0
T58	1594	0	0	0
T167	0	50	0	0
T168	0	79	0	0
T169	0	42	0	0
T170	0	8	0	0
T171	0	13	0	0
T172	0	90	0	0
T173	0	31	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172024014	32743	0	0
T1	11360	16	0	0
T2	36827	0	0	0
T27	0	28	0	0
T51	1708	0	0	0
T52	2146	0	0	0
T53	1103	0	0	0
T54	1294	0	0	0
T55	15841	0	0	0
T56	1421	0	0	0
T57	1110	0	0	0
T58	1594	0	0	0
T74	0	1506	0	0
T134	0	26	0	0
T167	0	28	0	0
T172	0	57	0	0
T174	0	28	0	0
T175	0	40	0	0
T176	0	41	0	0
T177	0	53	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172024014	34059	0	0
T1	11360	40	0	0
T27	0	48	0	0
T51	1708	0	0	0
T52	2146	0	0	0
T53	1103	0	0	0
T54	1294	0	0	0
T55	15841	0	0	0
T56	1421	0	0	0
T57	1110	0	0	0
T68	1441	2	0	0
T104	1571	0	0	0
T136	0	15	0	0
T151	0	12	0	0
T152	0	16	0	0
T153	0	8	0	0
T154	0	18	0	0
T167	0	37	0	0
T172	0	83	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172024014	35644	0	0
T74	140167	1769	0	0
T90	0	936	0	0
T119	2260	0	0	0
T155	176478	0	0	0
T156	927	0	0	0
T178	0	4174	0	0
T179	0	855	0	0
T180	0	2052	0	0
T181	0	503	0	0
T182	0	3544	0	0
T183	0	2609	0	0
T184	0	6031	0	0
T185	0	4609	0	0
T186	2720	0	0	0
T187	176105	0	0	0
T188	1072	0	0	0
T189	1952	0	0	0
T190	2115	0	0	0
T191	1536	0	0	0