Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	513228201	366	0	0
StatusRise_A	513228201	366	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513228201	366	0	0
T26	0	10	0	0
T28	4086	9	0	0
T29	4503	0	0	0
T30	4362	0	0	0
T31	4020	0	0	0
T32	6729	0	0	0
T33	5268	0	0	0
T34	6387	0	0	0
T44	0	15	0	0
T53	0	1	0	0
T68	4323	0	0	0
T69	2904	0	0	0
T104	4713	0	0	0
T161	0	5	0	0
T192	0	7	0	0
T193	0	3	0	0
T194	0	14	0	0
T195	0	9	0	0
T196	0	4	0	0
T197	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513228201	366	0	0
T26	0	10	0	0
T28	4086	9	0	0
T29	4503	0	0	0
T30	4362	0	0	0
T31	4020	0	0	0
T32	6729	0	0	0
T33	5268	0	0	0
T34	6387	0	0	0
T44	0	15	0	0
T53	0	1	0	0
T68	4323	0	0	0
T69	2904	0	0	0
T104	4713	0	0	0
T161	0	5	0	0
T192	0	7	0	0
T193	0	3	0	0
T194	0	14	0	0
T195	0	9	0	0
T196	0	4	0	0
T197	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	171076067	124	0	0
StatusRise_A	171076067	124	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171076067	124	0	0
T26	0	4	0	0
T28	1362	3	0	0
T29	1501	0	0	0
T30	1454	0	0	0
T31	1340	0	0	0
T32	2243	0	0	0
T33	1756	0	0	0
T34	2129	0	0	0
T44	0	4	0	0
T68	1441	0	0	0
T69	968	0	0	0
T104	1571	0	0	0
T161	0	1	0	0
T192	0	2	0	0
T193	0	1	0	0
T194	0	5	0	0
T195	0	3	0	0
T196	0	1	0	0
T197	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171076067	124	0	0
T26	0	4	0	0
T28	1362	3	0	0
T29	1501	0	0	0
T30	1454	0	0	0
T31	1340	0	0	0
T32	2243	0	0	0
T33	1756	0	0	0
T34	2129	0	0	0
T44	0	4	0	0
T68	1441	0	0	0
T69	968	0	0	0
T104	1571	0	0	0
T161	0	1	0	0
T192	0	2	0	0
T193	0	1	0	0
T194	0	5	0	0
T195	0	3	0	0
T196	0	1	0	0
T197	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	171076067	129	0	0
StatusRise_A	171076067	129	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171076067	129	0	0
T26	0	3	0	0
T28	1362	4	0	0
T29	1501	0	0	0
T30	1454	0	0	0
T31	1340	0	0	0
T32	2243	0	0	0
T33	1756	0	0	0
T34	2129	0	0	0
T44	0	6	0	0
T53	0	1	0	0
T68	1441	0	0	0
T69	968	0	0	0
T104	1571	0	0	0
T161	0	2	0	0
T192	0	3	0	0
T193	0	1	0	0
T194	0	4	0	0
T195	0	4	0	0
T196	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171076067	129	0	0
T26	0	3	0	0
T28	1362	4	0	0
T29	1501	0	0	0
T30	1454	0	0	0
T31	1340	0	0	0
T32	2243	0	0	0
T33	1756	0	0	0
T34	2129	0	0	0
T44	0	6	0	0
T53	0	1	0	0
T68	1441	0	0	0
T69	968	0	0	0
T104	1571	0	0	0
T161	0	2	0	0
T192	0	3	0	0
T193	0	1	0	0
T194	0	4	0	0
T195	0	4	0	0
T196	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	171076067	113	0	0
StatusRise_A	171076067	113	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171076067	113	0	0
T26	0	3	0	0
T28	1362	2	0	0
T29	1501	0	0	0
T30	1454	0	0	0
T31	1340	0	0	0
T32	2243	0	0	0
T33	1756	0	0	0
T34	2129	0	0	0
T44	0	5	0	0
T68	1441	0	0	0
T69	968	0	0	0
T104	1571	0	0	0
T161	0	2	0	0
T192	0	2	0	0
T193	0	1	0	0
T194	0	5	0	0
T195	0	2	0	0
T196	0	2	0	0
T197	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	171076067	113	0	0
T26	0	3	0	0
T28	1362	2	0	0
T29	1501	0	0	0
T30	1454	0	0	0
T31	1340	0	0	0
T32	2243	0	0	0
T33	1756	0	0	0
T34	2129	0	0	0
T44	0	5	0	0
T68	1441	0	0	0
T69	968	0	0	0
T104	1571	0	0	0
T161	0	2	0	0
T192	0	2	0	0
T193	0	1	0	0
T194	0	5	0	0
T195	0	2	0	0
T196	0	2	0	0
T197	0	1	0	0