Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T53
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	48993	0	0
CgEnOn_A	2147483647	39985	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48993	0	0
T4	10533	7	0	0
T5	54889	3	0	0
T6	8962	7	0	0
T26	0	19	0	0
T28	13812	38	0	0
T29	67464	5	0	0
T30	32760	3	0	0
T31	14286	3	0	0
T32	24070	6	0	0
T33	76146	3	0	0
T34	23250	3	0	0
T44	0	30	0	0
T52	0	4	0	0
T53	0	5	0	0
T68	6519	1	0	0
T69	37359	0	0	0
T104	7656	0	0	0
T161	0	10	0	0
T192	0	15	0	0
T193	0	5	0	0
T194	0	20	0	0
T195	0	20	0	0
T196	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39985	0	0
T4	10533	4	0	0
T5	54889	0	0	0
T6	8962	4	0	0
T21	0	4	0	0
T25	0	37	0	0
T26	0	28	0	0
T28	13812	35	0	0
T29	67464	2	0	0
T30	32760	0	0	0
T31	14286	0	0	0
T32	24070	3	0	0
T33	76146	0	0	0
T34	23250	0	0	0
T44	0	30	0	0
T51	0	47	0	0
T52	0	4	0	0
T53	0	8	0	0
T54	0	2	0	0
T65	0	3	0	0
T68	6519	4	0	0
T69	37359	0	0	0
T104	7656	0	0	0
T161	0	10	0	0
T192	0	15	0	0
T193	0	5	0	0
T194	0	20	0	0
T195	0	20	0	0
T196	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T53
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	236710199	140	0	0
CgEnOn_A	236710199	140	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236710199	140	0	0
T26	0	3	0	0
T28	593	4	0	0
T29	2971	0	0	0
T30	1466	0	0	0
T31	598	0	0	0
T32	1037	0	0	0
T33	3435	0	0	0
T34	1088	0	0	0
T44	0	6	0	0
T53	0	1	0	0
T68	625	0	0	0
T69	3851	0	0	0
T104	810	0	0	0
T161	0	2	0	0
T192	0	3	0	0
T193	0	1	0	0
T194	0	4	0	0
T195	0	4	0	0
T196	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236710199	140	0	0
T26	0	3	0	0
T28	593	4	0	0
T29	2971	0	0	0
T30	1466	0	0	0
T31	598	0	0	0
T32	1037	0	0	0
T33	3435	0	0	0
T34	1088	0	0	0
T44	0	6	0	0
T53	0	1	0	0
T68	625	0	0	0
T69	3851	0	0	0
T104	810	0	0	0
T161	0	2	0	0
T192	0	3	0	0
T193	0	1	0	0
T194	0	4	0	0
T195	0	4	0	0
T196	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T53
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	118354443	140	0	0
CgEnOn_A	118354443	140	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118354443	140	0	0
T26	0	3	0	0
T28	296	4	0	0
T29	1486	0	0	0
T30	733	0	0	0
T31	298	0	0	0
T32	519	0	0	0
T33	1717	0	0	0
T34	542	0	0	0
T44	0	6	0	0
T53	0	1	0	0
T68	312	0	0	0
T69	1925	0	0	0
T104	405	0	0	0
T161	0	2	0	0
T192	0	3	0	0
T193	0	1	0	0
T194	0	4	0	0
T195	0	4	0	0
T196	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118354443	140	0	0
T26	0	3	0	0
T28	296	4	0	0
T29	1486	0	0	0
T30	733	0	0	0
T31	298	0	0	0
T32	519	0	0	0
T33	1717	0	0	0
T34	542	0	0	0
T44	0	6	0	0
T53	0	1	0	0
T68	312	0	0	0
T69	1925	0	0	0
T104	405	0	0	0
T161	0	2	0	0
T192	0	3	0	0
T193	0	1	0	0
T194	0	4	0	0
T195	0	4	0	0
T196	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T53
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	118354443	140	0	0
CgEnOn_A	118354443	140	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118354443	140	0	0
T26	0	3	0	0
T28	296	4	0	0
T29	1486	0	0	0
T30	733	0	0	0
T31	298	0	0	0
T32	519	0	0	0
T33	1717	0	0	0
T34	542	0	0	0
T44	0	6	0	0
T53	0	1	0	0
T68	312	0	0	0
T69	1925	0	0	0
T104	405	0	0	0
T161	0	2	0	0
T192	0	3	0	0
T193	0	1	0	0
T194	0	4	0	0
T195	0	4	0	0
T196	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118354443	140	0	0
T26	0	3	0	0
T28	296	4	0	0
T29	1486	0	0	0
T30	733	0	0	0
T31	298	0	0	0
T32	519	0	0	0
T33	1717	0	0	0
T34	542	0	0	0
T44	0	6	0	0
T53	0	1	0	0
T68	312	0	0	0
T69	1925	0	0	0
T104	405	0	0	0
T161	0	2	0	0
T192	0	3	0	0
T193	0	1	0	0
T194	0	4	0	0
T195	0	4	0	0
T196	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T53
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	118354443	140	0	0
CgEnOn_A	118354443	140	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118354443	140	0	0
T26	0	3	0	0
T28	296	4	0	0
T29	1486	0	0	0
T30	733	0	0	0
T31	298	0	0	0
T32	519	0	0	0
T33	1717	0	0	0
T34	542	0	0	0
T44	0	6	0	0
T53	0	1	0	0
T68	312	0	0	0
T69	1925	0	0	0
T104	405	0	0	0
T161	0	2	0	0
T192	0	3	0	0
T193	0	1	0	0
T194	0	4	0	0
T195	0	4	0	0
T196	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118354443	140	0	0
T26	0	3	0	0
T28	296	4	0	0
T29	1486	0	0	0
T30	733	0	0	0
T31	298	0	0	0
T32	519	0	0	0
T33	1717	0	0	0
T34	542	0	0	0
T44	0	6	0	0
T53	0	1	0	0
T68	312	0	0	0
T69	1925	0	0	0
T104	405	0	0	0
T161	0	2	0	0
T192	0	3	0	0
T193	0	1	0	0
T194	0	4	0	0
T195	0	4	0	0
T196	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T53
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	474934572	140	0	0
CgEnOn_A	474934572	133	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474934572	140	0	0
T26	0	3	0	0
T28	1238	4	0	0
T29	6008	0	0	0
T30	2907	0	0	0
T31	1286	0	0	0
T32	2154	0	0	0
T33	6747	0	0	0
T34	2044	0	0	0
T44	0	6	0	0
T53	0	1	0	0
T68	1384	0	0	0
T69	7739	0	0	0
T104	1571	0	0	0
T161	0	2	0	0
T192	0	3	0	0
T193	0	1	0	0
T194	0	4	0	0
T195	0	4	0	0
T196	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474934572	133	0	0
T26	0	3	0	0
T28	1238	4	0	0
T29	6008	0	0	0
T30	2907	0	0	0
T31	1286	0	0	0
T32	2154	0	0	0
T33	6747	0	0	0
T34	2044	0	0	0
T44	0	6	0	0
T53	0	1	0	0
T68	1384	0	0	0
T69	7739	0	0	0
T104	1571	0	0	0
T161	0	2	0	0
T192	0	3	0	0
T193	0	1	0	0
T194	0	4	0	0
T195	0	4	0	0
T196	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T55
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	505769449	128	0	0
CgEnOn_A	505769449	125	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505769449	128	0	0
T26	0	4	0	0
T28	1285	3	0	0
T29	6259	0	0	0
T30	3029	0	0	0
T31	1340	0	0	0
T32	2243	0	0	0
T33	7028	0	0	0
T34	2129	0	0	0
T44	0	4	0	0
T68	1441	0	0	0
T69	8062	0	0	0
T104	1637	0	0	0
T161	0	1	0	0
T192	0	2	0	0
T193	0	1	0	0
T194	0	5	0	0
T195	0	3	0	0
T196	0	1	0	0
T197	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505769449	125	0	0
T26	0	4	0	0
T28	1285	3	0	0
T29	6259	0	0	0
T30	3029	0	0	0
T31	1340	0	0	0
T32	2243	0	0	0
T33	7028	0	0	0
T34	2129	0	0	0
T44	0	4	0	0
T68	1441	0	0	0
T69	8062	0	0	0
T104	1637	0	0	0
T161	0	1	0	0
T192	0	2	0	0
T193	0	1	0	0
T194	0	5	0	0
T195	0	3	0	0
T196	0	1	0	0
T197	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T55
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	505769449	128	0	0
CgEnOn_A	505769449	125	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505769449	128	0	0
T26	0	4	0	0
T28	1285	3	0	0
T29	6259	0	0	0
T30	3029	0	0	0
T31	1340	0	0	0
T32	2243	0	0	0
T33	7028	0	0	0
T34	2129	0	0	0
T44	0	4	0	0
T68	1441	0	0	0
T69	8062	0	0	0
T104	1637	0	0	0
T161	0	1	0	0
T192	0	2	0	0
T193	0	1	0	0
T194	0	5	0	0
T195	0	3	0	0
T196	0	1	0	0
T197	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505769449	125	0	0
T26	0	4	0	0
T28	1285	3	0	0
T29	6259	0	0	0
T30	3029	0	0	0
T31	1340	0	0	0
T32	2243	0	0	0
T33	7028	0	0	0
T34	2129	0	0	0
T44	0	4	0	0
T68	1441	0	0	0
T69	8062	0	0	0
T104	1637	0	0	0
T161	0	1	0	0
T192	0	2	0	0
T193	0	1	0	0
T194	0	5	0	0
T195	0	3	0	0
T196	0	1	0	0
T197	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T55
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	242647424	114	0	0
CgEnOn_A	242647424	113	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242647424	114	0	0
T26	0	3	0	0
T28	628	2	0	0
T29	3004	0	0	0
T30	1454	0	0	0
T31	643	0	0	0
T32	1077	0	0	0
T33	3373	0	0	0
T34	1022	0	0	0
T44	0	5	0	0
T68	692	0	0	0
T69	3870	0	0	0
T104	786	0	0	0
T161	0	2	0	0
T192	0	2	0	0
T193	0	1	0	0
T194	0	5	0	0
T195	0	2	0	0
T196	0	2	0	0
T197	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242647424	113	0	0
T26	0	3	0	0
T28	628	2	0	0
T29	3004	0	0	0
T30	1454	0	0	0
T31	643	0	0	0
T32	1077	0	0	0
T33	3373	0	0	0
T34	1022	0	0	0
T44	0	5	0	0
T68	692	0	0	0
T69	3870	0	0	0
T104	786	0	0	0
T161	0	2	0	0
T192	0	2	0	0
T193	0	1	0	0
T194	0	5	0	0
T195	0	2	0	0
T196	0	2	0	0
T197	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T53,T26
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	118354443	7929	0	0
CgEnOn_A	118354443	5688	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118354443	7929	0	0
T4	405	2	0	0
T5	3422	1	0	0
T6	341	2	0	0
T28	296	5	0	0
T29	1486	1	0	0
T30	733	1	0	0
T31	298	1	0	0
T32	519	1	0	0
T33	1717	1	0	0
T34	542	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118354443	5688	0	0
T4	405	1	0	0
T5	3422	0	0	0
T6	341	1	0	0
T21	0	1	0	0
T25	0	11	0	0
T26	0	3	0	0
T28	296	4	0	0
T29	1486	0	0	0
T30	733	0	0	0
T31	298	0	0	0
T32	519	0	0	0
T33	1717	0	0	0
T34	542	0	0	0
T51	0	14	0	0
T53	0	1	0	0
T65	0	1	0	0
T68	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T53,T26
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	236710199	7989	0	0
CgEnOn_A	236710199	5748	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236710199	7989	0	0
T4	810	2	0	0
T5	6844	1	0	0
T6	682	3	0	0
T28	593	5	0	0
T29	2971	1	0	0
T30	1466	1	0	0
T31	598	1	0	0
T32	1037	1	0	0
T33	3435	1	0	0
T34	1088	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236710199	5748	0	0
T4	810	1	0	0
T5	6844	0	0	0
T6	682	2	0	0
T21	0	1	0	0
T25	0	14	0	0
T26	0	3	0	0
T28	593	4	0	0
T29	2971	0	0	0
T30	1466	0	0	0
T31	598	0	0	0
T32	1037	0	0	0
T33	3435	0	0	0
T34	1088	0	0	0
T51	0	16	0	0
T53	0	1	0	0
T65	0	1	0	0
T68	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T53,T26
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	474934572	7990	0	0
CgEnOn_A	474934572	5742	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474934572	7990	0	0
T4	1644	2	0	0
T5	7874	1	0	0
T6	1402	2	0	0
T28	1238	5	0	0
T29	6008	1	0	0
T30	2907	1	0	0
T31	1286	1	0	0
T32	2154	1	0	0
T33	6747	1	0	0
T34	2044	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	474934572	5742	0	0
T4	1644	1	0	0
T5	7874	0	0	0
T6	1402	1	0	0
T21	0	1	0	0
T25	0	12	0	0
T26	0	3	0	0
T28	1238	4	0	0
T29	6008	0	0	0
T30	2907	0	0	0
T31	1286	0	0	0
T32	2154	0	0	0
T33	6747	0	0	0
T34	2044	0	0	0
T51	0	17	0	0
T53	0	1	0	0
T65	0	1	0	0
T68	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T26,T44
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	242647424	7943	0	0
CgEnOn_A	242647424	5691	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242647424	7943	0	0
T4	822	2	0	0
T5	3937	1	0	0
T6	701	3	0	0
T28	628	3	0	0
T29	3004	1	0	0
T30	1454	1	0	0
T31	643	1	0	0
T32	1077	1	0	0
T33	3373	1	0	0
T34	1022	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242647424	5691	0	0
T4	822	1	0	0
T5	3937	0	0	0
T6	701	2	0	0
T21	0	1	0	0
T25	0	13	0	0
T26	0	3	0	0
T28	628	2	0	0
T29	3004	0	0	0
T30	1454	0	0	0
T31	643	0	0	0
T32	1077	0	0	0
T33	3373	0	0	0
T34	1022	0	0	0
T51	0	17	0	0
T65	0	1	0	0
T68	0	1	0	0
T198	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T55
1	0	Covered	T4,T29,T32
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	505769449	4069	0	0
CgEnOn_A	505769449	4066	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505769449	4069	0	0
T4	1713	1	0	0
T5	8203	0	0	0
T6	1459	0	0	0
T21	0	1	0	0
T26	0	4	0	0
T28	1285	3	0	0
T29	6259	2	0	0
T30	3029	0	0	0
T31	1340	0	0	0
T32	2243	3	0	0
T33	7028	0	0	0
T34	2129	0	0	0
T52	0	4	0	0
T54	0	2	0	0
T60	0	8	0	0
T68	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505769449	4066	0	0
T4	1713	1	0	0
T5	8203	0	0	0
T6	1459	0	0	0
T21	0	1	0	0
T26	0	4	0	0
T28	1285	3	0	0
T29	6259	2	0	0
T30	3029	0	0	0
T31	1340	0	0	0
T32	2243	3	0	0
T33	7028	0	0	0
T34	2129	0	0	0
T52	0	4	0	0
T54	0	2	0	0
T60	0	8	0	0
T68	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T55
1	0	Covered	T4,T29,T32
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	505769449	3977	0	0
CgEnOn_A	505769449	3974	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505769449	3977	0	0
T4	1713	1	0	0
T5	8203	0	0	0
T6	1459	0	0	0
T21	0	1	0	0
T24	0	1	0	0
T26	0	4	0	0
T28	1285	3	0	0
T29	6259	4	0	0
T30	3029	0	0	0
T31	1340	0	0	0
T32	2243	5	0	0
T33	7028	0	0	0
T34	2129	0	0	0
T52	0	5	0	0
T54	0	1	0	0
T68	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505769449	3974	0	0
T4	1713	1	0	0
T5	8203	0	0	0
T6	1459	0	0	0
T21	0	1	0	0
T24	0	1	0	0
T26	0	4	0	0
T28	1285	3	0	0
T29	6259	4	0	0
T30	3029	0	0	0
T31	1340	0	0	0
T32	2243	5	0	0
T33	7028	0	0	0
T34	2129	0	0	0
T52	0	5	0	0
T54	0	1	0	0
T68	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T55
1	0	Covered	T4,T29,T32
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	505769449	4066	0	0
CgEnOn_A	505769449	4063	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505769449	4066	0	0
T4	1713	1	0	0
T5	8203	0	0	0
T6	1459	0	0	0
T21	0	1	0	0
T24	0	1	0	0
T26	0	4	0	0
T28	1285	3	0	0
T29	6259	2	0	0
T30	3029	0	0	0
T31	1340	0	0	0
T32	2243	3	0	0
T33	7028	0	0	0
T34	2129	0	0	0
T52	0	3	0	0
T54	0	2	0	0
T68	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505769449	4063	0	0
T4	1713	1	0	0
T5	8203	0	0	0
T6	1459	0	0	0
T21	0	1	0	0
T24	0	1	0	0
T26	0	4	0	0
T28	1285	3	0	0
T29	6259	2	0	0
T30	3029	0	0	0
T31	1340	0	0	0
T32	2243	3	0	0
T33	7028	0	0	0
T34	2129	0	0	0
T52	0	3	0	0
T54	0	2	0	0
T68	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T55
1	0	Covered	T4,T29,T32
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	505769449	3960	0	0
CgEnOn_A	505769449	3957	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505769449	3960	0	0
T4	1713	1	0	0
T5	8203	0	0	0
T6	1459	0	0	0
T21	0	1	0	0
T24	0	1	0	0
T26	0	4	0	0
T28	1285	3	0	0
T29	6259	4	0	0
T30	3029	0	0	0
T31	1340	0	0	0
T32	2243	4	0	0
T33	7028	0	0	0
T34	2129	0	0	0
T52	0	5	0	0
T54	0	2	0	0
T68	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505769449	3957	0	0
T4	1713	1	0	0
T5	8203	0	0	0
T6	1459	0	0	0
T21	0	1	0	0
T24	0	1	0	0
T26	0	4	0	0
T28	1285	3	0	0
T29	6259	4	0	0
T30	3029	0	0	0
T31	1340	0	0	0
T32	2243	4	0	0
T33	7028	0	0	0
T34	2129	0	0	0
T52	0	5	0	0
T54	0	2	0	0
T68	0	1	0	0