Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	112162047	399	0	0
StatusRise_A	112162047	399	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112162047	399	0	0
T1	149751	0	0	0
T19	0	7	0	0
T27	3150	5	0	0
T28	6699	0	0	0
T29	8661	0	0	0
T30	5202	0	0	0
T31	3708	0	0	0
T32	4020	0	0	0
T33	6045	0	0	0
T38	0	17	0	0
T49	5088	0	0	0
T50	5934	0	0	0
T149	0	5	0	0
T165	0	7	0	0
T172	0	14	0	0
T182	0	7	0	0
T183	0	10	0	0
T184	0	3	0	0
T185	0	9	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112162047	399	0	0
T1	149751	0	0	0
T19	0	7	0	0
T27	3150	5	0	0
T28	6699	0	0	0
T29	8661	0	0	0
T30	5202	0	0	0
T31	3708	0	0	0
T32	4020	0	0	0
T33	6045	0	0	0
T38	0	17	0	0
T49	5088	0	0	0
T50	5934	0	0	0
T149	0	5	0	0
T165	0	7	0	0
T172	0	14	0	0
T182	0	7	0	0
T183	0	10	0	0
T184	0	3	0	0
T185	0	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	37387349	135	0	0
StatusRise_A	37387349	135	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37387349	135	0	0
T1	49917	0	0	0
T19	0	2	0	0
T27	1050	2	0	0
T28	2233	0	0	0
T29	2887	0	0	0
T30	1734	0	0	0
T31	1236	0	0	0
T32	1340	0	0	0
T33	2015	0	0	0
T38	0	4	0	0
T49	1696	0	0	0
T50	1978	0	0	0
T149	0	3	0	0
T165	0	2	0	0
T172	0	5	0	0
T182	0	2	0	0
T183	0	4	0	0
T184	0	1	0	0
T185	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37387349	135	0	0
T1	49917	0	0	0
T19	0	2	0	0
T27	1050	2	0	0
T28	2233	0	0	0
T29	2887	0	0	0
T30	1734	0	0	0
T31	1236	0	0	0
T32	1340	0	0	0
T33	2015	0	0	0
T38	0	4	0	0
T49	1696	0	0	0
T50	1978	0	0	0
T149	0	3	0	0
T165	0	2	0	0
T172	0	5	0	0
T182	0	2	0	0
T183	0	4	0	0
T184	0	1	0	0
T185	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	37387349	125	0	0
StatusRise_A	37387349	125	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37387349	125	0	0
T1	49917	0	0	0
T19	0	2	0	0
T27	1050	1	0	0
T28	2233	0	0	0
T29	2887	0	0	0
T30	1734	0	0	0
T31	1236	0	0	0
T32	1340	0	0	0
T33	2015	0	0	0
T38	0	7	0	0
T49	1696	0	0	0
T50	1978	0	0	0
T149	0	1	0	0
T165	0	3	0	0
T172	0	3	0	0
T182	0	2	0	0
T183	0	3	0	0
T184	0	1	0	0
T185	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37387349	125	0	0
T1	49917	0	0	0
T19	0	2	0	0
T27	1050	1	0	0
T28	2233	0	0	0
T29	2887	0	0	0
T30	1734	0	0	0
T31	1236	0	0	0
T32	1340	0	0	0
T33	2015	0	0	0
T38	0	7	0	0
T49	1696	0	0	0
T50	1978	0	0	0
T149	0	1	0	0
T165	0	3	0	0
T172	0	3	0	0
T182	0	2	0	0
T183	0	3	0	0
T184	0	1	0	0
T185	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	37387349	139	0	0
StatusRise_A	37387349	139	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37387349	139	0	0
T1	49917	0	0	0
T19	0	3	0	0
T27	1050	2	0	0
T28	2233	0	0	0
T29	2887	0	0	0
T30	1734	0	0	0
T31	1236	0	0	0
T32	1340	0	0	0
T33	2015	0	0	0
T38	0	6	0	0
T49	1696	0	0	0
T50	1978	0	0	0
T149	0	1	0	0
T165	0	2	0	0
T172	0	6	0	0
T182	0	3	0	0
T183	0	3	0	0
T184	0	1	0	0
T185	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37387349	139	0	0
T1	49917	0	0	0
T19	0	3	0	0
T27	1050	2	0	0
T28	2233	0	0	0
T29	2887	0	0	0
T30	1734	0	0	0
T31	1236	0	0	0
T32	1340	0	0	0
T33	2015	0	0	0
T38	0	6	0	0
T49	1696	0	0	0
T50	1978	0	0	0
T149	0	1	0	0
T165	0	2	0	0
T172	0	6	0	0
T182	0	3	0	0
T183	0	3	0	0
T184	0	1	0	0
T185	0	4	0	0