Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T2,T19
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	951014638	31215	0	0
CgEnOn_A	951014638	22976	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	951014638	31215	0	0
T1	189683	0	0	0
T4	115800	7	0	0
T5	99832	3	0	0
T6	12601	47	0	0
T19	0	12	0	0
T20	0	11	0	0
T27	21928	13	0	0
T28	23848	9	0	0
T29	31980	8	0	0
T30	127616	3	0	0
T31	41710	3	0	0
T32	61676	3	0	0
T33	158976	3	0	0
T38	0	39	0	0
T49	9149	0	0	0
T50	9097	1	0	0
T149	0	5	0	0
T165	0	15	0	0
T172	0	15	0	0
T182	0	10	0	0
T183	0	15	0	0
T184	0	5	0	0
T185	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	951014638	22976	0	0
T1	189683	0	0	0
T4	115800	4	0	0
T5	99832	0	0	0
T6	12601	44	0	0
T18	0	6	0	0
T19	0	18	0	0
T20	0	11	0	0
T21	0	1	0	0
T27	21928	10	0	0
T28	23848	6	0	0
T29	31980	5	0	0
T30	127616	0	0	0
T31	41710	0	0	0
T32	61676	0	0	0
T33	158976	0	0	0
T38	0	60	0	0
T39	0	6	0	0
T49	9149	0	0	0
T50	9097	4	0	0
T70	0	3	0	0
T93	0	4	0	0
T149	0	5	0	0
T165	0	15	0	0
T172	0	15	0	0
T182	0	10	0	0
T183	0	15	0	0
T184	0	5	0	0
T185	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T2,T19
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	39845802	144	0	0
CgEnOn_A	39845802	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39845802	144	0	0
T1	15253	0	0	0
T19	0	2	0	0
T27	956	1	0	0
T28	1005	0	0	0
T29	1389	0	0	0
T30	6230	0	0	0
T31	1845	0	0	0
T32	3019	0	0	0
T33	7785	0	0	0
T38	0	7	0	0
T49	912	0	0	0
T50	917	0	0	0
T149	0	1	0	0
T165	0	3	0	0
T172	0	3	0	0
T182	0	2	0	0
T183	0	3	0	0
T184	0	1	0	0
T185	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39845802	144	0	0
T1	15253	0	0	0
T19	0	2	0	0
T27	956	1	0	0
T28	1005	0	0	0
T29	1389	0	0	0
T30	6230	0	0	0
T31	1845	0	0	0
T32	3019	0	0	0
T33	7785	0	0	0
T38	0	7	0	0
T49	912	0	0	0
T50	917	0	0	0
T149	0	1	0	0
T165	0	3	0	0
T172	0	3	0	0
T182	0	2	0	0
T183	0	3	0	0
T184	0	1	0	0
T185	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T2,T19
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	19922488	144	0	0
CgEnOn_A	19922488	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19922488	144	0	0
T1	7626	0	0	0
T19	0	2	0	0
T27	478	1	0	0
T28	502	0	0	0
T29	694	0	0	0
T30	3113	0	0	0
T31	922	0	0	0
T32	1509	0	0	0
T33	3891	0	0	0
T38	0	7	0	0
T49	456	0	0	0
T50	458	0	0	0
T149	0	1	0	0
T165	0	3	0	0
T172	0	3	0	0
T182	0	2	0	0
T183	0	3	0	0
T184	0	1	0	0
T185	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19922488	144	0	0
T1	7626	0	0	0
T19	0	2	0	0
T27	478	1	0	0
T28	502	0	0	0
T29	694	0	0	0
T30	3113	0	0	0
T31	922	0	0	0
T32	1509	0	0	0
T33	3891	0	0	0
T38	0	7	0	0
T49	456	0	0	0
T50	458	0	0	0
T149	0	1	0	0
T165	0	3	0	0
T172	0	3	0	0
T182	0	2	0	0
T183	0	3	0	0
T184	0	1	0	0
T185	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T2,T19
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	19922488	144	0	0
CgEnOn_A	19922488	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19922488	144	0	0
T1	7626	0	0	0
T19	0	2	0	0
T27	478	1	0	0
T28	502	0	0	0
T29	694	0	0	0
T30	3113	0	0	0
T31	922	0	0	0
T32	1509	0	0	0
T33	3891	0	0	0
T38	0	7	0	0
T49	456	0	0	0
T50	458	0	0	0
T149	0	1	0	0
T165	0	3	0	0
T172	0	3	0	0
T182	0	2	0	0
T183	0	3	0	0
T184	0	1	0	0
T185	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19922488	144	0	0
T1	7626	0	0	0
T19	0	2	0	0
T27	478	1	0	0
T28	502	0	0	0
T29	694	0	0	0
T30	3113	0	0	0
T31	922	0	0	0
T32	1509	0	0	0
T33	3891	0	0	0
T38	0	7	0	0
T49	456	0	0	0
T50	458	0	0	0
T149	0	1	0	0
T165	0	3	0	0
T172	0	3	0	0
T182	0	2	0	0
T183	0	3	0	0
T184	0	1	0	0
T185	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T2,T19
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	19922488	144	0	0
CgEnOn_A	19922488	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19922488	144	0	0
T1	7626	0	0	0
T19	0	2	0	0
T27	478	1	0	0
T28	502	0	0	0
T29	694	0	0	0
T30	3113	0	0	0
T31	922	0	0	0
T32	1509	0	0	0
T33	3891	0	0	0
T38	0	7	0	0
T49	456	0	0	0
T50	458	0	0	0
T149	0	1	0	0
T165	0	3	0	0
T172	0	3	0	0
T182	0	2	0	0
T183	0	3	0	0
T184	0	1	0	0
T185	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19922488	144	0	0
T1	7626	0	0	0
T19	0	2	0	0
T27	478	1	0	0
T28	502	0	0	0
T29	694	0	0	0
T30	3113	0	0	0
T31	922	0	0	0
T32	1509	0	0	0
T33	3891	0	0	0
T38	0	7	0	0
T49	456	0	0	0
T50	458	0	0	0
T149	0	1	0	0
T165	0	3	0	0
T172	0	3	0	0
T182	0	2	0	0
T183	0	3	0	0
T184	0	1	0	0
T185	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T2,T19
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	81234049	144	0	0
CgEnOn_A	81234049	129	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81234049	144	0	0
T1	30639	0	0	0
T19	0	2	0	0
T27	1964	1	0	0
T28	2144	0	0	0
T29	2857	0	0	0
T30	11103	0	0	0
T31	3712	0	0	0
T32	5362	0	0	0
T33	13820	0	0	0
T38	0	7	0	0
T49	1917	0	0	0
T50	1900	0	0	0
T149	0	1	0	0
T165	0	3	0	0
T172	0	3	0	0
T182	0	2	0	0
T183	0	3	0	0
T184	0	1	0	0
T185	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81234049	129	0	0
T1	30639	0	0	0
T19	0	2	0	0
T27	1964	1	0	0
T28	2144	0	0	0
T29	2857	0	0	0
T30	11103	0	0	0
T31	3712	0	0	0
T32	5362	0	0	0
T33	13820	0	0	0
T38	0	7	0	0
T49	1917	0	0	0
T50	1900	0	0	0
T149	0	1	0	0
T165	0	3	0	0
T172	0	3	0	0
T182	0	2	0	0
T183	0	3	0	0
T184	0	1	0	0
T185	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T2,T19
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	90389067	139	0	0
CgEnOn_A	90389067	137	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90389067	139	0	0
T1	49917	0	0	0
T19	0	2	0	0
T27	2027	2	0	0
T28	2233	0	0	0
T29	2976	0	0	0
T30	11566	0	0	0
T31	3866	0	0	0
T32	5586	0	0	0
T33	14397	0	0	0
T38	0	4	0	0
T49	1997	0	0	0
T50	1978	0	0	0
T149	0	3	0	0
T165	0	2	0	0
T172	0	5	0	0
T182	0	2	0	0
T183	0	4	0	0
T184	0	1	0	0
T185	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90389067	137	0	0
T1	49917	0	0	0
T19	0	2	0	0
T27	2027	2	0	0
T28	2233	0	0	0
T29	2976	0	0	0
T30	11566	0	0	0
T31	3866	0	0	0
T32	5586	0	0	0
T33	14397	0	0	0
T38	0	4	0	0
T49	1997	0	0	0
T50	1978	0	0	0
T149	0	3	0	0
T165	0	2	0	0
T172	0	5	0	0
T182	0	2	0	0
T183	0	4	0	0
T184	0	1	0	0
T185	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T2,T19
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	90389067	139	0	0
CgEnOn_A	90389067	137	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90389067	139	0	0
T1	49917	0	0	0
T19	0	2	0	0
T27	2027	2	0	0
T28	2233	0	0	0
T29	2976	0	0	0
T30	11566	0	0	0
T31	3866	0	0	0
T32	5586	0	0	0
T33	14397	0	0	0
T38	0	4	0	0
T49	1997	0	0	0
T50	1978	0	0	0
T149	0	3	0	0
T165	0	2	0	0
T172	0	5	0	0
T182	0	2	0	0
T183	0	4	0	0
T184	0	1	0	0
T185	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90389067	137	0	0
T1	49917	0	0	0
T19	0	2	0	0
T27	2027	2	0	0
T28	2233	0	0	0
T29	2976	0	0	0
T30	11566	0	0	0
T31	3866	0	0	0
T32	5586	0	0	0
T33	14397	0	0	0
T38	0	4	0	0
T49	1997	0	0	0
T50	1978	0	0	0
T149	0	3	0	0
T165	0	2	0	0
T172	0	5	0	0
T182	0	2	0	0
T183	0	4	0	0
T184	0	1	0	0
T185	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T2,T19
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	43415291	143	0	0
CgEnOn_A	43415291	140	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43415291	143	0	0
T1	21079	0	0	0
T19	0	3	0	0
T27	1007	2	0	0
T28	1072	0	0	0
T29	1428	0	0	0
T30	5551	0	0	0
T31	1856	0	0	0
T32	2681	0	0	0
T33	6910	0	0	0
T38	0	6	0	0
T49	958	0	0	0
T50	950	0	0	0
T149	0	1	0	0
T165	0	2	0	0
T172	0	6	0	0
T182	0	3	0	0
T183	0	3	0	0
T184	0	1	0	0
T185	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43415291	140	0	0
T1	21079	0	0	0
T19	0	3	0	0
T27	1007	2	0	0
T28	1072	0	0	0
T29	1428	0	0	0
T30	5551	0	0	0
T31	1856	0	0	0
T32	2681	0	0	0
T33	6910	0	0	0
T38	0	6	0	0
T49	958	0	0	0
T50	950	0	0	0
T149	0	1	0	0
T165	0	2	0	0
T172	0	6	0	0
T182	0	3	0	0
T183	0	3	0	0
T184	0	1	0	0
T185	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T19,T38
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	19922488	4820	0	0
CgEnOn_A	19922488	2776	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19922488	4820	0	0
T4	4488	2	0	0
T5	4343	1	0	0
T6	461	15	0	0
T27	478	2	0	0
T28	502	1	0	0
T29	694	1	0	0
T30	3113	1	0	0
T31	922	1	0	0
T32	1509	1	0	0
T33	3891	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19922488	2776	0	0
T4	4488	1	0	0
T5	4343	0	0	0
T6	461	14	0	0
T18	0	2	0	0
T19	0	2	0	0
T27	478	1	0	0
T28	502	0	0	0
T29	694	0	0	0
T30	3113	0	0	0
T31	922	0	0	0
T32	1509	0	0	0
T33	3891	0	0	0
T38	0	7	0	0
T39	0	2	0	0
T50	0	1	0	0
T70	0	1	0	0
T93	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T19,T38
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	39845802	4878	0	0
CgEnOn_A	39845802	2834	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39845802	4878	0	0
T4	8976	2	0	0
T5	8689	1	0	0
T6	923	15	0	0
T27	956	2	0	0
T28	1005	1	0	0
T29	1389	1	0	0
T30	6230	1	0	0
T31	1845	1	0	0
T32	3019	1	0	0
T33	7785	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39845802	2834	0	0
T4	8976	1	0	0
T5	8689	0	0	0
T6	923	14	0	0
T18	0	2	0	0
T19	0	2	0	0
T27	956	1	0	0
T28	1005	0	0	0
T29	1389	0	0	0
T30	6230	0	0	0
T31	1845	0	0	0
T32	3019	0	0	0
T33	7785	0	0	0
T38	0	7	0	0
T39	0	2	0	0
T50	0	1	0	0
T70	0	1	0	0
T93	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T19,T38
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	81234049	4876	0	0
CgEnOn_A	81234049	2817	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81234049	4876	0	0
T4	18059	2	0	0
T5	15317	1	0	0
T6	1980	17	0	0
T27	1964	2	0	0
T28	2144	1	0	0
T29	2857	1	0	0
T30	11103	1	0	0
T31	3712	1	0	0
T32	5362	1	0	0
T33	13820	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81234049	2817	0	0
T4	18059	1	0	0
T5	15317	0	0	0
T6	1980	16	0	0
T18	0	2	0	0
T19	0	2	0	0
T27	1964	1	0	0
T28	2144	0	0	0
T29	2857	0	0	0
T30	11103	0	0	0
T31	3712	0	0	0
T32	5362	0	0	0
T33	13820	0	0	0
T38	0	7	0	0
T39	0	2	0	0
T50	0	1	0	0
T70	0	1	0	0
T93	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T19,T38
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	43415291	4900	0	0
CgEnOn_A	43415291	2838	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43415291	4900	0	0
T4	9029	2	0	0
T5	7659	1	0	0
T6	989	17	0	0
T27	1007	3	0	0
T28	1072	1	0	0
T29	1428	1	0	0
T30	5551	1	0	0
T31	1856	1	0	0
T32	2681	1	0	0
T33	6910	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43415291	2838	0	0
T4	9029	1	0	0
T5	7659	0	0	0
T6	989	16	0	0
T18	0	3	0	0
T19	0	3	0	0
T27	1007	2	0	0
T28	1072	0	0	0
T29	1428	0	0	0
T30	5551	0	0	0
T31	1856	0	0	0
T32	2681	0	0	0
T33	6910	0	0	0
T38	0	6	0	0
T39	0	2	0	0
T50	0	1	0	0
T70	0	1	0	0
T93	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T2,T19
1	0	Covered	T4,T28,T29
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	90389067	2640	0	0
CgEnOn_A	90389067	2638	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90389067	2640	0	0
T4	18812	1	0	0
T5	15956	0	0	0
T6	2062	0	0	0
T19	0	2	0	0
T20	0	11	0	0
T21	0	1	0	0
T27	2027	2	0	0
T28	2233	6	0	0
T29	2976	5	0	0
T30	11566	0	0	0
T31	3866	0	0	0
T32	5586	0	0	0
T33	14397	0	0	0
T38	0	4	0	0
T50	0	1	0	0
T93	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90389067	2638	0	0
T4	18812	1	0	0
T5	15956	0	0	0
T6	2062	0	0	0
T19	0	2	0	0
T20	0	11	0	0
T21	0	1	0	0
T27	2027	2	0	0
T28	2233	6	0	0
T29	2976	5	0	0
T30	11566	0	0	0
T31	3866	0	0	0
T32	5586	0	0	0
T33	14397	0	0	0
T38	0	4	0	0
T50	0	1	0	0
T93	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T2,T19
1	0	Covered	T4,T28,T29
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	90389067	2609	0	0
CgEnOn_A	90389067	2607	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90389067	2609	0	0
T4	18812	1	0	0
T5	15956	0	0	0
T6	2062	0	0	0
T19	0	2	0	0
T20	0	7	0	0
T21	0	1	0	0
T27	2027	2	0	0
T28	2233	8	0	0
T29	2976	7	0	0
T30	11566	0	0	0
T31	3866	0	0	0
T32	5586	0	0	0
T33	14397	0	0	0
T38	0	4	0	0
T50	0	1	0	0
T93	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90389067	2607	0	0
T4	18812	1	0	0
T5	15956	0	0	0
T6	2062	0	0	0
T19	0	2	0	0
T20	0	7	0	0
T21	0	1	0	0
T27	2027	2	0	0
T28	2233	8	0	0
T29	2976	7	0	0
T30	11566	0	0	0
T31	3866	0	0	0
T32	5586	0	0	0
T33	14397	0	0	0
T38	0	4	0	0
T50	0	1	0	0
T93	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T2,T19
1	0	Covered	T4,T28,T29
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	90389067	2724	0	0
CgEnOn_A	90389067	2722	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90389067	2724	0	0
T4	18812	1	0	0
T5	15956	0	0	0
T6	2062	0	0	0
T19	0	2	0	0
T20	0	6	0	0
T27	2027	2	0	0
T28	2233	4	0	0
T29	2976	8	0	0
T30	11566	0	0	0
T31	3866	0	0	0
T32	5586	0	0	0
T33	14397	0	0	0
T38	0	4	0	0
T40	0	2	0	0
T50	0	1	0	0
T93	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90389067	2722	0	0
T4	18812	1	0	0
T5	15956	0	0	0
T6	2062	0	0	0
T19	0	2	0	0
T20	0	6	0	0
T27	2027	2	0	0
T28	2233	4	0	0
T29	2976	8	0	0
T30	11566	0	0	0
T31	3866	0	0	0
T32	5586	0	0	0
T33	14397	0	0	0
T38	0	4	0	0
T40	0	2	0	0
T50	0	1	0	0
T93	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T27,T2,T19
1	0	Covered	T4,T28,T29
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	90389067	2627	0	0
CgEnOn_A	90389067	2625	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90389067	2627	0	0
T4	18812	1	0	0
T5	15956	0	0	0
T6	2062	0	0	0
T19	0	2	0	0
T20	0	7	0	0
T21	0	1	0	0
T27	2027	2	0	0
T28	2233	9	0	0
T29	2976	6	0	0
T30	11566	0	0	0
T31	3866	0	0	0
T32	5586	0	0	0
T33	14397	0	0	0
T38	0	4	0	0
T50	0	1	0	0
T93	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90389067	2625	0	0
T4	18812	1	0	0
T5	15956	0	0	0
T6	2062	0	0	0
T19	0	2	0	0
T20	0	7	0	0
T21	0	1	0	0
T27	2027	2	0	0
T28	2233	9	0	0
T29	2976	6	0	0
T30	11566	0	0	0
T31	3866	0	0	0
T32	5586	0	0	0
T33	14397	0	0	0
T38	0	4	0	0
T50	0	1	0	0
T93	0	1	0	0