FLASH_CTRL Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: `00fe426038`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.570m	78.844us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.920s	26.013us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.740s	171.750us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.350s	55.467us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.391m	3.419ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	51.560s	2.065ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.790s	100.148us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.350s	55.467us	20	20	100.00
		flash_ctrl_csr_aliasing	51.560s	2.065ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.630s	17.208us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.720s	37.089us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.730s	48.949us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.874m	122.025us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	42.538m	680.382ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.338m	350.320ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.110s	15.829us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	51.241m	308.222ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.369m	5.402ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.618m	5.000ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.237h	50.869ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.512m	705.165us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.380s	16.890us	23	40	57.50
		flash_ctrl_rw_evict_all_en	32.980s	47.731us	37	40	92.50
		flash_ctrl_re_evict	41.500s	152.429us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.876m	8.147ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.876m	8.147ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	20.934m	15.611ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	30.810s	3.138ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	23.703m	18.329ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	45.198m	14.368ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	18.254m	821.972us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	52.338m	7.551ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.830s	15.169us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.386m	2.821ms	4	5	80.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.430s	90.046us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.780s	53.693us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	16.534m	959.811us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.267m	12.991ms	50	50	100.00
		flash_ctrl_otp_reset	2.283m	136.353us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	42.538m	680.382ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.190m	35.681ms	38	40	95.00
		flash_ctrl_intr_wr	1.374m	10.389ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	7.214m	24.576ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	5.055m	146.566ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.484m	1.241ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.375m	16.413ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.890s	18.650us	3	5	60.00
		flash_ctrl_ro_derr	2.802m	1.043ms	10	10	100.00
		flash_ctrl_rw_derr	12.400m	15.030ms	8	10	80.00
		flash_ctrl_derr_detect	1.800m	127.530us	5	5	100.00
		flash_ctrl_integrity	13.380m	25.025ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.950s	81.454us	3	5	60.00
		flash_ctrl_ro_serr	2.757m	7.068ms	10	10	100.00
		flash_ctrl_rw_serr	11.149m	8.483ms	7	10	70.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	2.085m	5.106ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.884m	4.423ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.130m	2.925ms	20	20	100.00
		flash_ctrl_write_word_sweep	13.980s	4.760us	0	1	0.00
		flash_ctrl_read_word_sweep	14.150s	94.431us	1	1	100.00
		flash_ctrl_ro	2.197m	2.941ms	20	20	100.00
		flash_ctrl_rw	13.035m	6.539ms	15	20	75.00
V2	filesystem_support	flash_ctrl_fs_sup	37.780s	1.201ms	0	5	0.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.905m	163.832ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.144m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.400s	72.010us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.880s	47.887us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.210s	124.971us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.210s	124.971us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.740s	171.750us	5	5	100.00
		flash_ctrl_csr_rw	17.350s	55.467us	20	20	100.00
		flash_ctrl_csr_aliasing	51.560s	2.065ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.780s	170.693us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.740s	171.750us	5	5	100.00
		flash_ctrl_csr_rw	17.350s	55.467us	20	20	100.00
		flash_ctrl_csr_aliasing	51.560s	2.065ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.780s	170.693us	20	20	100.00
V2		TOTAL			970	1013	95.76
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.230s	27.694us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.230s	27.694us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.230s	27.694us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.230s	27.694us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.070s	31.487us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.389h	1.335ms	5	5	100.00
		flash_ctrl_tl_intg_err	16.749m	852.499us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	16.749m	852.499us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	16.749m	852.499us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	33.060s	64.006us	3	3	100.00
		flash_ctrl_wr_intg	15.490s	110.653us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.570m	78.844us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.283m	136.353us	80	80	100.00
		flash_ctrl_disable	23.430s	90.046us	50	50	100.00
		flash_ctrl_sec_info_access	1.388m	3.683ms	50	50	100.00
		flash_ctrl_connect	16.780s	53.693us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.250s	39.932us	2	5	40.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.350s	55.467us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.230s	27.694us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.350s	55.467us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.230s	27.694us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.350s	55.467us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.230s	27.694us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.430s	90.046us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	33.060s	64.006us	3	3	100.00
		flash_ctrl_access_after_disable	13.720s	22.865us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.430s	90.046us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	30.810s	3.138ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	13.035m	6.539ms	15	20	75.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.149m	8.483ms	7	10	70.00
		flash_ctrl_rw_derr	12.400m	15.030ms	8	10	80.00
		flash_ctrl_integrity	13.380m	25.025ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	42.538m	680.382ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.389h	1.335ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.389h	1.335ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.389h	1.335ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.389h	1.335ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	20.570s	909.079us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.110s	44.496us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.270s	44.433us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.389h	1.335ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.389h	1.335ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.389h	1.335ms	5	5	100.00
V2S		TOTAL			141	144	97.92
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.410s	50.506us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1232	1278	96.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	44	80.00
V2S	12	12	11	91.67
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.48	95.84	94.26	98.85	91.84	98.31	98.10	98.18

Failure Buckets

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 19 failures:

Test flash_ctrl_rw_evict has 17 failures.

5.flash_ctrl_rw_evict.13744600447865407285836841218424920468212973841346251370558734357800593173448
Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 8305.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00032ba0
  UVM_INFO @ 8305.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.flash_ctrl_rw_evict.28672312068094113300657396586793462316834107997560718663053154526019816814516
Line 298, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 25007.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000036d8
  UVM_INFO @ 25007.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 15 more failures.

Test flash_ctrl_rw_evict_all_en has 2 failures.

25.flash_ctrl_rw_evict_all_en.61997800425505468232515913543695787986766154530403495697798199750152224917454
Line 295, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 28384.7 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x0004f190
  UVM_INFO @ 28384.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.flash_ctrl_rw_evict_all_en.108431607968159616108243352791918768213118350398106079012222805823529691860114
Line 290, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 74730.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00049588
  UVM_INFO @ 74730.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 6 failures:
- Test flash_ctrl_fs_sup has 5 failures.
  - 0.flash_ctrl_fs_sup.33931224737261261896154736430682106414749515175144999522999629388458853232095
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_fs_sup/latest/run.log
```
  UVM_ERROR @ 266352.1 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 266352.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.flash_ctrl_fs_sup.97004698135554614466446809848703837261384142083664385769802319875593010032458
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_fs_sup/latest/run.log
```
  UVM_ERROR @ 526526.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 526526.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
- Test flash_ctrl_read_word_sweep_serr has 1 failures.
  - 3.flash_ctrl_read_word_sweep_serr.51345813482873432083841543494119745637843252406052403452030313497210047989753
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_serr/latest/run.log
```
  UVM_ERROR @ 4601.9 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 4601.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 5 failures:
- Test flash_ctrl_rw has 4 failures.
  - 1.flash_ctrl_rw.22740320864395460835875433266464162825855804214761091435883315030002793802949
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:53fef9ab-0a06-42bd-a969-0c7298850ea4
```
  - 3.flash_ctrl_rw.5623264171051006376229835748218065163842622710187675571173534243343861023252
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw/latest/run.log
```
  Job ID: smart:4baa60c8-95cd-4d3b-b742-fbfaeeb6fdb1
```
  - ... and 2 more failures.
- Test flash_ctrl_rw_serr has 1 failures.
  - 8.flash_ctrl_rw_serr.38792027963172014749120759797289414974549835162613739702801924516576921004567
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest/run.log
```
  Job ID: smart:6fa302d4-ac9c-4445-8543-843ffe0fc24a
```
Error-[CNST-CIF] Constraints inconsistency failure has 3 failures:
- Test flash_ctrl_config_regwen has 3 failures.
  - 0.flash_ctrl_config_regwen.13280948513557742319733722246072676265716921562553212951106088772921369041830
    Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_config_regwen/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 1.flash_ctrl_config_regwen.5809325545787534406345611384960021480495150904506854458778901388504911592416
    Line 328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_flash_ctrl_env_0.1/seq_lib/flash_ctrl_config_regwen_vseq.sv, 46
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 1 more failures.
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 3 failures:
- Test flash_ctrl_read_word_sweep_derr has 2 failures.
  - 2.flash_ctrl_read_word_sweep_derr.102478257811708773727293740746385032030509307946996890111389843645462901940236
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_derr/latest/run.log
```
  UVM_ERROR @ 8858.5 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00003910
  UVM_INFO @ 8858.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.flash_ctrl_read_word_sweep_derr.29955270625671339547886676637023166928363878827974910857882285739796520995214
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_derr/latest/run.log
```
  UVM_ERROR @ 34341.5 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00002848
  UVM_INFO @ 34341.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_derr has 1 failures.
  - 2.flash_ctrl_rw_derr.91251077421745936105585762024093263198168361623467360411935092509078651637965
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 1644109.6 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00002808
  UVM_INFO @ 1644109.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:
- Test flash_ctrl_read_word_sweep_serr has 1 failures.
  - 4.flash_ctrl_read_word_sweep_serr.16365565130361394888243650360707425719642162417549063955979144384755344382498
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_serr/latest/run.log
```
  UVM_ERROR @ 45125.5 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 45125.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw has 1 failures.
  - 6.flash_ctrl_rw.96792980072628444814235242749762830005460888977450909142966774476597797233859
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw/latest/run.log
```
  UVM_ERROR @ 96295.4 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 96295.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 2 failures:

Test flash_ctrl_rw_serr has 2 failures.

5.flash_ctrl_rw_serr.28452033406869662372239774546162253022090136188980170537000270752047695313515
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 2146101.1 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (6198163431316028136145 [0x15000cc018130201ad1] vs 43977095294273189845713 [0x95000cc018130201ad1])
  UVM_INFO @ 2146101.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.flash_ctrl_rw_serr.82755705434539149580617327780307695147833680901976516321115398211271524678709
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest/run.log

  UVM_ERROR @ 320195.8 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (38148467416456602681486 [0x814085604064389808e] vs 40509650657891425288334 [0x894085604064389808e])
  UVM_INFO @ 320195.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_write_word_sweep_vseq.sv:22) [flash_ctrl_write_word_sweep_vseq] Check failed mywd == * (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_write_word_sweep has 1 failures.
  - 0.flash_ctrl_write_word_sweep.48248577169999152546474166363010193955184914384511096644176614503247306070610
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_write_word_sweep/latest/run.log
```
  UVM_ERROR @ 4760.4 ns: (flash_ctrl_write_word_sweep_vseq.sv:22) [uvm_test_top.env.virtual_sequencer.flash_ctrl_write_word_sweep_vseq] Check failed mywd == 1 (2 [0x2] vs 1 [0x1])
  UVM_INFO @ 4760.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_otf_item.sv:247) [rd_scr] ecc error is detected has 1 failures:
- Test flash_ctrl_oversize_error has 1 failures.
  - 3.flash_ctrl_oversize_error.37105963525243052647317319123138056530685506888108875949777055498378804056285
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest/run.log
```
  UVM_ERROR @ 3232911.3 ns: (flash_otf_item.sv:247) [rd_scr] ecc error is detected
  UVM_INFO @ 3232911.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_rw_derr has 1 failures.
  - 6.flash_ctrl_rw_derr.13019078818339017306001670917446855794048362833571056356890410379258431267785
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest/run.log
```
  UVM_ERROR @ 706126.1 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank1] Check failed rcv.mem_wdata == exp.req.prog_full_data (5481025082940326941696 [0x1292080c93800201400] vs 5480989054143307977728 [0x1292000c93800201400])
  UVM_INFO @ 706126.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp cb9c538f_c271b749:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 18.flash_ctrl_intr_rd.5957881720997583194754085228709064722518879593205904320758037105782334446825
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 1744448.8 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    7: obs:exp    cb9c538f_c271b749:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 1744448.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 22.flash_ctrl_rw_evict_all_en.53854487982292624244315967260813093452834080564827116459341656893962617324173
    Line 287, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 168673.6 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 168673.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *dfcade_693b0e00:ffffffff_ffffffff mismatch!! has 1 failures:
- Test flash_ctrl_intr_rd has 1 failures.
  - 33.flash_ctrl_intr_rd.18313392288410862181710124181204697165367486011748777397301340661391083524488
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd/latest/run.log
```
  UVM_ERROR @ 8322423.3 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    2: obs:exp    23dfcade_693b0e00:ffffffff_ffffffff  mismatch!!
  UVM_INFO @ 8322423.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```